0001
0002
0003
0004 #include "i40e.h"
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018 static void i40e_vc_vf_broadcast(struct i40e_pf *pf,
0019 enum virtchnl_ops v_opcode,
0020 i40e_status v_retval, u8 *msg,
0021 u16 msglen)
0022 {
0023 struct i40e_hw *hw = &pf->hw;
0024 struct i40e_vf *vf = pf->vf;
0025 int i;
0026
0027 for (i = 0; i < pf->num_alloc_vfs; i++, vf++) {
0028 int abs_vf_id = vf->vf_id + (int)hw->func_caps.vf_base_id;
0029
0030 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states) &&
0031 !test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states))
0032 continue;
0033
0034
0035
0036
0037 i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
0038 msg, msglen, NULL);
0039 }
0040 }
0041
0042
0043
0044
0045
0046
0047
0048
0049 static u32
0050 i40e_vc_link_speed2mbps(enum i40e_aq_link_speed link_speed)
0051 {
0052 switch (link_speed) {
0053 case I40E_LINK_SPEED_100MB:
0054 return SPEED_100;
0055 case I40E_LINK_SPEED_1GB:
0056 return SPEED_1000;
0057 case I40E_LINK_SPEED_2_5GB:
0058 return SPEED_2500;
0059 case I40E_LINK_SPEED_5GB:
0060 return SPEED_5000;
0061 case I40E_LINK_SPEED_10GB:
0062 return SPEED_10000;
0063 case I40E_LINK_SPEED_20GB:
0064 return SPEED_20000;
0065 case I40E_LINK_SPEED_25GB:
0066 return SPEED_25000;
0067 case I40E_LINK_SPEED_40GB:
0068 return SPEED_40000;
0069 case I40E_LINK_SPEED_UNKNOWN:
0070 return SPEED_UNKNOWN;
0071 }
0072 return SPEED_UNKNOWN;
0073 }
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083 static void i40e_set_vf_link_state(struct i40e_vf *vf,
0084 struct virtchnl_pf_event *pfe, struct i40e_link_status *ls)
0085 {
0086 u8 link_status = ls->link_info & I40E_AQ_LINK_UP;
0087
0088 if (vf->link_forced)
0089 link_status = vf->link_up;
0090
0091 if (vf->driver_caps & VIRTCHNL_VF_CAP_ADV_LINK_SPEED) {
0092 pfe->event_data.link_event_adv.link_speed = link_status ?
0093 i40e_vc_link_speed2mbps(ls->link_speed) : 0;
0094 pfe->event_data.link_event_adv.link_status = link_status;
0095 } else {
0096 pfe->event_data.link_event.link_speed = link_status ?
0097 i40e_virtchnl_link_speed(ls->link_speed) : 0;
0098 pfe->event_data.link_event.link_status = link_status;
0099 }
0100 }
0101
0102
0103
0104
0105
0106
0107
0108 static void i40e_vc_notify_vf_link_state(struct i40e_vf *vf)
0109 {
0110 struct virtchnl_pf_event pfe;
0111 struct i40e_pf *pf = vf->pf;
0112 struct i40e_hw *hw = &pf->hw;
0113 struct i40e_link_status *ls = &pf->hw.phy.link_info;
0114 int abs_vf_id = vf->vf_id + (int)hw->func_caps.vf_base_id;
0115
0116 pfe.event = VIRTCHNL_EVENT_LINK_CHANGE;
0117 pfe.severity = PF_EVENT_SEVERITY_INFO;
0118
0119 i40e_set_vf_link_state(vf, &pfe, ls);
0120
0121 i40e_aq_send_msg_to_vf(hw, abs_vf_id, VIRTCHNL_OP_EVENT,
0122 0, (u8 *)&pfe, sizeof(pfe), NULL);
0123 }
0124
0125
0126
0127
0128
0129
0130
0131 void i40e_vc_notify_link_state(struct i40e_pf *pf)
0132 {
0133 int i;
0134
0135 for (i = 0; i < pf->num_alloc_vfs; i++)
0136 i40e_vc_notify_vf_link_state(&pf->vf[i]);
0137 }
0138
0139
0140
0141
0142
0143
0144
0145 void i40e_vc_notify_reset(struct i40e_pf *pf)
0146 {
0147 struct virtchnl_pf_event pfe;
0148
0149 pfe.event = VIRTCHNL_EVENT_RESET_IMPENDING;
0150 pfe.severity = PF_EVENT_SEVERITY_CERTAIN_DOOM;
0151 i40e_vc_vf_broadcast(pf, VIRTCHNL_OP_EVENT, 0,
0152 (u8 *)&pfe, sizeof(struct virtchnl_pf_event));
0153 }
0154
0155
0156
0157
0158
0159
0160
0161 void i40e_vc_notify_vf_reset(struct i40e_vf *vf)
0162 {
0163 struct virtchnl_pf_event pfe;
0164 int abs_vf_id;
0165
0166
0167 if (!vf || vf->vf_id >= vf->pf->num_alloc_vfs)
0168 return;
0169
0170
0171 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states) &&
0172 !test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states))
0173 return;
0174
0175 abs_vf_id = vf->vf_id + (int)vf->pf->hw.func_caps.vf_base_id;
0176
0177 pfe.event = VIRTCHNL_EVENT_RESET_IMPENDING;
0178 pfe.severity = PF_EVENT_SEVERITY_CERTAIN_DOOM;
0179 i40e_aq_send_msg_to_vf(&vf->pf->hw, abs_vf_id, VIRTCHNL_OP_EVENT,
0180 0, (u8 *)&pfe,
0181 sizeof(struct virtchnl_pf_event), NULL);
0182 }
0183
0184
0185
0186
0187
0188
0189
0190
0191 static void i40e_vc_reset_vf(struct i40e_vf *vf, bool notify_vf)
0192 {
0193 struct i40e_pf *pf = vf->pf;
0194 int i;
0195
0196 if (notify_vf)
0197 i40e_vc_notify_vf_reset(vf);
0198
0199
0200
0201
0202
0203
0204 for (i = 0; i < 20; i++) {
0205
0206
0207
0208 if (test_bit(__I40E_VFS_RELEASING, pf->state))
0209 return;
0210 if (i40e_reset_vf(vf, false))
0211 return;
0212 usleep_range(10000, 20000);
0213 }
0214
0215 if (notify_vf)
0216 dev_warn(&vf->pf->pdev->dev,
0217 "Failed to initiate reset for VF %d after 200 milliseconds\n",
0218 vf->vf_id);
0219 else
0220 dev_dbg(&vf->pf->pdev->dev,
0221 "Failed to initiate reset for VF %d after 200 milliseconds\n",
0222 vf->vf_id);
0223 }
0224
0225
0226
0227
0228
0229
0230
0231
0232 static inline bool i40e_vc_isvalid_vsi_id(struct i40e_vf *vf, u16 vsi_id)
0233 {
0234 struct i40e_pf *pf = vf->pf;
0235 struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
0236
0237 return (vsi && (vsi->vf_id == vf->vf_id));
0238 }
0239
0240
0241
0242
0243
0244
0245
0246
0247
0248 static inline bool i40e_vc_isvalid_queue_id(struct i40e_vf *vf, u16 vsi_id,
0249 u16 qid)
0250 {
0251 struct i40e_pf *pf = vf->pf;
0252 struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
0253
0254 return (vsi && (qid < vsi->alloc_queue_pairs));
0255 }
0256
0257
0258
0259
0260
0261
0262
0263
0264 static inline bool i40e_vc_isvalid_vector_id(struct i40e_vf *vf, u32 vector_id)
0265 {
0266 struct i40e_pf *pf = vf->pf;
0267
0268 return vector_id < pf->hw.func_caps.num_msix_vectors_vf;
0269 }
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281 static u16 i40e_vc_get_pf_queue_id(struct i40e_vf *vf, u16 vsi_id,
0282 u8 vsi_queue_id)
0283 {
0284 struct i40e_pf *pf = vf->pf;
0285 struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
0286 u16 pf_queue_id = I40E_QUEUE_END_OF_LIST;
0287
0288 if (!vsi)
0289 return pf_queue_id;
0290
0291 if (le16_to_cpu(vsi->info.mapping_flags) &
0292 I40E_AQ_VSI_QUE_MAP_NONCONTIG)
0293 pf_queue_id =
0294 le16_to_cpu(vsi->info.queue_mapping[vsi_queue_id]);
0295 else
0296 pf_queue_id = le16_to_cpu(vsi->info.queue_mapping[0]) +
0297 vsi_queue_id;
0298
0299 return pf_queue_id;
0300 }
0301
0302
0303
0304
0305
0306
0307
0308
0309
0310 static u16 i40e_get_real_pf_qid(struct i40e_vf *vf, u16 vsi_id, u16 queue_id)
0311 {
0312 int i;
0313
0314 if (vf->adq_enabled) {
0315
0316
0317
0318
0319 for (i = 0; i < vf->num_tc; i++) {
0320 if (queue_id < vf->ch[i].num_qps) {
0321 vsi_id = vf->ch[i].vsi_id;
0322 break;
0323 }
0324
0325
0326
0327 queue_id -= vf->ch[i].num_qps;
0328 }
0329 }
0330
0331 return i40e_vc_get_pf_queue_id(vf, vsi_id, queue_id);
0332 }
0333
0334
0335
0336
0337
0338
0339
0340
0341
0342 static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id,
0343 struct virtchnl_vector_map *vecmap)
0344 {
0345 unsigned long linklistmap = 0, tempmap;
0346 struct i40e_pf *pf = vf->pf;
0347 struct i40e_hw *hw = &pf->hw;
0348 u16 vsi_queue_id, pf_queue_id;
0349 enum i40e_queue_type qtype;
0350 u16 next_q, vector_id, size;
0351 u32 reg, reg_idx;
0352 u16 itr_idx = 0;
0353
0354 vector_id = vecmap->vector_id;
0355
0356 if (0 == vector_id)
0357 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id);
0358 else
0359 reg_idx = I40E_VPINT_LNKLSTN(
0360 ((pf->hw.func_caps.num_msix_vectors_vf - 1) * vf->vf_id) +
0361 (vector_id - 1));
0362
0363 if (vecmap->rxq_map == 0 && vecmap->txq_map == 0) {
0364
0365 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
0366 goto irq_list_done;
0367 }
0368 tempmap = vecmap->rxq_map;
0369 for_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {
0370 linklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES *
0371 vsi_queue_id));
0372 }
0373
0374 tempmap = vecmap->txq_map;
0375 for_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {
0376 linklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES *
0377 vsi_queue_id + 1));
0378 }
0379
0380 size = I40E_MAX_VSI_QP * I40E_VIRTCHNL_SUPPORTED_QTYPES;
0381 next_q = find_first_bit(&linklistmap, size);
0382 if (unlikely(next_q == size))
0383 goto irq_list_done;
0384
0385 vsi_queue_id = next_q / I40E_VIRTCHNL_SUPPORTED_QTYPES;
0386 qtype = next_q % I40E_VIRTCHNL_SUPPORTED_QTYPES;
0387 pf_queue_id = i40e_get_real_pf_qid(vf, vsi_id, vsi_queue_id);
0388 reg = ((qtype << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) | pf_queue_id);
0389
0390 wr32(hw, reg_idx, reg);
0391
0392 while (next_q < size) {
0393 switch (qtype) {
0394 case I40E_QUEUE_TYPE_RX:
0395 reg_idx = I40E_QINT_RQCTL(pf_queue_id);
0396 itr_idx = vecmap->rxitr_idx;
0397 break;
0398 case I40E_QUEUE_TYPE_TX:
0399 reg_idx = I40E_QINT_TQCTL(pf_queue_id);
0400 itr_idx = vecmap->txitr_idx;
0401 break;
0402 default:
0403 break;
0404 }
0405
0406 next_q = find_next_bit(&linklistmap, size, next_q + 1);
0407 if (next_q < size) {
0408 vsi_queue_id = next_q / I40E_VIRTCHNL_SUPPORTED_QTYPES;
0409 qtype = next_q % I40E_VIRTCHNL_SUPPORTED_QTYPES;
0410 pf_queue_id = i40e_get_real_pf_qid(vf,
0411 vsi_id,
0412 vsi_queue_id);
0413 } else {
0414 pf_queue_id = I40E_QUEUE_END_OF_LIST;
0415 qtype = 0;
0416 }
0417
0418
0419 reg = (vector_id) |
0420 (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
0421 (pf_queue_id << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
0422 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
0423 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
0424 wr32(hw, reg_idx, reg);
0425 }
0426
0427
0428
0429
0430 if ((vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RX_POLLING) &&
0431 (vector_id == 0)) {
0432 reg = rd32(hw, I40E_GLINT_CTL);
0433 if (!(reg & I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK)) {
0434 reg |= I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
0435 wr32(hw, I40E_GLINT_CTL, reg);
0436 }
0437 }
0438
0439 irq_list_done:
0440 i40e_flush(hw);
0441 }
0442
0443
0444
0445
0446
0447
0448 static void i40e_release_iwarp_qvlist(struct i40e_vf *vf)
0449 {
0450 struct i40e_pf *pf = vf->pf;
0451 struct virtchnl_iwarp_qvlist_info *qvlist_info = vf->qvlist_info;
0452 u32 msix_vf;
0453 u32 i;
0454
0455 if (!vf->qvlist_info)
0456 return;
0457
0458 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
0459 for (i = 0; i < qvlist_info->num_vectors; i++) {
0460 struct virtchnl_iwarp_qv_info *qv_info;
0461 u32 next_q_index, next_q_type;
0462 struct i40e_hw *hw = &pf->hw;
0463 u32 v_idx, reg_idx, reg;
0464
0465 qv_info = &qvlist_info->qv_info[i];
0466 if (!qv_info)
0467 continue;
0468 v_idx = qv_info->v_idx;
0469 if (qv_info->ceq_idx != I40E_QUEUE_INVALID_IDX) {
0470
0471
0472
0473 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx;
0474 reg = rd32(hw, I40E_VPINT_CEQCTL(reg_idx));
0475 next_q_index = (reg & I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK)
0476 >> I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT;
0477 next_q_type = (reg & I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK)
0478 >> I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT;
0479
0480 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1);
0481 reg = (next_q_index &
0482 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) |
0483 (next_q_type <<
0484 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);
0485
0486 wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg);
0487 }
0488 }
0489 kfree(vf->qvlist_info);
0490 vf->qvlist_info = NULL;
0491 }
0492
0493
0494
0495
0496
0497
0498
0499
0500 static int i40e_config_iwarp_qvlist(struct i40e_vf *vf,
0501 struct virtchnl_iwarp_qvlist_info *qvlist_info)
0502 {
0503 struct i40e_pf *pf = vf->pf;
0504 struct i40e_hw *hw = &pf->hw;
0505 struct virtchnl_iwarp_qv_info *qv_info;
0506 u32 v_idx, i, reg_idx, reg;
0507 u32 next_q_idx, next_q_type;
0508 u32 msix_vf;
0509 int ret = 0;
0510
0511 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
0512
0513 if (qvlist_info->num_vectors > msix_vf) {
0514 dev_warn(&pf->pdev->dev,
0515 "Incorrect number of iwarp vectors %u. Maximum %u allowed.\n",
0516 qvlist_info->num_vectors,
0517 msix_vf);
0518 ret = -EINVAL;
0519 goto err_out;
0520 }
0521
0522 kfree(vf->qvlist_info);
0523 vf->qvlist_info = kzalloc(struct_size(vf->qvlist_info, qv_info,
0524 qvlist_info->num_vectors - 1),
0525 GFP_KERNEL);
0526 if (!vf->qvlist_info) {
0527 ret = -ENOMEM;
0528 goto err_out;
0529 }
0530 vf->qvlist_info->num_vectors = qvlist_info->num_vectors;
0531
0532 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
0533 for (i = 0; i < qvlist_info->num_vectors; i++) {
0534 qv_info = &qvlist_info->qv_info[i];
0535 if (!qv_info)
0536 continue;
0537
0538
0539 if (!i40e_vc_isvalid_vector_id(vf, qv_info->v_idx)) {
0540 ret = -EINVAL;
0541 goto err_free;
0542 }
0543
0544 v_idx = qv_info->v_idx;
0545
0546 vf->qvlist_info->qv_info[i] = *qv_info;
0547
0548 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1);
0549
0550
0551
0552
0553 reg = rd32(hw, I40E_VPINT_LNKLSTN(reg_idx));
0554 next_q_idx = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) >>
0555 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT);
0556 next_q_type = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK) >>
0557 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);
0558
0559 if (qv_info->ceq_idx != I40E_QUEUE_INVALID_IDX) {
0560 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx;
0561 reg = (I40E_VPINT_CEQCTL_CAUSE_ENA_MASK |
0562 (v_idx << I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) |
0563 (qv_info->itr_idx << I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) |
0564 (next_q_type << I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) |
0565 (next_q_idx << I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT));
0566 wr32(hw, I40E_VPINT_CEQCTL(reg_idx), reg);
0567
0568 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1);
0569 reg = (qv_info->ceq_idx &
0570 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) |
0571 (I40E_QUEUE_TYPE_PE_CEQ <<
0572 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);
0573 wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg);
0574 }
0575
0576 if (qv_info->aeq_idx != I40E_QUEUE_INVALID_IDX) {
0577 reg = (I40E_VPINT_AEQCTL_CAUSE_ENA_MASK |
0578 (v_idx << I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) |
0579 (qv_info->itr_idx << I40E_VPINT_AEQCTL_ITR_INDX_SHIFT));
0580
0581 wr32(hw, I40E_VPINT_AEQCTL(vf->vf_id), reg);
0582 }
0583 }
0584
0585 return 0;
0586 err_free:
0587 kfree(vf->qvlist_info);
0588 vf->qvlist_info = NULL;
0589 err_out:
0590 return ret;
0591 }
0592
0593
0594
0595
0596
0597
0598
0599
0600
0601
0602 static int i40e_config_vsi_tx_queue(struct i40e_vf *vf, u16 vsi_id,
0603 u16 vsi_queue_id,
0604 struct virtchnl_txq_info *info)
0605 {
0606 struct i40e_pf *pf = vf->pf;
0607 struct i40e_hw *hw = &pf->hw;
0608 struct i40e_hmc_obj_txq tx_ctx;
0609 struct i40e_vsi *vsi;
0610 u16 pf_queue_id;
0611 u32 qtx_ctl;
0612 int ret = 0;
0613
0614 if (!i40e_vc_isvalid_vsi_id(vf, info->vsi_id)) {
0615 ret = -ENOENT;
0616 goto error_context;
0617 }
0618 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id);
0619 vsi = i40e_find_vsi_from_id(pf, vsi_id);
0620 if (!vsi) {
0621 ret = -ENOENT;
0622 goto error_context;
0623 }
0624
0625
0626 memset(&tx_ctx, 0, sizeof(struct i40e_hmc_obj_txq));
0627
0628
0629 tx_ctx.base = info->dma_ring_addr / 128;
0630 tx_ctx.qlen = info->ring_len;
0631 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[0]);
0632 tx_ctx.rdylist_act = 0;
0633 tx_ctx.head_wb_ena = info->headwb_enabled;
0634 tx_ctx.head_wb_addr = info->dma_headwb_addr;
0635
0636
0637 ret = i40e_clear_lan_tx_queue_context(hw, pf_queue_id);
0638 if (ret) {
0639 dev_err(&pf->pdev->dev,
0640 "Failed to clear VF LAN Tx queue context %d, error: %d\n",
0641 pf_queue_id, ret);
0642 ret = -ENOENT;
0643 goto error_context;
0644 }
0645
0646
0647 ret = i40e_set_lan_tx_queue_context(hw, pf_queue_id, &tx_ctx);
0648 if (ret) {
0649 dev_err(&pf->pdev->dev,
0650 "Failed to set VF LAN Tx queue context %d error: %d\n",
0651 pf_queue_id, ret);
0652 ret = -ENOENT;
0653 goto error_context;
0654 }
0655
0656
0657 qtx_ctl = I40E_QTX_CTL_VF_QUEUE;
0658 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)
0659 & I40E_QTX_CTL_PF_INDX_MASK);
0660 qtx_ctl |= (((vf->vf_id + hw->func_caps.vf_base_id)
0661 << I40E_QTX_CTL_VFVM_INDX_SHIFT)
0662 & I40E_QTX_CTL_VFVM_INDX_MASK);
0663 wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl);
0664 i40e_flush(hw);
0665
0666 error_context:
0667 return ret;
0668 }
0669
0670
0671
0672
0673
0674
0675
0676
0677
0678
0679 static int i40e_config_vsi_rx_queue(struct i40e_vf *vf, u16 vsi_id,
0680 u16 vsi_queue_id,
0681 struct virtchnl_rxq_info *info)
0682 {
0683 u16 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id);
0684 struct i40e_pf *pf = vf->pf;
0685 struct i40e_vsi *vsi = pf->vsi[vf->lan_vsi_idx];
0686 struct i40e_hw *hw = &pf->hw;
0687 struct i40e_hmc_obj_rxq rx_ctx;
0688 int ret = 0;
0689
0690
0691 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
0692
0693
0694 rx_ctx.base = info->dma_ring_addr / 128;
0695 rx_ctx.qlen = info->ring_len;
0696
0697 if (info->splithdr_enabled) {
0698 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
0699 I40E_RX_SPLIT_IP |
0700 I40E_RX_SPLIT_TCP_UDP |
0701 I40E_RX_SPLIT_SCTP;
0702
0703 if (info->hdr_size > ((2 * 1024) - 64)) {
0704 ret = -EINVAL;
0705 goto error_param;
0706 }
0707 rx_ctx.hbuff = info->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
0708
0709
0710 rx_ctx.dtype = I40E_RX_DTYPE_HEADER_SPLIT;
0711 }
0712
0713
0714 if (info->databuffer_size > ((16 * 1024) - 128)) {
0715 ret = -EINVAL;
0716 goto error_param;
0717 }
0718 rx_ctx.dbuff = info->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
0719
0720
0721 if (info->max_pkt_size >= (16 * 1024) || info->max_pkt_size < 64) {
0722 ret = -EINVAL;
0723 goto error_param;
0724 }
0725 rx_ctx.rxmax = info->max_pkt_size;
0726
0727
0728 if (vsi->info.pvid)
0729 rx_ctx.rxmax += VLAN_HLEN;
0730
0731
0732 rx_ctx.dsize = 1;
0733
0734
0735 rx_ctx.lrxqthresh = 1;
0736 rx_ctx.crcstrip = 1;
0737 rx_ctx.prefena = 1;
0738 rx_ctx.l2tsel = 1;
0739
0740
0741 ret = i40e_clear_lan_rx_queue_context(hw, pf_queue_id);
0742 if (ret) {
0743 dev_err(&pf->pdev->dev,
0744 "Failed to clear VF LAN Rx queue context %d, error: %d\n",
0745 pf_queue_id, ret);
0746 ret = -ENOENT;
0747 goto error_param;
0748 }
0749
0750
0751 ret = i40e_set_lan_rx_queue_context(hw, pf_queue_id, &rx_ctx);
0752 if (ret) {
0753 dev_err(&pf->pdev->dev,
0754 "Failed to set VF LAN Rx queue context %d error: %d\n",
0755 pf_queue_id, ret);
0756 ret = -ENOENT;
0757 goto error_param;
0758 }
0759
0760 error_param:
0761 return ret;
0762 }
0763
0764
0765
0766
0767
0768
0769
0770
0771 static int i40e_alloc_vsi_res(struct i40e_vf *vf, u8 idx)
0772 {
0773 struct i40e_mac_filter *f = NULL;
0774 struct i40e_pf *pf = vf->pf;
0775 struct i40e_vsi *vsi;
0776 u64 max_tx_rate = 0;
0777 int ret = 0;
0778
0779 vsi = i40e_vsi_setup(pf, I40E_VSI_SRIOV, pf->vsi[pf->lan_vsi]->seid,
0780 vf->vf_id);
0781
0782 if (!vsi) {
0783 dev_err(&pf->pdev->dev,
0784 "add vsi failed for VF %d, aq_err %d\n",
0785 vf->vf_id, pf->hw.aq.asq_last_status);
0786 ret = -ENOENT;
0787 goto error_alloc_vsi_res;
0788 }
0789
0790 if (!idx) {
0791 u64 hena = i40e_pf_get_default_rss_hena(pf);
0792 u8 broadcast[ETH_ALEN];
0793
0794 vf->lan_vsi_idx = vsi->idx;
0795 vf->lan_vsi_id = vsi->id;
0796
0797
0798
0799
0800
0801
0802 if (vf->port_vlan_id)
0803 i40e_vsi_add_pvid(vsi, vf->port_vlan_id);
0804
0805 spin_lock_bh(&vsi->mac_filter_hash_lock);
0806 if (is_valid_ether_addr(vf->default_lan_addr.addr)) {
0807 f = i40e_add_mac_filter(vsi,
0808 vf->default_lan_addr.addr);
0809 if (!f)
0810 dev_info(&pf->pdev->dev,
0811 "Could not add MAC filter %pM for VF %d\n",
0812 vf->default_lan_addr.addr, vf->vf_id);
0813 }
0814 eth_broadcast_addr(broadcast);
0815 f = i40e_add_mac_filter(vsi, broadcast);
0816 if (!f)
0817 dev_info(&pf->pdev->dev,
0818 "Could not allocate VF broadcast filter\n");
0819 spin_unlock_bh(&vsi->mac_filter_hash_lock);
0820 wr32(&pf->hw, I40E_VFQF_HENA1(0, vf->vf_id), (u32)hena);
0821 wr32(&pf->hw, I40E_VFQF_HENA1(1, vf->vf_id), (u32)(hena >> 32));
0822
0823 ret = i40e_sync_vsi_filters(vsi);
0824 if (ret)
0825 dev_err(&pf->pdev->dev, "Unable to program ucast filters\n");
0826 }
0827
0828
0829 if (vf->adq_enabled) {
0830 vf->ch[idx].vsi_idx = vsi->idx;
0831 vf->ch[idx].vsi_id = vsi->id;
0832 }
0833
0834
0835 if (vf->tx_rate) {
0836 max_tx_rate = vf->tx_rate;
0837 } else if (vf->ch[idx].max_tx_rate) {
0838 max_tx_rate = vf->ch[idx].max_tx_rate;
0839 }
0840
0841 if (max_tx_rate) {
0842 max_tx_rate = div_u64(max_tx_rate, I40E_BW_CREDIT_DIVISOR);
0843 ret = i40e_aq_config_vsi_bw_limit(&pf->hw, vsi->seid,
0844 max_tx_rate, 0, NULL);
0845 if (ret)
0846 dev_err(&pf->pdev->dev, "Unable to set tx rate, VF %d, error code %d.\n",
0847 vf->vf_id, ret);
0848 }
0849
0850 error_alloc_vsi_res:
0851 return ret;
0852 }
0853
0854
0855
0856
0857
0858
0859
0860
0861 static void i40e_map_pf_queues_to_vsi(struct i40e_vf *vf)
0862 {
0863 struct i40e_pf *pf = vf->pf;
0864 struct i40e_hw *hw = &pf->hw;
0865 u32 reg, num_tc = 1;
0866 u16 vsi_id, qps;
0867 int i, j;
0868
0869 if (vf->adq_enabled)
0870 num_tc = vf->num_tc;
0871
0872 for (i = 0; i < num_tc; i++) {
0873 if (vf->adq_enabled) {
0874 qps = vf->ch[i].num_qps;
0875 vsi_id = vf->ch[i].vsi_id;
0876 } else {
0877 qps = pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
0878 vsi_id = vf->lan_vsi_id;
0879 }
0880
0881 for (j = 0; j < 7; j++) {
0882 if (j * 2 >= qps) {
0883
0884 reg = 0x07FF07FF;
0885 } else {
0886 u16 qid = i40e_vc_get_pf_queue_id(vf,
0887 vsi_id,
0888 j * 2);
0889 reg = qid;
0890 qid = i40e_vc_get_pf_queue_id(vf, vsi_id,
0891 (j * 2) + 1);
0892 reg |= qid << 16;
0893 }
0894 i40e_write_rx_ctl(hw,
0895 I40E_VSILAN_QTABLE(j, vsi_id),
0896 reg);
0897 }
0898 }
0899 }
0900
0901
0902
0903
0904
0905
0906
0907
0908 static void i40e_map_pf_to_vf_queues(struct i40e_vf *vf)
0909 {
0910 struct i40e_pf *pf = vf->pf;
0911 struct i40e_hw *hw = &pf->hw;
0912 u32 reg, total_qps = 0;
0913 u32 qps, num_tc = 1;
0914 u16 vsi_id, qid;
0915 int i, j;
0916
0917 if (vf->adq_enabled)
0918 num_tc = vf->num_tc;
0919
0920 for (i = 0; i < num_tc; i++) {
0921 if (vf->adq_enabled) {
0922 qps = vf->ch[i].num_qps;
0923 vsi_id = vf->ch[i].vsi_id;
0924 } else {
0925 qps = pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
0926 vsi_id = vf->lan_vsi_id;
0927 }
0928
0929 for (j = 0; j < qps; j++) {
0930 qid = i40e_vc_get_pf_queue_id(vf, vsi_id, j);
0931
0932 reg = (qid & I40E_VPLAN_QTABLE_QINDEX_MASK);
0933 wr32(hw, I40E_VPLAN_QTABLE(total_qps, vf->vf_id),
0934 reg);
0935 total_qps++;
0936 }
0937 }
0938 }
0939
0940
0941
0942
0943
0944
0945
0946 static void i40e_enable_vf_mappings(struct i40e_vf *vf)
0947 {
0948 struct i40e_pf *pf = vf->pf;
0949 struct i40e_hw *hw = &pf->hw;
0950 u32 reg;
0951
0952
0953
0954
0955
0956 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
0957 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
0958
0959
0960 reg = I40E_VPLAN_MAPENA_TXRX_ENA_MASK;
0961 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg);
0962
0963 i40e_map_pf_to_vf_queues(vf);
0964 i40e_map_pf_queues_to_vsi(vf);
0965
0966 i40e_flush(hw);
0967 }
0968
0969
0970
0971
0972
0973
0974
0975 static void i40e_disable_vf_mappings(struct i40e_vf *vf)
0976 {
0977 struct i40e_pf *pf = vf->pf;
0978 struct i40e_hw *hw = &pf->hw;
0979 int i;
0980
0981
0982 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), 0);
0983 for (i = 0; i < I40E_MAX_VSI_QP; i++)
0984 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_id),
0985 I40E_QUEUE_END_OF_LIST);
0986 i40e_flush(hw);
0987 }
0988
0989
0990
0991
0992
0993
0994
0995 static void i40e_free_vf_res(struct i40e_vf *vf)
0996 {
0997 struct i40e_pf *pf = vf->pf;
0998 struct i40e_hw *hw = &pf->hw;
0999 u32 reg_idx, reg;
1000 int i, j, msix_vf;
1001
1002
1003
1004
1005 clear_bit(I40E_VF_STATE_INIT, &vf->vf_states);
1006
1007
1008
1009
1010 if (vf->num_queue_pairs > I40E_DEFAULT_QUEUES_PER_VF) {
1011 pf->queues_left += vf->num_queue_pairs -
1012 I40E_DEFAULT_QUEUES_PER_VF;
1013 }
1014
1015
1016 if (vf->lan_vsi_idx) {
1017 i40e_vsi_release(pf->vsi[vf->lan_vsi_idx]);
1018 vf->lan_vsi_idx = 0;
1019 vf->lan_vsi_id = 0;
1020 }
1021
1022
1023 if (vf->adq_enabled && vf->ch[0].vsi_idx) {
1024 for (j = 0; j < vf->num_tc; j++) {
1025
1026
1027
1028
1029 if (j)
1030 i40e_vsi_release(pf->vsi[vf->ch[j].vsi_idx]);
1031 vf->ch[j].vsi_idx = 0;
1032 vf->ch[j].vsi_id = 0;
1033 }
1034 }
1035 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
1036
1037
1038 for (i = 0; i < msix_vf; i++) {
1039
1040 if (0 == i)
1041 reg_idx = I40E_VFINT_DYN_CTL0(vf->vf_id);
1042 else
1043 reg_idx = I40E_VFINT_DYN_CTLN(((msix_vf - 1) *
1044 (vf->vf_id))
1045 + (i - 1));
1046 wr32(hw, reg_idx, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1047 i40e_flush(hw);
1048 }
1049
1050
1051 for (i = 0; i < msix_vf; i++) {
1052
1053 if (0 == i)
1054 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id);
1055 else
1056 reg_idx = I40E_VPINT_LNKLSTN(((msix_vf - 1) *
1057 (vf->vf_id))
1058 + (i - 1));
1059 reg = (I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK |
1060 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1061 wr32(hw, reg_idx, reg);
1062 i40e_flush(hw);
1063 }
1064
1065 vf->num_queue_pairs = 0;
1066 clear_bit(I40E_VF_STATE_MC_PROMISC, &vf->vf_states);
1067 clear_bit(I40E_VF_STATE_UC_PROMISC, &vf->vf_states);
1068 }
1069
1070
1071
1072
1073
1074
1075
1076 static int i40e_alloc_vf_res(struct i40e_vf *vf)
1077 {
1078 struct i40e_pf *pf = vf->pf;
1079 int total_queue_pairs = 0;
1080 int ret, idx;
1081
1082 if (vf->num_req_queues &&
1083 vf->num_req_queues <= pf->queues_left + I40E_DEFAULT_QUEUES_PER_VF)
1084 pf->num_vf_qps = vf->num_req_queues;
1085 else
1086 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
1087
1088
1089 ret = i40e_alloc_vsi_res(vf, 0);
1090 if (ret)
1091 goto error_alloc;
1092 total_queue_pairs += pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
1093
1094
1095 if (vf->adq_enabled) {
1096 if (pf->queues_left >=
1097 (I40E_MAX_VF_QUEUES - I40E_DEFAULT_QUEUES_PER_VF)) {
1098
1099 for (idx = 1; idx < vf->num_tc; idx++) {
1100 ret = i40e_alloc_vsi_res(vf, idx);
1101 if (ret)
1102 goto error_alloc;
1103 }
1104
1105 total_queue_pairs = I40E_MAX_VF_QUEUES;
1106 } else {
1107 dev_info(&pf->pdev->dev, "VF %d: Not enough queues to allocate, disabling ADq\n",
1108 vf->vf_id);
1109 vf->adq_enabled = false;
1110 }
1111 }
1112
1113
1114
1115
1116
1117
1118 if (total_queue_pairs > I40E_DEFAULT_QUEUES_PER_VF)
1119 pf->queues_left -=
1120 total_queue_pairs - I40E_DEFAULT_QUEUES_PER_VF;
1121
1122 if (vf->trusted)
1123 set_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
1124 else
1125 clear_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
1126
1127
1128
1129
1130 vf->num_queue_pairs = total_queue_pairs;
1131
1132
1133 set_bit(I40E_VF_STATE_INIT, &vf->vf_states);
1134
1135 error_alloc:
1136 if (ret)
1137 i40e_free_vf_res(vf);
1138
1139 return ret;
1140 }
1141
1142 #define VF_DEVICE_STATUS 0xAA
1143 #define VF_TRANS_PENDING_MASK 0x20
1144
1145
1146
1147
1148
1149
1150
1151 static int i40e_quiesce_vf_pci(struct i40e_vf *vf)
1152 {
1153 struct i40e_pf *pf = vf->pf;
1154 struct i40e_hw *hw = &pf->hw;
1155 int vf_abs_id, i;
1156 u32 reg;
1157
1158 vf_abs_id = vf->vf_id + hw->func_caps.vf_base_id;
1159
1160 wr32(hw, I40E_PF_PCI_CIAA,
1161 VF_DEVICE_STATUS | (vf_abs_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
1162 for (i = 0; i < 100; i++) {
1163 reg = rd32(hw, I40E_PF_PCI_CIAD);
1164 if ((reg & VF_TRANS_PENDING_MASK) == 0)
1165 return 0;
1166 udelay(1);
1167 }
1168 return -EIO;
1169 }
1170
1171
1172
1173
1174
1175
1176
1177 static int __i40e_getnum_vf_vsi_vlan_filters(struct i40e_vsi *vsi)
1178 {
1179 struct i40e_mac_filter *f;
1180 u16 num_vlans = 0, bkt;
1181
1182 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
1183 if (f->vlan >= 0 && f->vlan <= I40E_MAX_VLANID)
1184 num_vlans++;
1185 }
1186
1187 return num_vlans;
1188 }
1189
1190
1191
1192
1193
1194
1195
1196 static int i40e_getnum_vf_vsi_vlan_filters(struct i40e_vsi *vsi)
1197 {
1198 int num_vlans;
1199
1200 spin_lock_bh(&vsi->mac_filter_hash_lock);
1201 num_vlans = __i40e_getnum_vf_vsi_vlan_filters(vsi);
1202 spin_unlock_bh(&vsi->mac_filter_hash_lock);
1203
1204 return num_vlans;
1205 }
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216 static void i40e_get_vlan_list_sync(struct i40e_vsi *vsi, u16 *num_vlans,
1217 s16 **vlan_list)
1218 {
1219 struct i40e_mac_filter *f;
1220 int i = 0;
1221 int bkt;
1222
1223 spin_lock_bh(&vsi->mac_filter_hash_lock);
1224 *num_vlans = __i40e_getnum_vf_vsi_vlan_filters(vsi);
1225 *vlan_list = kcalloc(*num_vlans, sizeof(**vlan_list), GFP_ATOMIC);
1226 if (!(*vlan_list))
1227 goto err;
1228
1229 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
1230 if (f->vlan < 0 || f->vlan > I40E_MAX_VLANID)
1231 continue;
1232 (*vlan_list)[i++] = f->vlan;
1233 }
1234 err:
1235 spin_unlock_bh(&vsi->mac_filter_hash_lock);
1236 }
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249 static i40e_status
1250 i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable,
1251 bool unicast_enable, s16 *vl, u16 num_vlans)
1252 {
1253 i40e_status aq_ret, aq_tmp = 0;
1254 struct i40e_pf *pf = vf->pf;
1255 struct i40e_hw *hw = &pf->hw;
1256 int i;
1257
1258
1259 if (!num_vlans || !vl) {
1260 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(hw, seid,
1261 multi_enable,
1262 NULL);
1263 if (aq_ret) {
1264 int aq_err = pf->hw.aq.asq_last_status;
1265
1266 dev_err(&pf->pdev->dev,
1267 "VF %d failed to set multicast promiscuous mode err %s aq_err %s\n",
1268 vf->vf_id,
1269 i40e_stat_str(&pf->hw, aq_ret),
1270 i40e_aq_str(&pf->hw, aq_err));
1271
1272 return aq_ret;
1273 }
1274
1275 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(hw, seid,
1276 unicast_enable,
1277 NULL, true);
1278
1279 if (aq_ret) {
1280 int aq_err = pf->hw.aq.asq_last_status;
1281
1282 dev_err(&pf->pdev->dev,
1283 "VF %d failed to set unicast promiscuous mode err %s aq_err %s\n",
1284 vf->vf_id,
1285 i40e_stat_str(&pf->hw, aq_ret),
1286 i40e_aq_str(&pf->hw, aq_err));
1287 }
1288
1289 return aq_ret;
1290 }
1291
1292 for (i = 0; i < num_vlans; i++) {
1293 aq_ret = i40e_aq_set_vsi_mc_promisc_on_vlan(hw, seid,
1294 multi_enable,
1295 vl[i], NULL);
1296 if (aq_ret) {
1297 int aq_err = pf->hw.aq.asq_last_status;
1298
1299 dev_err(&pf->pdev->dev,
1300 "VF %d failed to set multicast promiscuous mode err %s aq_err %s\n",
1301 vf->vf_id,
1302 i40e_stat_str(&pf->hw, aq_ret),
1303 i40e_aq_str(&pf->hw, aq_err));
1304
1305 if (!aq_tmp)
1306 aq_tmp = aq_ret;
1307 }
1308
1309 aq_ret = i40e_aq_set_vsi_uc_promisc_on_vlan(hw, seid,
1310 unicast_enable,
1311 vl[i], NULL);
1312 if (aq_ret) {
1313 int aq_err = pf->hw.aq.asq_last_status;
1314
1315 dev_err(&pf->pdev->dev,
1316 "VF %d failed to set unicast promiscuous mode err %s aq_err %s\n",
1317 vf->vf_id,
1318 i40e_stat_str(&pf->hw, aq_ret),
1319 i40e_aq_str(&pf->hw, aq_err));
1320
1321 if (!aq_tmp)
1322 aq_tmp = aq_ret;
1323 }
1324 }
1325
1326 if (aq_tmp)
1327 aq_ret = aq_tmp;
1328
1329 return aq_ret;
1330 }
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342 static i40e_status i40e_config_vf_promiscuous_mode(struct i40e_vf *vf,
1343 u16 vsi_id,
1344 bool allmulti,
1345 bool alluni)
1346 {
1347 i40e_status aq_ret = I40E_SUCCESS;
1348 struct i40e_pf *pf = vf->pf;
1349 struct i40e_vsi *vsi;
1350 u16 num_vlans;
1351 s16 *vl;
1352
1353 vsi = i40e_find_vsi_from_id(pf, vsi_id);
1354 if (!i40e_vc_isvalid_vsi_id(vf, vsi_id) || !vsi)
1355 return I40E_ERR_PARAM;
1356
1357 if (vf->port_vlan_id) {
1358 aq_ret = i40e_set_vsi_promisc(vf, vsi->seid, allmulti,
1359 alluni, &vf->port_vlan_id, 1);
1360 return aq_ret;
1361 } else if (i40e_getnum_vf_vsi_vlan_filters(vsi)) {
1362 i40e_get_vlan_list_sync(vsi, &num_vlans, &vl);
1363
1364 if (!vl)
1365 return I40E_ERR_NO_MEMORY;
1366
1367 aq_ret = i40e_set_vsi_promisc(vf, vsi->seid, allmulti, alluni,
1368 vl, num_vlans);
1369 kfree(vl);
1370 return aq_ret;
1371 }
1372
1373
1374 aq_ret = i40e_set_vsi_promisc(vf, vsi->seid, allmulti, alluni,
1375 NULL, 0);
1376 return aq_ret;
1377 }
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388 static int i40e_sync_vfr_reset(struct i40e_hw *hw, int vf_id)
1389 {
1390 u32 reg;
1391 int i;
1392
1393 for (i = 0; i < I40E_VFR_WAIT_COUNT; i++) {
1394 reg = rd32(hw, I40E_VFINT_ICR0_ENA(vf_id)) &
1395 I40E_VFINT_ICR0_ADMINQ_MASK;
1396 if (reg)
1397 return 0;
1398
1399 usleep_range(100, 200);
1400 }
1401
1402 return -EAGAIN;
1403 }
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414 static void i40e_trigger_vf_reset(struct i40e_vf *vf, bool flr)
1415 {
1416 struct i40e_pf *pf = vf->pf;
1417 struct i40e_hw *hw = &pf->hw;
1418 u32 reg, reg_idx, bit_idx;
1419 bool vf_active;
1420 u32 radq;
1421
1422
1423 vf_active = test_and_clear_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states);
1424
1425
1426
1427
1428
1429
1430
1431 clear_bit(I40E_VF_STATE_INIT, &vf->vf_states);
1432
1433
1434
1435
1436 if (!flr) {
1437
1438 radq = rd32(hw, I40E_VFINT_ICR0_ENA(vf->vf_id)) &
1439 I40E_VFINT_ICR0_ADMINQ_MASK;
1440 if (vf_active && !radq)
1441
1442 if (i40e_sync_vfr_reset(hw, vf->vf_id))
1443 dev_info(&pf->pdev->dev,
1444 "Reset VF %d never finished\n",
1445 vf->vf_id);
1446
1447
1448
1449
1450 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id));
1451 reg |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
1452 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
1453 i40e_flush(hw);
1454 }
1455
1456 reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32;
1457 bit_idx = (hw->func_caps.vf_base_id + vf->vf_id) % 32;
1458 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
1459 i40e_flush(hw);
1460
1461 if (i40e_quiesce_vf_pci(vf))
1462 dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
1463 vf->vf_id);
1464 }
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474 static void i40e_cleanup_reset_vf(struct i40e_vf *vf)
1475 {
1476 struct i40e_pf *pf = vf->pf;
1477 struct i40e_hw *hw = &pf->hw;
1478 u32 reg;
1479
1480
1481 i40e_config_vf_promiscuous_mode(vf, vf->lan_vsi_id, false, false);
1482
1483
1484 i40e_free_vf_res(vf);
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id));
1497 reg &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
1498 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
1499
1500
1501 if (!i40e_alloc_vf_res(vf)) {
1502 int abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
1503 i40e_enable_vf_mappings(vf);
1504 set_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states);
1505 clear_bit(I40E_VF_STATE_DISABLED, &vf->vf_states);
1506
1507 if (!test_and_clear_bit(I40E_VF_STATE_PRE_ENABLE,
1508 &vf->vf_states))
1509 i40e_notify_client_of_vf_reset(pf, abs_vf_id);
1510 vf->num_vlan = 0;
1511 }
1512
1513
1514
1515
1516
1517 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), VIRTCHNL_VFR_VFACTIVE);
1518 }
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528 bool i40e_reset_vf(struct i40e_vf *vf, bool flr)
1529 {
1530 struct i40e_pf *pf = vf->pf;
1531 struct i40e_hw *hw = &pf->hw;
1532 bool rsd = false;
1533 u32 reg;
1534 int i;
1535
1536 if (test_bit(__I40E_VF_RESETS_DISABLED, pf->state))
1537 return true;
1538
1539
1540
1541
1542 if (test_and_set_bit(__I40E_VF_DISABLE, pf->state))
1543 return true;
1544
1545 i40e_trigger_vf_reset(vf, flr);
1546
1547
1548
1549
1550 for (i = 0; i < 10; i++) {
1551
1552
1553
1554
1555
1556 usleep_range(10000, 20000);
1557 reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id));
1558 if (reg & I40E_VPGEN_VFRSTAT_VFRD_MASK) {
1559 rsd = true;
1560 break;
1561 }
1562 }
1563
1564 if (flr)
1565 usleep_range(10000, 20000);
1566
1567 if (!rsd)
1568 dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
1569 vf->vf_id);
1570 usleep_range(10000, 20000);
1571
1572
1573 if (vf->lan_vsi_idx != 0)
1574 i40e_vsi_stop_rings(pf->vsi[vf->lan_vsi_idx]);
1575
1576 i40e_cleanup_reset_vf(vf);
1577
1578 i40e_flush(hw);
1579 clear_bit(__I40E_VF_DISABLE, pf->state);
1580
1581 return true;
1582 }
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596 bool i40e_reset_all_vfs(struct i40e_pf *pf, bool flr)
1597 {
1598 struct i40e_hw *hw = &pf->hw;
1599 struct i40e_vf *vf;
1600 int i, v;
1601 u32 reg;
1602
1603
1604 if (!pf->num_alloc_vfs)
1605 return false;
1606
1607
1608 if (test_and_set_bit(__I40E_VF_DISABLE, pf->state))
1609 return false;
1610
1611
1612 for (v = 0; v < pf->num_alloc_vfs; v++)
1613 i40e_trigger_vf_reset(&pf->vf[v], flr);
1614
1615
1616
1617
1618
1619
1620
1621 for (i = 0, v = 0; i < 10 && v < pf->num_alloc_vfs; i++) {
1622 usleep_range(10000, 20000);
1623
1624
1625
1626
1627 while (v < pf->num_alloc_vfs) {
1628 vf = &pf->vf[v];
1629 reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id));
1630 if (!(reg & I40E_VPGEN_VFRSTAT_VFRD_MASK))
1631 break;
1632
1633
1634
1635
1636 v++;
1637 }
1638 }
1639
1640 if (flr)
1641 usleep_range(10000, 20000);
1642
1643
1644
1645
1646 if (v < pf->num_alloc_vfs)
1647 dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
1648 pf->vf[v].vf_id);
1649 usleep_range(10000, 20000);
1650
1651
1652
1653
1654 for (v = 0; v < pf->num_alloc_vfs; v++) {
1655
1656 if (pf->vf[v].lan_vsi_idx == 0)
1657 continue;
1658
1659 i40e_vsi_stop_rings_no_wait(pf->vsi[pf->vf[v].lan_vsi_idx]);
1660 }
1661
1662
1663
1664
1665 for (v = 0; v < pf->num_alloc_vfs; v++) {
1666
1667 if (pf->vf[v].lan_vsi_idx == 0)
1668 continue;
1669
1670 i40e_vsi_wait_queues_disabled(pf->vsi[pf->vf[v].lan_vsi_idx]);
1671 }
1672
1673
1674
1675
1676 mdelay(50);
1677
1678
1679 for (v = 0; v < pf->num_alloc_vfs; v++)
1680 i40e_cleanup_reset_vf(&pf->vf[v]);
1681
1682 i40e_flush(hw);
1683 clear_bit(__I40E_VF_DISABLE, pf->state);
1684
1685 return true;
1686 }
1687
1688
1689
1690
1691
1692
1693
1694 void i40e_free_vfs(struct i40e_pf *pf)
1695 {
1696 struct i40e_hw *hw = &pf->hw;
1697 u32 reg_idx, bit_idx;
1698 int i, tmp, vf_id;
1699
1700 if (!pf->vf)
1701 return;
1702
1703 set_bit(__I40E_VFS_RELEASING, pf->state);
1704 while (test_and_set_bit(__I40E_VF_DISABLE, pf->state))
1705 usleep_range(1000, 2000);
1706
1707 i40e_notify_client_of_vf_enable(pf, 0);
1708
1709
1710
1711
1712
1713 if (!pci_vfs_assigned(pf->pdev))
1714 pci_disable_sriov(pf->pdev);
1715 else
1716 dev_warn(&pf->pdev->dev, "VFs are assigned - not disabling SR-IOV\n");
1717
1718
1719 for (i = 0; i < pf->num_alloc_vfs; i++) {
1720 if (test_bit(I40E_VF_STATE_INIT, &pf->vf[i].vf_states))
1721 continue;
1722
1723 i40e_vsi_stop_rings_no_wait(pf->vsi[pf->vf[i].lan_vsi_idx]);
1724 }
1725
1726 for (i = 0; i < pf->num_alloc_vfs; i++) {
1727 if (test_bit(I40E_VF_STATE_INIT, &pf->vf[i].vf_states))
1728 continue;
1729
1730 i40e_vsi_wait_queues_disabled(pf->vsi[pf->vf[i].lan_vsi_idx]);
1731 }
1732
1733
1734 tmp = pf->num_alloc_vfs;
1735 pf->num_alloc_vfs = 0;
1736 for (i = 0; i < tmp; i++) {
1737 if (test_bit(I40E_VF_STATE_INIT, &pf->vf[i].vf_states))
1738 i40e_free_vf_res(&pf->vf[i]);
1739
1740 i40e_disable_vf_mappings(&pf->vf[i]);
1741 }
1742
1743 kfree(pf->vf);
1744 pf->vf = NULL;
1745
1746
1747
1748
1749
1750 if (!pci_vfs_assigned(pf->pdev)) {
1751
1752
1753
1754 for (vf_id = 0; vf_id < tmp; vf_id++) {
1755 reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
1756 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
1757 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
1758 }
1759 }
1760 clear_bit(__I40E_VF_DISABLE, pf->state);
1761 clear_bit(__I40E_VFS_RELEASING, pf->state);
1762 }
1763
1764 #ifdef CONFIG_PCI_IOV
1765
1766
1767
1768
1769
1770
1771
1772 int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs)
1773 {
1774 struct i40e_vf *vfs;
1775 int i, ret = 0;
1776
1777
1778 i40e_irq_dynamic_disable_icr0(pf);
1779
1780
1781 if (pci_num_vf(pf->pdev) != num_alloc_vfs) {
1782 ret = pci_enable_sriov(pf->pdev, num_alloc_vfs);
1783 if (ret) {
1784 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
1785 pf->num_alloc_vfs = 0;
1786 goto err_iov;
1787 }
1788 }
1789
1790 vfs = kcalloc(num_alloc_vfs, sizeof(struct i40e_vf), GFP_KERNEL);
1791 if (!vfs) {
1792 ret = -ENOMEM;
1793 goto err_alloc;
1794 }
1795 pf->vf = vfs;
1796
1797
1798 for (i = 0; i < num_alloc_vfs; i++) {
1799 vfs[i].pf = pf;
1800 vfs[i].parent_type = I40E_SWITCH_ELEMENT_TYPE_VEB;
1801 vfs[i].vf_id = i;
1802
1803
1804 set_bit(I40E_VIRTCHNL_VF_CAP_L2, &vfs[i].vf_caps);
1805 vfs[i].spoofchk = true;
1806
1807 set_bit(I40E_VF_STATE_PRE_ENABLE, &vfs[i].vf_states);
1808
1809 }
1810 pf->num_alloc_vfs = num_alloc_vfs;
1811
1812
1813 i40e_reset_all_vfs(pf, false);
1814
1815 i40e_notify_client_of_vf_enable(pf, num_alloc_vfs);
1816
1817 err_alloc:
1818 if (ret)
1819 i40e_free_vfs(pf);
1820 err_iov:
1821
1822 i40e_irq_dynamic_enable_icr0(pf);
1823 return ret;
1824 }
1825
1826 #endif
1827
1828
1829
1830
1831
1832
1833
1834 static int i40e_pci_sriov_enable(struct pci_dev *pdev, int num_vfs)
1835 {
1836 #ifdef CONFIG_PCI_IOV
1837 struct i40e_pf *pf = pci_get_drvdata(pdev);
1838 int pre_existing_vfs = pci_num_vf(pdev);
1839 int err = 0;
1840
1841 if (test_bit(__I40E_TESTING, pf->state)) {
1842 dev_warn(&pdev->dev,
1843 "Cannot enable SR-IOV virtual functions while the device is undergoing diagnostic testing\n");
1844 err = -EPERM;
1845 goto err_out;
1846 }
1847
1848 if (pre_existing_vfs && pre_existing_vfs != num_vfs)
1849 i40e_free_vfs(pf);
1850 else if (pre_existing_vfs && pre_existing_vfs == num_vfs)
1851 goto out;
1852
1853 if (num_vfs > pf->num_req_vfs) {
1854 dev_warn(&pdev->dev, "Unable to enable %d VFs. Limited to %d VFs due to device resource constraints.\n",
1855 num_vfs, pf->num_req_vfs);
1856 err = -EPERM;
1857 goto err_out;
1858 }
1859
1860 dev_info(&pdev->dev, "Allocating %d VFs.\n", num_vfs);
1861 err = i40e_alloc_vfs(pf, num_vfs);
1862 if (err) {
1863 dev_warn(&pdev->dev, "Failed to enable SR-IOV: %d\n", err);
1864 goto err_out;
1865 }
1866
1867 out:
1868 return num_vfs;
1869
1870 err_out:
1871 return err;
1872 #endif
1873 return 0;
1874 }
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884 int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1885 {
1886 struct i40e_pf *pf = pci_get_drvdata(pdev);
1887 int ret = 0;
1888
1889 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
1890 dev_warn(&pdev->dev, "Unable to configure VFs, other operation is pending.\n");
1891 return -EAGAIN;
1892 }
1893
1894 if (num_vfs) {
1895 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
1896 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
1897 i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);
1898 }
1899 ret = i40e_pci_sriov_enable(pdev, num_vfs);
1900 goto sriov_configure_out;
1901 }
1902
1903 if (!pci_vfs_assigned(pf->pdev)) {
1904 i40e_free_vfs(pf);
1905 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
1906 i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);
1907 } else {
1908 dev_warn(&pdev->dev, "Unable to free VFs because some are assigned to VMs.\n");
1909 ret = -EINVAL;
1910 goto sriov_configure_out;
1911 }
1912 sriov_configure_out:
1913 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
1914 return ret;
1915 }
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929 static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode,
1930 u32 v_retval, u8 *msg, u16 msglen)
1931 {
1932 struct i40e_pf *pf;
1933 struct i40e_hw *hw;
1934 int abs_vf_id;
1935 i40e_status aq_ret;
1936
1937
1938 if (!vf || vf->vf_id >= vf->pf->num_alloc_vfs)
1939 return -EINVAL;
1940
1941 pf = vf->pf;
1942 hw = &pf->hw;
1943 abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
1944
1945 aq_ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
1946 msg, msglen, NULL);
1947 if (aq_ret) {
1948 dev_info(&pf->pdev->dev,
1949 "Unable to send the message to VF %d aq_err %d\n",
1950 vf->vf_id, pf->hw.aq.asq_last_status);
1951 return -EIO;
1952 }
1953
1954 return 0;
1955 }
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965 static int i40e_vc_send_resp_to_vf(struct i40e_vf *vf,
1966 enum virtchnl_ops opcode,
1967 i40e_status retval)
1968 {
1969 return i40e_vc_send_msg_to_vf(vf, opcode, retval, NULL, 0);
1970 }
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980 static bool i40e_sync_vf_state(struct i40e_vf *vf, enum i40e_vf_states state)
1981 {
1982 int i;
1983
1984
1985
1986
1987
1988
1989 for (i = 0; i < I40E_VF_STATE_WAIT_COUNT; i++) {
1990 if (test_bit(state, &vf->vf_states))
1991 return true;
1992 usleep_range(10000, 20000);
1993 }
1994
1995 return test_bit(state, &vf->vf_states);
1996 }
1997
1998
1999
2000
2001
2002
2003
2004
2005 static int i40e_vc_get_version_msg(struct i40e_vf *vf, u8 *msg)
2006 {
2007 struct virtchnl_version_info info = {
2008 VIRTCHNL_VERSION_MAJOR, VIRTCHNL_VERSION_MINOR
2009 };
2010
2011 vf->vf_ver = *(struct virtchnl_version_info *)msg;
2012
2013 if (VF_IS_V10(&vf->vf_ver))
2014 info.minor = VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
2015 return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
2016 I40E_SUCCESS, (u8 *)&info,
2017 sizeof(struct virtchnl_version_info));
2018 }
2019
2020
2021
2022
2023
2024 static void i40e_del_qch(struct i40e_vf *vf)
2025 {
2026 struct i40e_pf *pf = vf->pf;
2027 int i;
2028
2029
2030
2031
2032 for (i = 1; i < vf->num_tc; i++) {
2033 if (vf->ch[i].vsi_idx) {
2034 i40e_vsi_release(pf->vsi[vf->ch[i].vsi_idx]);
2035 vf->ch[i].vsi_idx = 0;
2036 vf->ch[i].vsi_id = 0;
2037 }
2038 }
2039 }
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050 static u16 i40e_vc_get_max_frame_size(struct i40e_vf *vf)
2051 {
2052 u16 max_frame_size = vf->pf->hw.phy.link_info.max_frame_size;
2053
2054 if (vf->port_vlan_id)
2055 max_frame_size -= VLAN_HLEN;
2056
2057 return max_frame_size;
2058 }
2059
2060
2061
2062
2063
2064
2065
2066
2067 static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
2068 {
2069 struct virtchnl_vf_resource *vfres = NULL;
2070 struct i40e_pf *pf = vf->pf;
2071 i40e_status aq_ret = 0;
2072 struct i40e_vsi *vsi;
2073 int num_vsis = 1;
2074 size_t len = 0;
2075 int ret;
2076
2077 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_INIT)) {
2078 aq_ret = I40E_ERR_PARAM;
2079 goto err;
2080 }
2081
2082 len = struct_size(vfres, vsi_res, num_vsis);
2083 vfres = kzalloc(len, GFP_KERNEL);
2084 if (!vfres) {
2085 aq_ret = I40E_ERR_NO_MEMORY;
2086 len = 0;
2087 goto err;
2088 }
2089 if (VF_IS_V11(&vf->vf_ver))
2090 vf->driver_caps = *(u32 *)msg;
2091 else
2092 vf->driver_caps = VIRTCHNL_VF_OFFLOAD_L2 |
2093 VIRTCHNL_VF_OFFLOAD_RSS_REG |
2094 VIRTCHNL_VF_OFFLOAD_VLAN;
2095
2096 vfres->vf_cap_flags = VIRTCHNL_VF_OFFLOAD_L2;
2097 vfres->vf_cap_flags |= VIRTCHNL_VF_CAP_ADV_LINK_SPEED;
2098 vsi = pf->vsi[vf->lan_vsi_idx];
2099 if (!vsi->info.pvid)
2100 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_VLAN;
2101
2102 if (i40e_vf_client_capable(pf, vf->vf_id) &&
2103 (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_IWARP)) {
2104 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_IWARP;
2105 set_bit(I40E_VF_STATE_IWARPENA, &vf->vf_states);
2106 } else {
2107 clear_bit(I40E_VF_STATE_IWARPENA, &vf->vf_states);
2108 }
2109
2110 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
2111 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RSS_PF;
2112 } else {
2113 if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) &&
2114 (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_AQ))
2115 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RSS_AQ;
2116 else
2117 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RSS_REG;
2118 }
2119
2120 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) {
2121 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2)
2122 vfres->vf_cap_flags |=
2123 VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2;
2124 }
2125
2126 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ENCAP)
2127 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP;
2128
2129 if ((pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE) &&
2130 (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM))
2131 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM;
2132
2133 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RX_POLLING) {
2134 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
2135 dev_err(&pf->pdev->dev,
2136 "VF %d requested polling mode: this feature is supported only when the device is running in single function per port (SFP) mode\n",
2137 vf->vf_id);
2138 aq_ret = I40E_ERR_PARAM;
2139 goto err;
2140 }
2141 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RX_POLLING;
2142 }
2143
2144 if (pf->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) {
2145 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_WB_ON_ITR)
2146 vfres->vf_cap_flags |=
2147 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;
2148 }
2149
2150 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_REQ_QUEUES)
2151 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_REQ_QUEUES;
2152
2153 if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ADQ)
2154 vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ADQ;
2155
2156 vfres->num_vsis = num_vsis;
2157 vfres->num_queue_pairs = vf->num_queue_pairs;
2158 vfres->max_vectors = pf->hw.func_caps.num_msix_vectors_vf;
2159 vfres->rss_key_size = I40E_HKEY_ARRAY_SIZE;
2160 vfres->rss_lut_size = I40E_VF_HLUT_ARRAY_SIZE;
2161 vfres->max_mtu = i40e_vc_get_max_frame_size(vf);
2162
2163 if (vf->lan_vsi_idx) {
2164 vfres->vsi_res[0].vsi_id = vf->lan_vsi_id;
2165 vfres->vsi_res[0].vsi_type = VIRTCHNL_VSI_SRIOV;
2166 vfres->vsi_res[0].num_queue_pairs = vsi->alloc_queue_pairs;
2167
2168 vfres->vsi_res[0].qset_handle
2169 = le16_to_cpu(vsi->info.qs_handle[0]);
2170 if (!(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_USO) && !vf->pf_set_mac) {
2171 i40e_del_mac_filter(vsi, vf->default_lan_addr.addr);
2172 eth_zero_addr(vf->default_lan_addr.addr);
2173 }
2174 ether_addr_copy(vfres->vsi_res[0].default_mac_addr,
2175 vf->default_lan_addr.addr);
2176 }
2177 set_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states);
2178
2179 err:
2180
2181 ret = i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_GET_VF_RESOURCES,
2182 aq_ret, (u8 *)vfres, len);
2183
2184 kfree(vfres);
2185 return ret;
2186 }
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196 static int i40e_vc_config_promiscuous_mode_msg(struct i40e_vf *vf, u8 *msg)
2197 {
2198 struct virtchnl_promisc_info *info =
2199 (struct virtchnl_promisc_info *)msg;
2200 struct i40e_pf *pf = vf->pf;
2201 i40e_status aq_ret = 0;
2202 bool allmulti = false;
2203 bool alluni = false;
2204
2205 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
2206 aq_ret = I40E_ERR_PARAM;
2207 goto err_out;
2208 }
2209 if (!test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
2210 dev_err(&pf->pdev->dev,
2211 "Unprivileged VF %d is attempting to configure promiscuous mode\n",
2212 vf->vf_id);
2213
2214
2215
2216
2217 aq_ret = 0;
2218 goto err_out;
2219 }
2220
2221 if (info->flags > I40E_MAX_VF_PROMISC_FLAGS) {
2222 aq_ret = I40E_ERR_PARAM;
2223 goto err_out;
2224 }
2225
2226 if (!i40e_vc_isvalid_vsi_id(vf, info->vsi_id)) {
2227 aq_ret = I40E_ERR_PARAM;
2228 goto err_out;
2229 }
2230
2231
2232 if (info->flags & FLAG_VF_MULTICAST_PROMISC)
2233 allmulti = true;
2234
2235 if (info->flags & FLAG_VF_UNICAST_PROMISC)
2236 alluni = true;
2237 aq_ret = i40e_config_vf_promiscuous_mode(vf, info->vsi_id, allmulti,
2238 alluni);
2239 if (aq_ret)
2240 goto err_out;
2241
2242 if (allmulti) {
2243 if (!test_and_set_bit(I40E_VF_STATE_MC_PROMISC,
2244 &vf->vf_states))
2245 dev_info(&pf->pdev->dev,
2246 "VF %d successfully set multicast promiscuous mode\n",
2247 vf->vf_id);
2248 } else if (test_and_clear_bit(I40E_VF_STATE_MC_PROMISC,
2249 &vf->vf_states))
2250 dev_info(&pf->pdev->dev,
2251 "VF %d successfully unset multicast promiscuous mode\n",
2252 vf->vf_id);
2253
2254 if (alluni) {
2255 if (!test_and_set_bit(I40E_VF_STATE_UC_PROMISC,
2256 &vf->vf_states))
2257 dev_info(&pf->pdev->dev,
2258 "VF %d successfully set unicast promiscuous mode\n",
2259 vf->vf_id);
2260 } else if (test_and_clear_bit(I40E_VF_STATE_UC_PROMISC,
2261 &vf->vf_states))
2262 dev_info(&pf->pdev->dev,
2263 "VF %d successfully unset unicast promiscuous mode\n",
2264 vf->vf_id);
2265
2266 err_out:
2267
2268 return i40e_vc_send_resp_to_vf(vf,
2269 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
2270 aq_ret);
2271 }
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281 static int i40e_vc_config_queues_msg(struct i40e_vf *vf, u8 *msg)
2282 {
2283 struct virtchnl_vsi_queue_config_info *qci =
2284 (struct virtchnl_vsi_queue_config_info *)msg;
2285 struct virtchnl_queue_pair_info *qpi;
2286 u16 vsi_id, vsi_queue_id = 0;
2287 struct i40e_pf *pf = vf->pf;
2288 i40e_status aq_ret = 0;
2289 int i, j = 0, idx = 0;
2290 struct i40e_vsi *vsi;
2291 u16 num_qps_all = 0;
2292
2293 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
2294 aq_ret = I40E_ERR_PARAM;
2295 goto error_param;
2296 }
2297
2298 if (!i40e_vc_isvalid_vsi_id(vf, qci->vsi_id)) {
2299 aq_ret = I40E_ERR_PARAM;
2300 goto error_param;
2301 }
2302
2303 if (qci->num_queue_pairs > I40E_MAX_VF_QUEUES) {
2304 aq_ret = I40E_ERR_PARAM;
2305 goto error_param;
2306 }
2307
2308 if (vf->adq_enabled) {
2309 for (i = 0; i < vf->num_tc; i++)
2310 num_qps_all += vf->ch[i].num_qps;
2311 if (num_qps_all != qci->num_queue_pairs) {
2312 aq_ret = I40E_ERR_PARAM;
2313 goto error_param;
2314 }
2315 }
2316
2317 vsi_id = qci->vsi_id;
2318
2319 for (i = 0; i < qci->num_queue_pairs; i++) {
2320 qpi = &qci->qpair[i];
2321
2322 if (!vf->adq_enabled) {
2323 if (!i40e_vc_isvalid_queue_id(vf, vsi_id,
2324 qpi->txq.queue_id)) {
2325 aq_ret = I40E_ERR_PARAM;
2326 goto error_param;
2327 }
2328
2329 vsi_queue_id = qpi->txq.queue_id;
2330
2331 if (qpi->txq.vsi_id != qci->vsi_id ||
2332 qpi->rxq.vsi_id != qci->vsi_id ||
2333 qpi->rxq.queue_id != vsi_queue_id) {
2334 aq_ret = I40E_ERR_PARAM;
2335 goto error_param;
2336 }
2337 }
2338
2339 if (vf->adq_enabled) {
2340 if (idx >= ARRAY_SIZE(vf->ch)) {
2341 aq_ret = I40E_ERR_NO_AVAILABLE_VSI;
2342 goto error_param;
2343 }
2344 vsi_id = vf->ch[idx].vsi_id;
2345 }
2346
2347 if (i40e_config_vsi_rx_queue(vf, vsi_id, vsi_queue_id,
2348 &qpi->rxq) ||
2349 i40e_config_vsi_tx_queue(vf, vsi_id, vsi_queue_id,
2350 &qpi->txq)) {
2351 aq_ret = I40E_ERR_PARAM;
2352 goto error_param;
2353 }
2354
2355
2356
2357
2358
2359
2360 if (vf->adq_enabled) {
2361 if (idx >= ARRAY_SIZE(vf->ch)) {
2362 aq_ret = I40E_ERR_NO_AVAILABLE_VSI;
2363 goto error_param;
2364 }
2365 if (j == (vf->ch[idx].num_qps - 1)) {
2366 idx++;
2367 j = 0;
2368 vsi_queue_id = 0;
2369 } else {
2370 j++;
2371 vsi_queue_id++;
2372 }
2373 }
2374 }
2375
2376 if (!vf->adq_enabled) {
2377 pf->vsi[vf->lan_vsi_idx]->num_queue_pairs =
2378 qci->num_queue_pairs;
2379 } else {
2380 for (i = 0; i < vf->num_tc; i++) {
2381 vsi = pf->vsi[vf->ch[i].vsi_idx];
2382 vsi->num_queue_pairs = vf->ch[i].num_qps;
2383
2384 if (i40e_update_adq_vsi_queues(vsi, i)) {
2385 aq_ret = I40E_ERR_CONFIG;
2386 goto error_param;
2387 }
2388 }
2389 }
2390
2391 error_param:
2392
2393 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
2394 aq_ret);
2395 }
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405 static int i40e_validate_queue_map(struct i40e_vf *vf, u16 vsi_id,
2406 unsigned long queuemap)
2407 {
2408 u16 vsi_queue_id, queue_id;
2409
2410 for_each_set_bit(vsi_queue_id, &queuemap, I40E_MAX_VSI_QP) {
2411 if (vf->adq_enabled) {
2412 vsi_id = vf->ch[vsi_queue_id / I40E_MAX_VF_VSI].vsi_id;
2413 queue_id = (vsi_queue_id % I40E_DEFAULT_QUEUES_PER_VF);
2414 } else {
2415 queue_id = vsi_queue_id;
2416 }
2417
2418 if (!i40e_vc_isvalid_queue_id(vf, vsi_id, queue_id))
2419 return -EINVAL;
2420 }
2421
2422 return 0;
2423 }
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433 static int i40e_vc_config_irq_map_msg(struct i40e_vf *vf, u8 *msg)
2434 {
2435 struct virtchnl_irq_map_info *irqmap_info =
2436 (struct virtchnl_irq_map_info *)msg;
2437 struct virtchnl_vector_map *map;
2438 u16 vsi_id;
2439 i40e_status aq_ret = 0;
2440 int i;
2441
2442 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
2443 aq_ret = I40E_ERR_PARAM;
2444 goto error_param;
2445 }
2446
2447 if (irqmap_info->num_vectors >
2448 vf->pf->hw.func_caps.num_msix_vectors_vf) {
2449 aq_ret = I40E_ERR_PARAM;
2450 goto error_param;
2451 }
2452
2453 for (i = 0; i < irqmap_info->num_vectors; i++) {
2454 map = &irqmap_info->vecmap[i];
2455
2456 if (!i40e_vc_isvalid_vector_id(vf, map->vector_id) ||
2457 !i40e_vc_isvalid_vsi_id(vf, map->vsi_id)) {
2458 aq_ret = I40E_ERR_PARAM;
2459 goto error_param;
2460 }
2461 vsi_id = map->vsi_id;
2462
2463 if (i40e_validate_queue_map(vf, vsi_id, map->rxq_map)) {
2464 aq_ret = I40E_ERR_PARAM;
2465 goto error_param;
2466 }
2467
2468 if (i40e_validate_queue_map(vf, vsi_id, map->txq_map)) {
2469 aq_ret = I40E_ERR_PARAM;
2470 goto error_param;
2471 }
2472
2473 i40e_config_irq_link_list(vf, vsi_id, map);
2474 }
2475 error_param:
2476
2477 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_CONFIG_IRQ_MAP,
2478 aq_ret);
2479 }
2480
2481
2482
2483
2484
2485
2486
2487 static int i40e_ctrl_vf_tx_rings(struct i40e_vsi *vsi, unsigned long q_map,
2488 bool enable)
2489 {
2490 struct i40e_pf *pf = vsi->back;
2491 int ret = 0;
2492 u16 q_id;
2493
2494 for_each_set_bit(q_id, &q_map, I40E_MAX_VF_QUEUES) {
2495 ret = i40e_control_wait_tx_q(vsi->seid, pf,
2496 vsi->base_queue + q_id,
2497 false , enable);
2498 if (ret)
2499 break;
2500 }
2501 return ret;
2502 }
2503
2504
2505
2506
2507
2508
2509
2510 static int i40e_ctrl_vf_rx_rings(struct i40e_vsi *vsi, unsigned long q_map,
2511 bool enable)
2512 {
2513 struct i40e_pf *pf = vsi->back;
2514 int ret = 0;
2515 u16 q_id;
2516
2517 for_each_set_bit(q_id, &q_map, I40E_MAX_VF_QUEUES) {
2518 ret = i40e_control_wait_rx_q(pf, vsi->base_queue + q_id,
2519 enable);
2520 if (ret)
2521 break;
2522 }
2523 return ret;
2524 }
2525
2526
2527
2528
2529
2530
2531
2532 static bool i40e_vc_validate_vqs_bitmaps(struct virtchnl_queue_select *vqs)
2533 {
2534 if ((!vqs->rx_queues && !vqs->tx_queues) ||
2535 vqs->rx_queues >= BIT(I40E_MAX_VF_QUEUES) ||
2536 vqs->tx_queues >= BIT(I40E_MAX_VF_QUEUES))
2537 return false;
2538
2539 return true;
2540 }
2541
2542
2543
2544
2545
2546
2547
2548
2549 static int i40e_vc_enable_queues_msg(struct i40e_vf *vf, u8 *msg)
2550 {
2551 struct virtchnl_queue_select *vqs =
2552 (struct virtchnl_queue_select *)msg;
2553 struct i40e_pf *pf = vf->pf;
2554 i40e_status aq_ret = 0;
2555 int i;
2556
2557 if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states)) {
2558 aq_ret = I40E_ERR_PARAM;
2559 goto error_param;
2560 }
2561
2562 if (!i40e_vc_isvalid_vsi_id(vf, vqs->vsi_id)) {
2563 aq_ret = I40E_ERR_PARAM;
2564 goto error_param;
2565 }
2566
2567 if (!i40e_vc_validate_vqs_bitmaps(vqs)) {
2568 aq_ret = I40E_ERR_PARAM;
2569 goto error_param;
2570 }
2571
2572
2573 if (i40e_ctrl_vf_rx_rings(pf->vsi[vf->lan_vsi_idx], vqs->rx_queues,
2574 true)) {
2575 aq_ret = I40E_ERR_TIMEOUT;
2576 goto error_param;
2577 }
2578 if (i40e_ctrl_vf_tx_rings(pf->vsi[vf->lan_vsi_idx], vqs->tx_queues,
2579 true)) {
2580 aq_ret = I40E_ERR_TIMEOUT;
2581 goto error_param;
2582 }
2583
2584
2585 if (vf->adq_enabled) {
2586
2587 for (i = 1; i < vf->num_tc; i++) {
2588 if (i40e_vsi_start_rings(pf->vsi[vf->ch[i].vsi_idx]))
2589 aq_ret = I40E_ERR_TIMEOUT;
2590 }
2591 }
2592
2593 error_param:
2594
2595 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_ENABLE_QUEUES,
2596 aq_ret);
2597 }
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607 static int i40e_vc_disable_queues_msg(struct i40e_vf *vf, u8 *msg)
2608 {
2609 struct virtchnl_queue_select *vqs =
2610 (struct virtchnl_queue_select *)msg;
2611 struct i40e_pf *pf = vf->pf;
2612 i40e_status aq_ret = 0;
2613
2614 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
2615 aq_ret = I40E_ERR_PARAM;
2616 goto error_param;
2617 }
2618
2619 if (!i40e_vc_isvalid_vsi_id(vf, vqs->vsi_id)) {
2620 aq_ret = I40E_ERR_PARAM;
2621 goto error_param;
2622 }
2623
2624 if (!i40e_vc_validate_vqs_bitmaps(vqs)) {
2625 aq_ret = I40E_ERR_PARAM;
2626 goto error_param;
2627 }
2628
2629
2630 if (i40e_ctrl_vf_tx_rings(pf->vsi[vf->lan_vsi_idx], vqs->tx_queues,
2631 false)) {
2632 aq_ret = I40E_ERR_TIMEOUT;
2633 goto error_param;
2634 }
2635 if (i40e_ctrl_vf_rx_rings(pf->vsi[vf->lan_vsi_idx], vqs->rx_queues,
2636 false)) {
2637 aq_ret = I40E_ERR_TIMEOUT;
2638 goto error_param;
2639 }
2640 error_param:
2641
2642 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DISABLE_QUEUES,
2643 aq_ret);
2644 }
2645
2646
2647
2648
2649
2650
2651
2652
2653 static int i40e_check_enough_queue(struct i40e_vf *vf, u16 needed)
2654 {
2655 unsigned int i, cur_queues, more, pool_size;
2656 struct i40e_lump_tracking *pile;
2657 struct i40e_pf *pf = vf->pf;
2658 struct i40e_vsi *vsi;
2659
2660 vsi = pf->vsi[vf->lan_vsi_idx];
2661 cur_queues = vsi->alloc_queue_pairs;
2662
2663
2664 if (cur_queues >= needed)
2665 return vsi->base_queue;
2666
2667 pile = pf->qp_pile;
2668 if (cur_queues > 0) {
2669
2670
2671
2672
2673 more = needed - cur_queues;
2674 for (i = vsi->base_queue + cur_queues;
2675 i < pile->num_entries; i++) {
2676 if (pile->list[i] & I40E_PILE_VALID_BIT)
2677 break;
2678
2679 if (more-- == 1)
2680
2681 return vsi->base_queue;
2682 }
2683 }
2684
2685 pool_size = 0;
2686 for (i = 0; i < pile->num_entries; i++) {
2687 if (pile->list[i] & I40E_PILE_VALID_BIT) {
2688 pool_size = 0;
2689 continue;
2690 }
2691 if (needed <= ++pool_size)
2692
2693 return i;
2694 }
2695
2696 return -ENOMEM;
2697 }
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709 static int i40e_vc_request_queues_msg(struct i40e_vf *vf, u8 *msg)
2710 {
2711 struct virtchnl_vf_res_request *vfres =
2712 (struct virtchnl_vf_res_request *)msg;
2713 u16 req_pairs = vfres->num_queue_pairs;
2714 u8 cur_pairs = vf->num_queue_pairs;
2715 struct i40e_pf *pf = vf->pf;
2716
2717 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE))
2718 return -EINVAL;
2719
2720 if (req_pairs > I40E_MAX_VF_QUEUES) {
2721 dev_err(&pf->pdev->dev,
2722 "VF %d tried to request more than %d queues.\n",
2723 vf->vf_id,
2724 I40E_MAX_VF_QUEUES);
2725 vfres->num_queue_pairs = I40E_MAX_VF_QUEUES;
2726 } else if (req_pairs - cur_pairs > pf->queues_left) {
2727 dev_warn(&pf->pdev->dev,
2728 "VF %d requested %d more queues, but only %d left.\n",
2729 vf->vf_id,
2730 req_pairs - cur_pairs,
2731 pf->queues_left);
2732 vfres->num_queue_pairs = pf->queues_left + cur_pairs;
2733 } else if (i40e_check_enough_queue(vf, req_pairs) < 0) {
2734 dev_warn(&pf->pdev->dev,
2735 "VF %d requested %d more queues, but there is not enough for it.\n",
2736 vf->vf_id,
2737 req_pairs - cur_pairs);
2738 vfres->num_queue_pairs = cur_pairs;
2739 } else {
2740
2741 vf->num_req_queues = req_pairs;
2742 i40e_vc_reset_vf(vf, true);
2743 return 0;
2744 }
2745
2746 return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_REQUEST_QUEUES, 0,
2747 (u8 *)vfres, sizeof(*vfres));
2748 }
2749
2750
2751
2752
2753
2754
2755
2756
2757 static int i40e_vc_get_stats_msg(struct i40e_vf *vf, u8 *msg)
2758 {
2759 struct virtchnl_queue_select *vqs =
2760 (struct virtchnl_queue_select *)msg;
2761 struct i40e_pf *pf = vf->pf;
2762 struct i40e_eth_stats stats;
2763 i40e_status aq_ret = 0;
2764 struct i40e_vsi *vsi;
2765
2766 memset(&stats, 0, sizeof(struct i40e_eth_stats));
2767
2768 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
2769 aq_ret = I40E_ERR_PARAM;
2770 goto error_param;
2771 }
2772
2773 if (!i40e_vc_isvalid_vsi_id(vf, vqs->vsi_id)) {
2774 aq_ret = I40E_ERR_PARAM;
2775 goto error_param;
2776 }
2777
2778 vsi = pf->vsi[vf->lan_vsi_idx];
2779 if (!vsi) {
2780 aq_ret = I40E_ERR_PARAM;
2781 goto error_param;
2782 }
2783 i40e_update_eth_stats(vsi);
2784 stats = vsi->eth_stats;
2785
2786 error_param:
2787
2788 return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS, aq_ret,
2789 (u8 *)&stats, sizeof(stats));
2790 }
2791
2792 #define I40E_MAX_MACVLAN_PER_HW 3072
2793 #define I40E_MAX_MACVLAN_PER_PF(num_ports) (I40E_MAX_MACVLAN_PER_HW / \
2794 (num_ports))
2795
2796
2797
2798 #define I40E_VC_MAX_MAC_ADDR_PER_VF (16 + 1 + 1)
2799 #define I40E_VC_MAX_VLAN_PER_VF 16
2800
2801 #define I40E_VC_MAX_MACVLAN_PER_TRUSTED_VF(vf_num, num_ports) \
2802 ({ typeof(vf_num) vf_num_ = (vf_num); \
2803 typeof(num_ports) num_ports_ = (num_ports); \
2804 ((I40E_MAX_MACVLAN_PER_PF(num_ports_) - vf_num_ * \
2805 I40E_VC_MAX_MAC_ADDR_PER_VF) / vf_num_) + \
2806 I40E_VC_MAX_MAC_ADDR_PER_VF; })
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824 static inline int i40e_check_vf_permission(struct i40e_vf *vf,
2825 struct virtchnl_ether_addr_list *al)
2826 {
2827 struct i40e_pf *pf = vf->pf;
2828 struct i40e_vsi *vsi = pf->vsi[vf->lan_vsi_idx];
2829 struct i40e_hw *hw = &pf->hw;
2830 int mac2add_cnt = 0;
2831 int i;
2832
2833 for (i = 0; i < al->num_elements; i++) {
2834 struct i40e_mac_filter *f;
2835 u8 *addr = al->list[i].addr;
2836
2837 if (is_broadcast_ether_addr(addr) ||
2838 is_zero_ether_addr(addr)) {
2839 dev_err(&pf->pdev->dev, "invalid VF MAC addr %pM\n",
2840 addr);
2841 return I40E_ERR_INVALID_MAC_ADDR;
2842 }
2843
2844
2845
2846
2847
2848
2849
2850
2851 if (!test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps) &&
2852 !is_multicast_ether_addr(addr) && vf->pf_set_mac &&
2853 !ether_addr_equal(addr, vf->default_lan_addr.addr)) {
2854 dev_err(&pf->pdev->dev,
2855 "VF attempting to override administratively set MAC address, bring down and up the VF interface to resume normal operation\n");
2856 return -EPERM;
2857 }
2858
2859
2860 f = i40e_find_mac(vsi, addr);
2861 if (!f)
2862 ++mac2add_cnt;
2863 }
2864
2865
2866
2867
2868
2869 if (!test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
2870 if ((i40e_count_filters(vsi) + mac2add_cnt) >
2871 I40E_VC_MAX_MAC_ADDR_PER_VF) {
2872 dev_err(&pf->pdev->dev,
2873 "Cannot add more MAC addresses, VF is not trusted, switch the VF to trusted to add more functionality\n");
2874 return -EPERM;
2875 }
2876
2877
2878
2879
2880
2881 } else {
2882 if ((i40e_count_filters(vsi) + mac2add_cnt) >
2883 I40E_VC_MAX_MACVLAN_PER_TRUSTED_VF(pf->num_alloc_vfs,
2884 hw->num_ports)) {
2885 dev_err(&pf->pdev->dev,
2886 "Cannot add more MAC addresses, trusted VF exhausted it's resources\n");
2887 return -EPERM;
2888 }
2889 }
2890 return 0;
2891 }
2892
2893
2894
2895
2896
2897
2898
2899
2900 static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg)
2901 {
2902 struct virtchnl_ether_addr_list *al =
2903 (struct virtchnl_ether_addr_list *)msg;
2904 struct i40e_pf *pf = vf->pf;
2905 struct i40e_vsi *vsi = NULL;
2906 i40e_status ret = 0;
2907 int i;
2908
2909 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
2910 !i40e_vc_isvalid_vsi_id(vf, al->vsi_id)) {
2911 ret = I40E_ERR_PARAM;
2912 goto error_param;
2913 }
2914
2915 vsi = pf->vsi[vf->lan_vsi_idx];
2916
2917
2918
2919
2920 spin_lock_bh(&vsi->mac_filter_hash_lock);
2921
2922 ret = i40e_check_vf_permission(vf, al);
2923 if (ret) {
2924 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2925 goto error_param;
2926 }
2927
2928
2929 for (i = 0; i < al->num_elements; i++) {
2930 struct i40e_mac_filter *f;
2931
2932 f = i40e_find_mac(vsi, al->list[i].addr);
2933 if (!f) {
2934 f = i40e_add_mac_filter(vsi, al->list[i].addr);
2935
2936 if (!f) {
2937 dev_err(&pf->pdev->dev,
2938 "Unable to add MAC filter %pM for VF %d\n",
2939 al->list[i].addr, vf->vf_id);
2940 ret = I40E_ERR_PARAM;
2941 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2942 goto error_param;
2943 }
2944 if (is_valid_ether_addr(al->list[i].addr) &&
2945 is_zero_ether_addr(vf->default_lan_addr.addr))
2946 ether_addr_copy(vf->default_lan_addr.addr,
2947 al->list[i].addr);
2948 }
2949 }
2950 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2951
2952
2953 ret = i40e_sync_vsi_filters(vsi);
2954 if (ret)
2955 dev_err(&pf->pdev->dev, "Unable to program VF %d MAC filters, error %d\n",
2956 vf->vf_id, ret);
2957
2958 error_param:
2959
2960 return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_ETH_ADDR,
2961 ret, NULL, 0);
2962 }
2963
2964
2965
2966
2967
2968
2969
2970
2971 static int i40e_vc_del_mac_addr_msg(struct i40e_vf *vf, u8 *msg)
2972 {
2973 struct virtchnl_ether_addr_list *al =
2974 (struct virtchnl_ether_addr_list *)msg;
2975 bool was_unimac_deleted = false;
2976 struct i40e_pf *pf = vf->pf;
2977 struct i40e_vsi *vsi = NULL;
2978 i40e_status ret = 0;
2979 int i;
2980
2981 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
2982 !i40e_vc_isvalid_vsi_id(vf, al->vsi_id)) {
2983 ret = I40E_ERR_PARAM;
2984 goto error_param;
2985 }
2986
2987 for (i = 0; i < al->num_elements; i++) {
2988 if (is_broadcast_ether_addr(al->list[i].addr) ||
2989 is_zero_ether_addr(al->list[i].addr)) {
2990 dev_err(&pf->pdev->dev, "Invalid MAC addr %pM for VF %d\n",
2991 al->list[i].addr, vf->vf_id);
2992 ret = I40E_ERR_INVALID_MAC_ADDR;
2993 goto error_param;
2994 }
2995 if (ether_addr_equal(al->list[i].addr, vf->default_lan_addr.addr))
2996 was_unimac_deleted = true;
2997 }
2998 vsi = pf->vsi[vf->lan_vsi_idx];
2999
3000 spin_lock_bh(&vsi->mac_filter_hash_lock);
3001
3002 for (i = 0; i < al->num_elements; i++)
3003 if (i40e_del_mac_filter(vsi, al->list[i].addr)) {
3004 ret = I40E_ERR_INVALID_MAC_ADDR;
3005 spin_unlock_bh(&vsi->mac_filter_hash_lock);
3006 goto error_param;
3007 }
3008
3009 spin_unlock_bh(&vsi->mac_filter_hash_lock);
3010
3011
3012 ret = i40e_sync_vsi_filters(vsi);
3013 if (ret)
3014 dev_err(&pf->pdev->dev, "Unable to program VF %d MAC filters, error %d\n",
3015 vf->vf_id, ret);
3016
3017 if (vf->trusted && was_unimac_deleted) {
3018 struct i40e_mac_filter *f;
3019 struct hlist_node *h;
3020 u8 *macaddr = NULL;
3021 int bkt;
3022
3023
3024 spin_lock_bh(&vsi->mac_filter_hash_lock);
3025 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
3026 if (is_valid_ether_addr(f->macaddr))
3027 macaddr = f->macaddr;
3028 }
3029 if (macaddr)
3030 ether_addr_copy(vf->default_lan_addr.addr, macaddr);
3031 spin_unlock_bh(&vsi->mac_filter_hash_lock);
3032 }
3033 error_param:
3034
3035 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DEL_ETH_ADDR, ret);
3036 }
3037
3038
3039
3040
3041
3042
3043
3044
3045 static int i40e_vc_add_vlan_msg(struct i40e_vf *vf, u8 *msg)
3046 {
3047 struct virtchnl_vlan_filter_list *vfl =
3048 (struct virtchnl_vlan_filter_list *)msg;
3049 struct i40e_pf *pf = vf->pf;
3050 struct i40e_vsi *vsi = NULL;
3051 i40e_status aq_ret = 0;
3052 int i;
3053
3054 if ((vf->num_vlan >= I40E_VC_MAX_VLAN_PER_VF) &&
3055 !test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
3056 dev_err(&pf->pdev->dev,
3057 "VF is not trusted, switch the VF to trusted to add more VLAN addresses\n");
3058 goto error_param;
3059 }
3060 if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states) ||
3061 !i40e_vc_isvalid_vsi_id(vf, vfl->vsi_id)) {
3062 aq_ret = I40E_ERR_PARAM;
3063 goto error_param;
3064 }
3065
3066 for (i = 0; i < vfl->num_elements; i++) {
3067 if (vfl->vlan_id[i] > I40E_MAX_VLANID) {
3068 aq_ret = I40E_ERR_PARAM;
3069 dev_err(&pf->pdev->dev,
3070 "invalid VF VLAN id %d\n", vfl->vlan_id[i]);
3071 goto error_param;
3072 }
3073 }
3074 vsi = pf->vsi[vf->lan_vsi_idx];
3075 if (vsi->info.pvid) {
3076 aq_ret = I40E_ERR_PARAM;
3077 goto error_param;
3078 }
3079
3080 i40e_vlan_stripping_enable(vsi);
3081 for (i = 0; i < vfl->num_elements; i++) {
3082
3083 int ret = i40e_vsi_add_vlan(vsi, vfl->vlan_id[i]);
3084 if (!ret)
3085 vf->num_vlan++;
3086
3087 if (test_bit(I40E_VF_STATE_UC_PROMISC, &vf->vf_states))
3088 i40e_aq_set_vsi_uc_promisc_on_vlan(&pf->hw, vsi->seid,
3089 true,
3090 vfl->vlan_id[i],
3091 NULL);
3092 if (test_bit(I40E_VF_STATE_MC_PROMISC, &vf->vf_states))
3093 i40e_aq_set_vsi_mc_promisc_on_vlan(&pf->hw, vsi->seid,
3094 true,
3095 vfl->vlan_id[i],
3096 NULL);
3097
3098 if (ret)
3099 dev_err(&pf->pdev->dev,
3100 "Unable to add VLAN filter %d for VF %d, error %d\n",
3101 vfl->vlan_id[i], vf->vf_id, ret);
3102 }
3103
3104 error_param:
3105
3106 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_ADD_VLAN, aq_ret);
3107 }
3108
3109
3110
3111
3112
3113
3114
3115
3116 static int i40e_vc_remove_vlan_msg(struct i40e_vf *vf, u8 *msg)
3117 {
3118 struct virtchnl_vlan_filter_list *vfl =
3119 (struct virtchnl_vlan_filter_list *)msg;
3120 struct i40e_pf *pf = vf->pf;
3121 struct i40e_vsi *vsi = NULL;
3122 i40e_status aq_ret = 0;
3123 int i;
3124
3125 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
3126 !i40e_vc_isvalid_vsi_id(vf, vfl->vsi_id)) {
3127 aq_ret = I40E_ERR_PARAM;
3128 goto error_param;
3129 }
3130
3131 for (i = 0; i < vfl->num_elements; i++) {
3132 if (vfl->vlan_id[i] > I40E_MAX_VLANID) {
3133 aq_ret = I40E_ERR_PARAM;
3134 goto error_param;
3135 }
3136 }
3137
3138 vsi = pf->vsi[vf->lan_vsi_idx];
3139 if (vsi->info.pvid) {
3140 if (vfl->num_elements > 1 || vfl->vlan_id[0])
3141 aq_ret = I40E_ERR_PARAM;
3142 goto error_param;
3143 }
3144
3145 for (i = 0; i < vfl->num_elements; i++) {
3146 i40e_vsi_kill_vlan(vsi, vfl->vlan_id[i]);
3147 vf->num_vlan--;
3148
3149 if (test_bit(I40E_VF_STATE_UC_PROMISC, &vf->vf_states))
3150 i40e_aq_set_vsi_uc_promisc_on_vlan(&pf->hw, vsi->seid,
3151 false,
3152 vfl->vlan_id[i],
3153 NULL);
3154 if (test_bit(I40E_VF_STATE_MC_PROMISC, &vf->vf_states))
3155 i40e_aq_set_vsi_mc_promisc_on_vlan(&pf->hw, vsi->seid,
3156 false,
3157 vfl->vlan_id[i],
3158 NULL);
3159 }
3160
3161 error_param:
3162
3163 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DEL_VLAN, aq_ret);
3164 }
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174 static int i40e_vc_iwarp_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
3175 {
3176 struct i40e_pf *pf = vf->pf;
3177 int abs_vf_id = vf->vf_id + pf->hw.func_caps.vf_base_id;
3178 i40e_status aq_ret = 0;
3179
3180 if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states) ||
3181 !test_bit(I40E_VF_STATE_IWARPENA, &vf->vf_states)) {
3182 aq_ret = I40E_ERR_PARAM;
3183 goto error_param;
3184 }
3185
3186 i40e_notify_client_of_vf_msg(pf->vsi[pf->lan_vsi], abs_vf_id,
3187 msg, msglen);
3188
3189 error_param:
3190
3191 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_IWARP,
3192 aq_ret);
3193 }
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203 static int i40e_vc_iwarp_qvmap_msg(struct i40e_vf *vf, u8 *msg, bool config)
3204 {
3205 struct virtchnl_iwarp_qvlist_info *qvlist_info =
3206 (struct virtchnl_iwarp_qvlist_info *)msg;
3207 i40e_status aq_ret = 0;
3208
3209 if (!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states) ||
3210 !test_bit(I40E_VF_STATE_IWARPENA, &vf->vf_states)) {
3211 aq_ret = I40E_ERR_PARAM;
3212 goto error_param;
3213 }
3214
3215 if (config) {
3216 if (i40e_config_iwarp_qvlist(vf, qvlist_info))
3217 aq_ret = I40E_ERR_PARAM;
3218 } else {
3219 i40e_release_iwarp_qvlist(vf);
3220 }
3221
3222 error_param:
3223
3224 return i40e_vc_send_resp_to_vf(vf,
3225 config ? VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP :
3226 VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP,
3227 aq_ret);
3228 }
3229
3230
3231
3232
3233
3234
3235
3236
3237 static int i40e_vc_config_rss_key(struct i40e_vf *vf, u8 *msg)
3238 {
3239 struct virtchnl_rss_key *vrk =
3240 (struct virtchnl_rss_key *)msg;
3241 struct i40e_pf *pf = vf->pf;
3242 struct i40e_vsi *vsi = NULL;
3243 i40e_status aq_ret = 0;
3244
3245 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
3246 !i40e_vc_isvalid_vsi_id(vf, vrk->vsi_id) ||
3247 vrk->key_len != I40E_HKEY_ARRAY_SIZE) {
3248 aq_ret = I40E_ERR_PARAM;
3249 goto err;
3250 }
3251
3252 vsi = pf->vsi[vf->lan_vsi_idx];
3253 aq_ret = i40e_config_rss(vsi, vrk->key, NULL, 0);
3254 err:
3255
3256 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_KEY,
3257 aq_ret);
3258 }
3259
3260
3261
3262
3263
3264
3265
3266
3267 static int i40e_vc_config_rss_lut(struct i40e_vf *vf, u8 *msg)
3268 {
3269 struct virtchnl_rss_lut *vrl =
3270 (struct virtchnl_rss_lut *)msg;
3271 struct i40e_pf *pf = vf->pf;
3272 struct i40e_vsi *vsi = NULL;
3273 i40e_status aq_ret = 0;
3274 u16 i;
3275
3276 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE) ||
3277 !i40e_vc_isvalid_vsi_id(vf, vrl->vsi_id) ||
3278 vrl->lut_entries != I40E_VF_HLUT_ARRAY_SIZE) {
3279 aq_ret = I40E_ERR_PARAM;
3280 goto err;
3281 }
3282
3283 for (i = 0; i < vrl->lut_entries; i++)
3284 if (vrl->lut[i] >= vf->num_queue_pairs) {
3285 aq_ret = I40E_ERR_PARAM;
3286 goto err;
3287 }
3288
3289 vsi = pf->vsi[vf->lan_vsi_idx];
3290 aq_ret = i40e_config_rss(vsi, NULL, vrl->lut, I40E_VF_HLUT_ARRAY_SIZE);
3291
3292 err:
3293 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_LUT,
3294 aq_ret);
3295 }
3296
3297
3298
3299
3300
3301
3302
3303
3304 static int i40e_vc_get_rss_hena(struct i40e_vf *vf, u8 *msg)
3305 {
3306 struct virtchnl_rss_hena *vrh = NULL;
3307 struct i40e_pf *pf = vf->pf;
3308 i40e_status aq_ret = 0;
3309 int len = 0;
3310
3311 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3312 aq_ret = I40E_ERR_PARAM;
3313 goto err;
3314 }
3315 len = sizeof(struct virtchnl_rss_hena);
3316
3317 vrh = kzalloc(len, GFP_KERNEL);
3318 if (!vrh) {
3319 aq_ret = I40E_ERR_NO_MEMORY;
3320 len = 0;
3321 goto err;
3322 }
3323 vrh->hena = i40e_pf_get_default_rss_hena(pf);
3324 err:
3325
3326 aq_ret = i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_GET_RSS_HENA_CAPS,
3327 aq_ret, (u8 *)vrh, len);
3328 kfree(vrh);
3329 return aq_ret;
3330 }
3331
3332
3333
3334
3335
3336
3337
3338
3339 static int i40e_vc_set_rss_hena(struct i40e_vf *vf, u8 *msg)
3340 {
3341 struct virtchnl_rss_hena *vrh =
3342 (struct virtchnl_rss_hena *)msg;
3343 struct i40e_pf *pf = vf->pf;
3344 struct i40e_hw *hw = &pf->hw;
3345 i40e_status aq_ret = 0;
3346
3347 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3348 aq_ret = I40E_ERR_PARAM;
3349 goto err;
3350 }
3351 i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, vf->vf_id), (u32)vrh->hena);
3352 i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, vf->vf_id),
3353 (u32)(vrh->hena >> 32));
3354
3355
3356 err:
3357 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_SET_RSS_HENA, aq_ret);
3358 }
3359
3360
3361
3362
3363
3364
3365
3366
3367 static int i40e_vc_enable_vlan_stripping(struct i40e_vf *vf, u8 *msg)
3368 {
3369 i40e_status aq_ret = 0;
3370 struct i40e_vsi *vsi;
3371
3372 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3373 aq_ret = I40E_ERR_PARAM;
3374 goto err;
3375 }
3376
3377 vsi = vf->pf->vsi[vf->lan_vsi_idx];
3378 i40e_vlan_stripping_enable(vsi);
3379
3380
3381 err:
3382 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
3383 aq_ret);
3384 }
3385
3386
3387
3388
3389
3390
3391
3392
3393 static int i40e_vc_disable_vlan_stripping(struct i40e_vf *vf, u8 *msg)
3394 {
3395 i40e_status aq_ret = 0;
3396 struct i40e_vsi *vsi;
3397
3398 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3399 aq_ret = I40E_ERR_PARAM;
3400 goto err;
3401 }
3402
3403 vsi = vf->pf->vsi[vf->lan_vsi_idx];
3404 i40e_vlan_stripping_disable(vsi);
3405
3406
3407 err:
3408 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
3409 aq_ret);
3410 }
3411
3412
3413
3414
3415
3416
3417
3418
3419 static int i40e_validate_cloud_filter(struct i40e_vf *vf,
3420 struct virtchnl_filter *tc_filter)
3421 {
3422 struct virtchnl_l4_spec mask = tc_filter->mask.tcp_spec;
3423 struct virtchnl_l4_spec data = tc_filter->data.tcp_spec;
3424 struct i40e_pf *pf = vf->pf;
3425 struct i40e_vsi *vsi = NULL;
3426 struct i40e_mac_filter *f;
3427 struct hlist_node *h;
3428 bool found = false;
3429 int bkt;
3430
3431 if (!tc_filter->action) {
3432 dev_info(&pf->pdev->dev,
3433 "VF %d: Currently ADq doesn't support Drop Action\n",
3434 vf->vf_id);
3435 goto err;
3436 }
3437
3438
3439 if (!tc_filter->action_meta ||
3440 tc_filter->action_meta > I40E_MAX_VF_VSI) {
3441 dev_info(&pf->pdev->dev, "VF %d: Invalid TC number %u\n",
3442 vf->vf_id, tc_filter->action_meta);
3443 goto err;
3444 }
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455 if (mask.dst_mac[0] && !mask.dst_ip[0]) {
3456 vsi = pf->vsi[vf->lan_vsi_idx];
3457 f = i40e_find_mac(vsi, data.dst_mac);
3458
3459 if (!f) {
3460 dev_info(&pf->pdev->dev,
3461 "Destination MAC %pM doesn't belong to VF %d\n",
3462 data.dst_mac, vf->vf_id);
3463 goto err;
3464 }
3465
3466 if (mask.vlan_id) {
3467 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f,
3468 hlist) {
3469 if (f->vlan == ntohs(data.vlan_id)) {
3470 found = true;
3471 break;
3472 }
3473 }
3474 if (!found) {
3475 dev_info(&pf->pdev->dev,
3476 "VF %d doesn't have any VLAN id %u\n",
3477 vf->vf_id, ntohs(data.vlan_id));
3478 goto err;
3479 }
3480 }
3481 } else {
3482
3483 if (!test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
3484 dev_err(&pf->pdev->dev,
3485 "VF %d not trusted, make VF trusted to add advanced mode ADq cloud filters\n",
3486 vf->vf_id);
3487 return I40E_ERR_CONFIG;
3488 }
3489 }
3490
3491 if (mask.dst_mac[0] & data.dst_mac[0]) {
3492 if (is_broadcast_ether_addr(data.dst_mac) ||
3493 is_zero_ether_addr(data.dst_mac)) {
3494 dev_info(&pf->pdev->dev, "VF %d: Invalid Dest MAC addr %pM\n",
3495 vf->vf_id, data.dst_mac);
3496 goto err;
3497 }
3498 }
3499
3500 if (mask.src_mac[0] & data.src_mac[0]) {
3501 if (is_broadcast_ether_addr(data.src_mac) ||
3502 is_zero_ether_addr(data.src_mac)) {
3503 dev_info(&pf->pdev->dev, "VF %d: Invalid Source MAC addr %pM\n",
3504 vf->vf_id, data.src_mac);
3505 goto err;
3506 }
3507 }
3508
3509 if (mask.dst_port & data.dst_port) {
3510 if (!data.dst_port) {
3511 dev_info(&pf->pdev->dev, "VF %d: Invalid Dest port\n",
3512 vf->vf_id);
3513 goto err;
3514 }
3515 }
3516
3517 if (mask.src_port & data.src_port) {
3518 if (!data.src_port) {
3519 dev_info(&pf->pdev->dev, "VF %d: Invalid Source port\n",
3520 vf->vf_id);
3521 goto err;
3522 }
3523 }
3524
3525 if (tc_filter->flow_type != VIRTCHNL_TCP_V6_FLOW &&
3526 tc_filter->flow_type != VIRTCHNL_TCP_V4_FLOW) {
3527 dev_info(&pf->pdev->dev, "VF %d: Invalid Flow type\n",
3528 vf->vf_id);
3529 goto err;
3530 }
3531
3532 if (mask.vlan_id & data.vlan_id) {
3533 if (ntohs(data.vlan_id) > I40E_MAX_VLANID) {
3534 dev_info(&pf->pdev->dev, "VF %d: invalid VLAN ID\n",
3535 vf->vf_id);
3536 goto err;
3537 }
3538 }
3539
3540 return I40E_SUCCESS;
3541 err:
3542 return I40E_ERR_CONFIG;
3543 }
3544
3545
3546
3547
3548
3549
3550 static struct i40e_vsi *i40e_find_vsi_from_seid(struct i40e_vf *vf, u16 seid)
3551 {
3552 struct i40e_pf *pf = vf->pf;
3553 struct i40e_vsi *vsi = NULL;
3554 int i;
3555
3556 for (i = 0; i < vf->num_tc ; i++) {
3557 vsi = i40e_find_vsi_from_id(pf, vf->ch[i].vsi_id);
3558 if (vsi && vsi->seid == seid)
3559 return vsi;
3560 }
3561 return NULL;
3562 }
3563
3564
3565
3566
3567
3568
3569
3570 static void i40e_del_all_cloud_filters(struct i40e_vf *vf)
3571 {
3572 struct i40e_cloud_filter *cfilter = NULL;
3573 struct i40e_pf *pf = vf->pf;
3574 struct i40e_vsi *vsi = NULL;
3575 struct hlist_node *node;
3576 int ret;
3577
3578 hlist_for_each_entry_safe(cfilter, node,
3579 &vf->cloud_filter_list, cloud_node) {
3580 vsi = i40e_find_vsi_from_seid(vf, cfilter->seid);
3581
3582 if (!vsi) {
3583 dev_err(&pf->pdev->dev, "VF %d: no VSI found for matching %u seid, can't delete cloud filter\n",
3584 vf->vf_id, cfilter->seid);
3585 continue;
3586 }
3587
3588 if (cfilter->dst_port)
3589 ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter,
3590 false);
3591 else
3592 ret = i40e_add_del_cloud_filter(vsi, cfilter, false);
3593 if (ret)
3594 dev_err(&pf->pdev->dev,
3595 "VF %d: Failed to delete cloud filter, err %s aq_err %s\n",
3596 vf->vf_id, i40e_stat_str(&pf->hw, ret),
3597 i40e_aq_str(&pf->hw,
3598 pf->hw.aq.asq_last_status));
3599
3600 hlist_del(&cfilter->cloud_node);
3601 kfree(cfilter);
3602 vf->num_cloud_filters--;
3603 }
3604 }
3605
3606
3607
3608
3609
3610
3611
3612
3613 static int i40e_vc_del_cloud_filter(struct i40e_vf *vf, u8 *msg)
3614 {
3615 struct virtchnl_filter *vcf = (struct virtchnl_filter *)msg;
3616 struct virtchnl_l4_spec mask = vcf->mask.tcp_spec;
3617 struct virtchnl_l4_spec tcf = vcf->data.tcp_spec;
3618 struct i40e_cloud_filter cfilter, *cf = NULL;
3619 struct i40e_pf *pf = vf->pf;
3620 struct i40e_vsi *vsi = NULL;
3621 struct hlist_node *node;
3622 i40e_status aq_ret = 0;
3623 int i, ret;
3624
3625 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3626 aq_ret = I40E_ERR_PARAM;
3627 goto err;
3628 }
3629
3630 if (!vf->adq_enabled) {
3631 dev_info(&pf->pdev->dev,
3632 "VF %d: ADq not enabled, can't apply cloud filter\n",
3633 vf->vf_id);
3634 aq_ret = I40E_ERR_PARAM;
3635 goto err;
3636 }
3637
3638 if (i40e_validate_cloud_filter(vf, vcf)) {
3639 dev_info(&pf->pdev->dev,
3640 "VF %d: Invalid input, can't apply cloud filter\n",
3641 vf->vf_id);
3642 aq_ret = I40E_ERR_PARAM;
3643 goto err;
3644 }
3645
3646 memset(&cfilter, 0, sizeof(cfilter));
3647
3648 for (i = 0; i < ETH_ALEN; i++)
3649 cfilter.dst_mac[i] = mask.dst_mac[i] & tcf.dst_mac[i];
3650
3651
3652 for (i = 0; i < ETH_ALEN; i++)
3653 cfilter.src_mac[i] = mask.src_mac[i] & tcf.src_mac[i];
3654
3655 cfilter.vlan_id = mask.vlan_id & tcf.vlan_id;
3656 cfilter.dst_port = mask.dst_port & tcf.dst_port;
3657 cfilter.src_port = mask.src_port & tcf.src_port;
3658
3659 switch (vcf->flow_type) {
3660 case VIRTCHNL_TCP_V4_FLOW:
3661 cfilter.n_proto = ETH_P_IP;
3662 if (mask.dst_ip[0] & tcf.dst_ip[0])
3663 memcpy(&cfilter.ip.v4.dst_ip, tcf.dst_ip,
3664 ARRAY_SIZE(tcf.dst_ip));
3665 else if (mask.src_ip[0] & tcf.dst_ip[0])
3666 memcpy(&cfilter.ip.v4.src_ip, tcf.src_ip,
3667 ARRAY_SIZE(tcf.dst_ip));
3668 break;
3669 case VIRTCHNL_TCP_V6_FLOW:
3670 cfilter.n_proto = ETH_P_IPV6;
3671 if (mask.dst_ip[3] & tcf.dst_ip[3])
3672 memcpy(&cfilter.ip.v6.dst_ip6, tcf.dst_ip,
3673 sizeof(cfilter.ip.v6.dst_ip6));
3674 if (mask.src_ip[3] & tcf.src_ip[3])
3675 memcpy(&cfilter.ip.v6.src_ip6, tcf.src_ip,
3676 sizeof(cfilter.ip.v6.src_ip6));
3677 break;
3678 default:
3679
3680
3681
3682 dev_info(&pf->pdev->dev, "VF %d: Flow type not configured\n",
3683 vf->vf_id);
3684 }
3685
3686
3687 vsi = pf->vsi[vf->ch[vcf->action_meta].vsi_idx];
3688 cfilter.seid = vsi->seid;
3689 cfilter.flags = vcf->field_flags;
3690
3691
3692 if (tcf.dst_port)
3693 ret = i40e_add_del_cloud_filter_big_buf(vsi, &cfilter, false);
3694 else
3695 ret = i40e_add_del_cloud_filter(vsi, &cfilter, false);
3696 if (ret) {
3697 dev_err(&pf->pdev->dev,
3698 "VF %d: Failed to delete cloud filter, err %s aq_err %s\n",
3699 vf->vf_id, i40e_stat_str(&pf->hw, ret),
3700 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
3701 goto err;
3702 }
3703
3704 hlist_for_each_entry_safe(cf, node,
3705 &vf->cloud_filter_list, cloud_node) {
3706 if (cf->seid != cfilter.seid)
3707 continue;
3708 if (mask.dst_port)
3709 if (cfilter.dst_port != cf->dst_port)
3710 continue;
3711 if (mask.dst_mac[0])
3712 if (!ether_addr_equal(cf->src_mac, cfilter.src_mac))
3713 continue;
3714
3715 if (cfilter.n_proto == ETH_P_IP && mask.dst_ip[0])
3716 if (memcmp(&cfilter.ip.v4.dst_ip, &cf->ip.v4.dst_ip,
3717 ARRAY_SIZE(tcf.dst_ip)))
3718 continue;
3719
3720 if (cfilter.n_proto == ETH_P_IPV6 && mask.dst_ip[3])
3721 if (memcmp(&cfilter.ip.v6.dst_ip6, &cf->ip.v6.dst_ip6,
3722 sizeof(cfilter.ip.v6.src_ip6)))
3723 continue;
3724 if (mask.vlan_id)
3725 if (cfilter.vlan_id != cf->vlan_id)
3726 continue;
3727
3728 hlist_del(&cf->cloud_node);
3729 kfree(cf);
3730 vf->num_cloud_filters--;
3731 }
3732
3733 err:
3734 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DEL_CLOUD_FILTER,
3735 aq_ret);
3736 }
3737
3738
3739
3740
3741
3742
3743
3744
3745 static int i40e_vc_add_cloud_filter(struct i40e_vf *vf, u8 *msg)
3746 {
3747 struct virtchnl_filter *vcf = (struct virtchnl_filter *)msg;
3748 struct virtchnl_l4_spec mask = vcf->mask.tcp_spec;
3749 struct virtchnl_l4_spec tcf = vcf->data.tcp_spec;
3750 struct i40e_cloud_filter *cfilter = NULL;
3751 struct i40e_pf *pf = vf->pf;
3752 struct i40e_vsi *vsi = NULL;
3753 i40e_status aq_ret = 0;
3754 int i, ret;
3755
3756 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3757 aq_ret = I40E_ERR_PARAM;
3758 goto err_out;
3759 }
3760
3761 if (!vf->adq_enabled) {
3762 dev_info(&pf->pdev->dev,
3763 "VF %d: ADq is not enabled, can't apply cloud filter\n",
3764 vf->vf_id);
3765 aq_ret = I40E_ERR_PARAM;
3766 goto err_out;
3767 }
3768
3769 if (i40e_validate_cloud_filter(vf, vcf)) {
3770 dev_info(&pf->pdev->dev,
3771 "VF %d: Invalid input/s, can't apply cloud filter\n",
3772 vf->vf_id);
3773 aq_ret = I40E_ERR_PARAM;
3774 goto err_out;
3775 }
3776
3777 cfilter = kzalloc(sizeof(*cfilter), GFP_KERNEL);
3778 if (!cfilter)
3779 return -ENOMEM;
3780
3781
3782 for (i = 0; i < ETH_ALEN; i++)
3783 cfilter->dst_mac[i] = mask.dst_mac[i] & tcf.dst_mac[i];
3784
3785
3786 for (i = 0; i < ETH_ALEN; i++)
3787 cfilter->src_mac[i] = mask.src_mac[i] & tcf.src_mac[i];
3788
3789 cfilter->vlan_id = mask.vlan_id & tcf.vlan_id;
3790 cfilter->dst_port = mask.dst_port & tcf.dst_port;
3791 cfilter->src_port = mask.src_port & tcf.src_port;
3792
3793 switch (vcf->flow_type) {
3794 case VIRTCHNL_TCP_V4_FLOW:
3795 cfilter->n_proto = ETH_P_IP;
3796 if (mask.dst_ip[0] & tcf.dst_ip[0])
3797 memcpy(&cfilter->ip.v4.dst_ip, tcf.dst_ip,
3798 ARRAY_SIZE(tcf.dst_ip));
3799 else if (mask.src_ip[0] & tcf.dst_ip[0])
3800 memcpy(&cfilter->ip.v4.src_ip, tcf.src_ip,
3801 ARRAY_SIZE(tcf.dst_ip));
3802 break;
3803 case VIRTCHNL_TCP_V6_FLOW:
3804 cfilter->n_proto = ETH_P_IPV6;
3805 if (mask.dst_ip[3] & tcf.dst_ip[3])
3806 memcpy(&cfilter->ip.v6.dst_ip6, tcf.dst_ip,
3807 sizeof(cfilter->ip.v6.dst_ip6));
3808 if (mask.src_ip[3] & tcf.src_ip[3])
3809 memcpy(&cfilter->ip.v6.src_ip6, tcf.src_ip,
3810 sizeof(cfilter->ip.v6.src_ip6));
3811 break;
3812 default:
3813
3814
3815
3816 dev_info(&pf->pdev->dev, "VF %d: Flow type not configured\n",
3817 vf->vf_id);
3818 }
3819
3820
3821 vsi = pf->vsi[vf->ch[vcf->action_meta].vsi_idx];
3822 cfilter->seid = vsi->seid;
3823 cfilter->flags = vcf->field_flags;
3824
3825
3826 if (tcf.dst_port)
3827 ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter, true);
3828 else
3829 ret = i40e_add_del_cloud_filter(vsi, cfilter, true);
3830 if (ret) {
3831 dev_err(&pf->pdev->dev,
3832 "VF %d: Failed to add cloud filter, err %s aq_err %s\n",
3833 vf->vf_id, i40e_stat_str(&pf->hw, ret),
3834 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
3835 goto err_free;
3836 }
3837
3838 INIT_HLIST_NODE(&cfilter->cloud_node);
3839 hlist_add_head(&cfilter->cloud_node, &vf->cloud_filter_list);
3840
3841 cfilter = NULL;
3842 vf->num_cloud_filters++;
3843 err_free:
3844 kfree(cfilter);
3845 err_out:
3846 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_ADD_CLOUD_FILTER,
3847 aq_ret);
3848 }
3849
3850
3851
3852
3853
3854
3855 static int i40e_vc_add_qch_msg(struct i40e_vf *vf, u8 *msg)
3856 {
3857 struct virtchnl_tc_info *tci =
3858 (struct virtchnl_tc_info *)msg;
3859 struct i40e_pf *pf = vf->pf;
3860 struct i40e_link_status *ls = &pf->hw.phy.link_info;
3861 int i, adq_request_qps = 0;
3862 i40e_status aq_ret = 0;
3863 u64 speed = 0;
3864
3865 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3866 aq_ret = I40E_ERR_PARAM;
3867 goto err;
3868 }
3869
3870
3871 if (vf->spoofchk) {
3872 dev_err(&pf->pdev->dev,
3873 "Spoof check is ON, turn it OFF to enable ADq\n");
3874 aq_ret = I40E_ERR_PARAM;
3875 goto err;
3876 }
3877
3878 if (!(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ADQ)) {
3879 dev_err(&pf->pdev->dev,
3880 "VF %d attempting to enable ADq, but hasn't properly negotiated that capability\n",
3881 vf->vf_id);
3882 aq_ret = I40E_ERR_PARAM;
3883 goto err;
3884 }
3885
3886
3887 if (!tci->num_tc || tci->num_tc > I40E_MAX_VF_VSI) {
3888 dev_err(&pf->pdev->dev,
3889 "VF %d trying to set %u TCs, valid range 1-%u TCs per VF\n",
3890 vf->vf_id, tci->num_tc, I40E_MAX_VF_VSI);
3891 aq_ret = I40E_ERR_PARAM;
3892 goto err;
3893 }
3894
3895
3896 for (i = 0; i < tci->num_tc; i++)
3897 if (!tci->list[i].count ||
3898 tci->list[i].count > I40E_DEFAULT_QUEUES_PER_VF) {
3899 dev_err(&pf->pdev->dev,
3900 "VF %d: TC %d trying to set %u queues, valid range 1-%u queues per TC\n",
3901 vf->vf_id, i, tci->list[i].count,
3902 I40E_DEFAULT_QUEUES_PER_VF);
3903 aq_ret = I40E_ERR_PARAM;
3904 goto err;
3905 }
3906
3907
3908 adq_request_qps = I40E_MAX_VF_QUEUES - I40E_DEFAULT_QUEUES_PER_VF;
3909
3910 if (pf->queues_left < adq_request_qps) {
3911 dev_err(&pf->pdev->dev,
3912 "No queues left to allocate to VF %d\n",
3913 vf->vf_id);
3914 aq_ret = I40E_ERR_PARAM;
3915 goto err;
3916 } else {
3917
3918
3919
3920
3921 vf->num_queue_pairs = I40E_MAX_VF_QUEUES;
3922 }
3923
3924
3925 speed = i40e_vc_link_speed2mbps(ls->link_speed);
3926 if (speed == SPEED_UNKNOWN) {
3927 dev_err(&pf->pdev->dev,
3928 "Cannot detect link speed\n");
3929 aq_ret = I40E_ERR_PARAM;
3930 goto err;
3931 }
3932
3933
3934 vf->num_tc = tci->num_tc;
3935 for (i = 0; i < vf->num_tc; i++) {
3936 if (tci->list[i].max_tx_rate) {
3937 if (tci->list[i].max_tx_rate > speed) {
3938 dev_err(&pf->pdev->dev,
3939 "Invalid max tx rate %llu specified for VF %d.",
3940 tci->list[i].max_tx_rate,
3941 vf->vf_id);
3942 aq_ret = I40E_ERR_PARAM;
3943 goto err;
3944 } else {
3945 vf->ch[i].max_tx_rate =
3946 tci->list[i].max_tx_rate;
3947 }
3948 }
3949 vf->ch[i].num_qps = tci->list[i].count;
3950 }
3951
3952
3953 vf->adq_enabled = true;
3954
3955
3956 i40e_vc_reset_vf(vf, true);
3957
3958 return I40E_SUCCESS;
3959
3960
3961 err:
3962 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_ENABLE_CHANNELS,
3963 aq_ret);
3964 }
3965
3966
3967
3968
3969
3970
3971 static int i40e_vc_del_qch_msg(struct i40e_vf *vf, u8 *msg)
3972 {
3973 struct i40e_pf *pf = vf->pf;
3974 i40e_status aq_ret = 0;
3975
3976 if (!i40e_sync_vf_state(vf, I40E_VF_STATE_ACTIVE)) {
3977 aq_ret = I40E_ERR_PARAM;
3978 goto err;
3979 }
3980
3981 if (vf->adq_enabled) {
3982 i40e_del_all_cloud_filters(vf);
3983 i40e_del_qch(vf);
3984 vf->adq_enabled = false;
3985 vf->num_tc = 0;
3986 dev_info(&pf->pdev->dev,
3987 "Deleting Queue Channels and cloud filters for ADq on VF %d\n",
3988 vf->vf_id);
3989 } else {
3990 dev_info(&pf->pdev->dev, "VF %d trying to delete queue channels but ADq isn't enabled\n",
3991 vf->vf_id);
3992 aq_ret = I40E_ERR_PARAM;
3993 }
3994
3995
3996 i40e_vc_reset_vf(vf, true);
3997
3998 return I40E_SUCCESS;
3999
4000 err:
4001 return i40e_vc_send_resp_to_vf(vf, VIRTCHNL_OP_DISABLE_CHANNELS,
4002 aq_ret);
4003 }
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017 int i40e_vc_process_vf_msg(struct i40e_pf *pf, s16 vf_id, u32 v_opcode,
4018 u32 __always_unused v_retval, u8 *msg, u16 msglen)
4019 {
4020 struct i40e_hw *hw = &pf->hw;
4021 int local_vf_id = vf_id - (s16)hw->func_caps.vf_base_id;
4022 struct i40e_vf *vf;
4023 int ret;
4024
4025 pf->vf_aq_requests++;
4026 if (local_vf_id < 0 || local_vf_id >= pf->num_alloc_vfs)
4027 return -EINVAL;
4028 vf = &(pf->vf[local_vf_id]);
4029
4030
4031 if (test_bit(I40E_VF_STATE_DISABLED, &vf->vf_states))
4032 return I40E_ERR_PARAM;
4033
4034
4035 ret = virtchnl_vc_validate_vf_msg(&vf->vf_ver, v_opcode, msg, msglen);
4036
4037 if (ret) {
4038 i40e_vc_send_resp_to_vf(vf, v_opcode, I40E_ERR_PARAM);
4039 dev_err(&pf->pdev->dev, "Invalid message from VF %d, opcode %d, len %d\n",
4040 local_vf_id, v_opcode, msglen);
4041 switch (ret) {
4042 case VIRTCHNL_STATUS_ERR_PARAM:
4043 return -EPERM;
4044 default:
4045 return -EINVAL;
4046 }
4047 }
4048
4049 switch (v_opcode) {
4050 case VIRTCHNL_OP_VERSION:
4051 ret = i40e_vc_get_version_msg(vf, msg);
4052 break;
4053 case VIRTCHNL_OP_GET_VF_RESOURCES:
4054 ret = i40e_vc_get_vf_resources_msg(vf, msg);
4055 i40e_vc_notify_vf_link_state(vf);
4056 break;
4057 case VIRTCHNL_OP_RESET_VF:
4058 i40e_vc_reset_vf(vf, false);
4059 ret = 0;
4060 break;
4061 case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
4062 ret = i40e_vc_config_promiscuous_mode_msg(vf, msg);
4063 break;
4064 case VIRTCHNL_OP_CONFIG_VSI_QUEUES:
4065 ret = i40e_vc_config_queues_msg(vf, msg);
4066 break;
4067 case VIRTCHNL_OP_CONFIG_IRQ_MAP:
4068 ret = i40e_vc_config_irq_map_msg(vf, msg);
4069 break;
4070 case VIRTCHNL_OP_ENABLE_QUEUES:
4071 ret = i40e_vc_enable_queues_msg(vf, msg);
4072 i40e_vc_notify_vf_link_state(vf);
4073 break;
4074 case VIRTCHNL_OP_DISABLE_QUEUES:
4075 ret = i40e_vc_disable_queues_msg(vf, msg);
4076 break;
4077 case VIRTCHNL_OP_ADD_ETH_ADDR:
4078 ret = i40e_vc_add_mac_addr_msg(vf, msg);
4079 break;
4080 case VIRTCHNL_OP_DEL_ETH_ADDR:
4081 ret = i40e_vc_del_mac_addr_msg(vf, msg);
4082 break;
4083 case VIRTCHNL_OP_ADD_VLAN:
4084 ret = i40e_vc_add_vlan_msg(vf, msg);
4085 break;
4086 case VIRTCHNL_OP_DEL_VLAN:
4087 ret = i40e_vc_remove_vlan_msg(vf, msg);
4088 break;
4089 case VIRTCHNL_OP_GET_STATS:
4090 ret = i40e_vc_get_stats_msg(vf, msg);
4091 break;
4092 case VIRTCHNL_OP_IWARP:
4093 ret = i40e_vc_iwarp_msg(vf, msg, msglen);
4094 break;
4095 case VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP:
4096 ret = i40e_vc_iwarp_qvmap_msg(vf, msg, true);
4097 break;
4098 case VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP:
4099 ret = i40e_vc_iwarp_qvmap_msg(vf, msg, false);
4100 break;
4101 case VIRTCHNL_OP_CONFIG_RSS_KEY:
4102 ret = i40e_vc_config_rss_key(vf, msg);
4103 break;
4104 case VIRTCHNL_OP_CONFIG_RSS_LUT:
4105 ret = i40e_vc_config_rss_lut(vf, msg);
4106 break;
4107 case VIRTCHNL_OP_GET_RSS_HENA_CAPS:
4108 ret = i40e_vc_get_rss_hena(vf, msg);
4109 break;
4110 case VIRTCHNL_OP_SET_RSS_HENA:
4111 ret = i40e_vc_set_rss_hena(vf, msg);
4112 break;
4113 case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING:
4114 ret = i40e_vc_enable_vlan_stripping(vf, msg);
4115 break;
4116 case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING:
4117 ret = i40e_vc_disable_vlan_stripping(vf, msg);
4118 break;
4119 case VIRTCHNL_OP_REQUEST_QUEUES:
4120 ret = i40e_vc_request_queues_msg(vf, msg);
4121 break;
4122 case VIRTCHNL_OP_ENABLE_CHANNELS:
4123 ret = i40e_vc_add_qch_msg(vf, msg);
4124 break;
4125 case VIRTCHNL_OP_DISABLE_CHANNELS:
4126 ret = i40e_vc_del_qch_msg(vf, msg);
4127 break;
4128 case VIRTCHNL_OP_ADD_CLOUD_FILTER:
4129 ret = i40e_vc_add_cloud_filter(vf, msg);
4130 break;
4131 case VIRTCHNL_OP_DEL_CLOUD_FILTER:
4132 ret = i40e_vc_del_cloud_filter(vf, msg);
4133 break;
4134 case VIRTCHNL_OP_UNKNOWN:
4135 default:
4136 dev_err(&pf->pdev->dev, "Unsupported opcode %d from VF %d\n",
4137 v_opcode, local_vf_id);
4138 ret = i40e_vc_send_resp_to_vf(vf, v_opcode,
4139 I40E_ERR_NOT_IMPLEMENTED);
4140 break;
4141 }
4142
4143 return ret;
4144 }
4145
4146
4147
4148
4149
4150
4151
4152
4153 int i40e_vc_process_vflr_event(struct i40e_pf *pf)
4154 {
4155 struct i40e_hw *hw = &pf->hw;
4156 u32 reg, reg_idx, bit_idx;
4157 struct i40e_vf *vf;
4158 int vf_id;
4159
4160 if (!test_bit(__I40E_VFLR_EVENT_PENDING, pf->state))
4161 return 0;
4162
4163
4164
4165
4166
4167
4168 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
4169 reg |= I40E_PFINT_ICR0_ENA_VFLR_MASK;
4170 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
4171 i40e_flush(hw);
4172
4173 clear_bit(__I40E_VFLR_EVENT_PENDING, pf->state);
4174 for (vf_id = 0; vf_id < pf->num_alloc_vfs; vf_id++) {
4175 reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
4176 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
4177
4178 vf = &pf->vf[vf_id];
4179 reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx));
4180 if (reg & BIT(bit_idx))
4181
4182 i40e_reset_vf(vf, true);
4183 }
4184
4185 return 0;
4186 }
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197 static int i40e_validate_vf(struct i40e_pf *pf, int vf_id)
4198 {
4199 struct i40e_vsi *vsi;
4200 struct i40e_vf *vf;
4201 int ret = 0;
4202
4203 if (vf_id >= pf->num_alloc_vfs) {
4204 dev_err(&pf->pdev->dev,
4205 "Invalid VF Identifier %d\n", vf_id);
4206 ret = -EINVAL;
4207 goto err_out;
4208 }
4209 vf = &pf->vf[vf_id];
4210 vsi = i40e_find_vsi_from_id(pf, vf->lan_vsi_id);
4211 if (!vsi)
4212 ret = -EINVAL;
4213 err_out:
4214 return ret;
4215 }
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225 int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
4226 {
4227 struct i40e_netdev_priv *np = netdev_priv(netdev);
4228 struct i40e_vsi *vsi = np->vsi;
4229 struct i40e_pf *pf = vsi->back;
4230 struct i40e_mac_filter *f;
4231 struct i40e_vf *vf;
4232 int ret = 0;
4233 struct hlist_node *h;
4234 int bkt;
4235 u8 i;
4236
4237 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4238 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4239 return -EAGAIN;
4240 }
4241
4242
4243 ret = i40e_validate_vf(pf, vf_id);
4244 if (ret)
4245 goto error_param;
4246
4247 vf = &pf->vf[vf_id];
4248
4249
4250
4251
4252
4253
4254
4255 for (i = 0; i < 15; i++) {
4256 if (test_bit(I40E_VF_STATE_INIT, &vf->vf_states))
4257 break;
4258 msleep(20);
4259 }
4260 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
4261 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
4262 vf_id);
4263 ret = -EAGAIN;
4264 goto error_param;
4265 }
4266 vsi = pf->vsi[vf->lan_vsi_idx];
4267
4268 if (is_multicast_ether_addr(mac)) {
4269 dev_err(&pf->pdev->dev,
4270 "Invalid Ethernet address %pM for VF %d\n", mac, vf_id);
4271 ret = -EINVAL;
4272 goto error_param;
4273 }
4274
4275
4276
4277
4278 spin_lock_bh(&vsi->mac_filter_hash_lock);
4279
4280
4281 if (!is_zero_ether_addr(vf->default_lan_addr.addr))
4282 i40e_del_mac_filter(vsi, vf->default_lan_addr.addr);
4283
4284
4285
4286
4287 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist)
4288 __i40e_del_filter(vsi, f);
4289
4290 spin_unlock_bh(&vsi->mac_filter_hash_lock);
4291
4292
4293 if (i40e_sync_vsi_filters(vsi)) {
4294 dev_err(&pf->pdev->dev, "Unable to program ucast filters\n");
4295 ret = -EIO;
4296 goto error_param;
4297 }
4298 ether_addr_copy(vf->default_lan_addr.addr, mac);
4299
4300 if (is_zero_ether_addr(mac)) {
4301 vf->pf_set_mac = false;
4302 dev_info(&pf->pdev->dev, "Removing MAC on VF %d\n", vf_id);
4303 } else {
4304 vf->pf_set_mac = true;
4305 dev_info(&pf->pdev->dev, "Setting MAC %pM on VF %d\n",
4306 mac, vf_id);
4307 }
4308
4309
4310
4311
4312 i40e_vc_reset_vf(vf, true);
4313 dev_info(&pf->pdev->dev, "Bring down and up the VF interface to make this change effective.\n");
4314
4315 error_param:
4316 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4317 return ret;
4318 }
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330 int i40e_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,
4331 u16 vlan_id, u8 qos, __be16 vlan_proto)
4332 {
4333 u16 vlanprio = vlan_id | (qos << I40E_VLAN_PRIORITY_SHIFT);
4334 struct i40e_netdev_priv *np = netdev_priv(netdev);
4335 bool allmulti = false, alluni = false;
4336 struct i40e_pf *pf = np->vsi->back;
4337 struct i40e_vsi *vsi;
4338 struct i40e_vf *vf;
4339 int ret = 0;
4340
4341 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4342 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4343 return -EAGAIN;
4344 }
4345
4346
4347 ret = i40e_validate_vf(pf, vf_id);
4348 if (ret)
4349 goto error_pvid;
4350
4351 if ((vlan_id > I40E_MAX_VLANID) || (qos > 7)) {
4352 dev_err(&pf->pdev->dev, "Invalid VF Parameters\n");
4353 ret = -EINVAL;
4354 goto error_pvid;
4355 }
4356
4357 if (vlan_proto != htons(ETH_P_8021Q)) {
4358 dev_err(&pf->pdev->dev, "VF VLAN protocol is not supported\n");
4359 ret = -EPROTONOSUPPORT;
4360 goto error_pvid;
4361 }
4362
4363 vf = &pf->vf[vf_id];
4364 vsi = pf->vsi[vf->lan_vsi_idx];
4365 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
4366 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
4367 vf_id);
4368 ret = -EAGAIN;
4369 goto error_pvid;
4370 }
4371
4372 if (le16_to_cpu(vsi->info.pvid) == vlanprio)
4373
4374 goto error_pvid;
4375
4376 i40e_vlan_stripping_enable(vsi);
4377 i40e_vc_reset_vf(vf, true);
4378
4379 vsi = pf->vsi[vf->lan_vsi_idx];
4380
4381 spin_lock_bh(&vsi->mac_filter_hash_lock);
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391 if ((!(vlan_id || qos) ||
4392 vlanprio != le16_to_cpu(vsi->info.pvid)) &&
4393 vsi->info.pvid) {
4394 ret = i40e_add_vlan_all_mac(vsi, I40E_VLAN_ANY);
4395 if (ret) {
4396 dev_info(&vsi->back->pdev->dev,
4397 "add VF VLAN failed, ret=%d aq_err=%d\n", ret,
4398 vsi->back->hw.aq.asq_last_status);
4399 spin_unlock_bh(&vsi->mac_filter_hash_lock);
4400 goto error_pvid;
4401 }
4402 }
4403
4404 if (vsi->info.pvid) {
4405
4406 i40e_rm_vlan_all_mac(vsi, (le16_to_cpu(vsi->info.pvid) &
4407 VLAN_VID_MASK));
4408 }
4409
4410 spin_unlock_bh(&vsi->mac_filter_hash_lock);
4411
4412
4413 ret = i40e_config_vf_promiscuous_mode(vf, vf->lan_vsi_id,
4414 allmulti, alluni);
4415 if (ret) {
4416 dev_err(&pf->pdev->dev, "Unable to config VF promiscuous mode\n");
4417 goto error_pvid;
4418 }
4419
4420 if (vlan_id || qos)
4421 ret = i40e_vsi_add_pvid(vsi, vlanprio);
4422 else
4423 i40e_vsi_remove_pvid(vsi);
4424 spin_lock_bh(&vsi->mac_filter_hash_lock);
4425
4426 if (vlan_id) {
4427 dev_info(&pf->pdev->dev, "Setting VLAN %d, QOS 0x%x on VF %d\n",
4428 vlan_id, qos, vf_id);
4429
4430
4431 ret = i40e_add_vlan_all_mac(vsi, vlan_id);
4432 if (ret) {
4433 dev_info(&vsi->back->pdev->dev,
4434 "add VF VLAN failed, ret=%d aq_err=%d\n", ret,
4435 vsi->back->hw.aq.asq_last_status);
4436 spin_unlock_bh(&vsi->mac_filter_hash_lock);
4437 goto error_pvid;
4438 }
4439
4440
4441 i40e_rm_vlan_all_mac(vsi, I40E_VLAN_ANY);
4442 }
4443
4444 spin_unlock_bh(&vsi->mac_filter_hash_lock);
4445
4446 if (test_bit(I40E_VF_STATE_UC_PROMISC, &vf->vf_states))
4447 alluni = true;
4448
4449 if (test_bit(I40E_VF_STATE_MC_PROMISC, &vf->vf_states))
4450 allmulti = true;
4451
4452
4453 i40e_service_event_schedule(vsi->back);
4454
4455 if (ret) {
4456 dev_err(&pf->pdev->dev, "Unable to update VF vsi context\n");
4457 goto error_pvid;
4458 }
4459
4460
4461
4462
4463 vf->port_vlan_id = le16_to_cpu(vsi->info.pvid);
4464
4465 ret = i40e_config_vf_promiscuous_mode(vf, vsi->id, allmulti, alluni);
4466 if (ret) {
4467 dev_err(&pf->pdev->dev, "Unable to config vf promiscuous mode\n");
4468 goto error_pvid;
4469 }
4470
4471 ret = 0;
4472
4473 error_pvid:
4474 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4475 return ret;
4476 }
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487 int i40e_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate,
4488 int max_tx_rate)
4489 {
4490 struct i40e_netdev_priv *np = netdev_priv(netdev);
4491 struct i40e_pf *pf = np->vsi->back;
4492 struct i40e_vsi *vsi;
4493 struct i40e_vf *vf;
4494 int ret = 0;
4495
4496 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4497 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4498 return -EAGAIN;
4499 }
4500
4501
4502 ret = i40e_validate_vf(pf, vf_id);
4503 if (ret)
4504 goto error;
4505
4506 if (min_tx_rate) {
4507 dev_err(&pf->pdev->dev, "Invalid min tx rate (%d) (greater than 0) specified for VF %d.\n",
4508 min_tx_rate, vf_id);
4509 ret = -EINVAL;
4510 goto error;
4511 }
4512
4513 vf = &pf->vf[vf_id];
4514 vsi = pf->vsi[vf->lan_vsi_idx];
4515 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
4516 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
4517 vf_id);
4518 ret = -EAGAIN;
4519 goto error;
4520 }
4521
4522 ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate);
4523 if (ret)
4524 goto error;
4525
4526 vf->tx_rate = max_tx_rate;
4527 error:
4528 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4529 return ret;
4530 }
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540 int i40e_ndo_get_vf_config(struct net_device *netdev,
4541 int vf_id, struct ifla_vf_info *ivi)
4542 {
4543 struct i40e_netdev_priv *np = netdev_priv(netdev);
4544 struct i40e_vsi *vsi = np->vsi;
4545 struct i40e_pf *pf = vsi->back;
4546 struct i40e_vf *vf;
4547 int ret = 0;
4548
4549 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4550 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4551 return -EAGAIN;
4552 }
4553
4554
4555 ret = i40e_validate_vf(pf, vf_id);
4556 if (ret)
4557 goto error_param;
4558
4559 vf = &pf->vf[vf_id];
4560
4561 vsi = pf->vsi[vf->lan_vsi_idx];
4562 if (!vsi) {
4563 ret = -ENOENT;
4564 goto error_param;
4565 }
4566
4567 ivi->vf = vf_id;
4568
4569 ether_addr_copy(ivi->mac, vf->default_lan_addr.addr);
4570
4571 ivi->max_tx_rate = vf->tx_rate;
4572 ivi->min_tx_rate = 0;
4573 ivi->vlan = le16_to_cpu(vsi->info.pvid) & I40E_VLAN_MASK;
4574 ivi->qos = (le16_to_cpu(vsi->info.pvid) & I40E_PRIORITY_MASK) >>
4575 I40E_VLAN_PRIORITY_SHIFT;
4576 if (vf->link_forced == false)
4577 ivi->linkstate = IFLA_VF_LINK_STATE_AUTO;
4578 else if (vf->link_up == true)
4579 ivi->linkstate = IFLA_VF_LINK_STATE_ENABLE;
4580 else
4581 ivi->linkstate = IFLA_VF_LINK_STATE_DISABLE;
4582 ivi->spoofchk = vf->spoofchk;
4583 ivi->trusted = vf->trusted;
4584 ret = 0;
4585
4586 error_param:
4587 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4588 return ret;
4589 }
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599 int i40e_ndo_set_vf_link_state(struct net_device *netdev, int vf_id, int link)
4600 {
4601 struct i40e_netdev_priv *np = netdev_priv(netdev);
4602 struct i40e_pf *pf = np->vsi->back;
4603 struct i40e_link_status *ls = &pf->hw.phy.link_info;
4604 struct virtchnl_pf_event pfe;
4605 struct i40e_hw *hw = &pf->hw;
4606 struct i40e_vf *vf;
4607 int abs_vf_id;
4608 int ret = 0;
4609
4610 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4611 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4612 return -EAGAIN;
4613 }
4614
4615
4616 if (vf_id >= pf->num_alloc_vfs) {
4617 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
4618 ret = -EINVAL;
4619 goto error_out;
4620 }
4621
4622 vf = &pf->vf[vf_id];
4623 abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
4624
4625 pfe.event = VIRTCHNL_EVENT_LINK_CHANGE;
4626 pfe.severity = PF_EVENT_SEVERITY_INFO;
4627
4628 switch (link) {
4629 case IFLA_VF_LINK_STATE_AUTO:
4630 vf->link_forced = false;
4631 i40e_set_vf_link_state(vf, &pfe, ls);
4632 break;
4633 case IFLA_VF_LINK_STATE_ENABLE:
4634 vf->link_forced = true;
4635 vf->link_up = true;
4636 i40e_set_vf_link_state(vf, &pfe, ls);
4637 break;
4638 case IFLA_VF_LINK_STATE_DISABLE:
4639 vf->link_forced = true;
4640 vf->link_up = false;
4641 i40e_set_vf_link_state(vf, &pfe, ls);
4642 break;
4643 default:
4644 ret = -EINVAL;
4645 goto error_out;
4646 }
4647
4648 i40e_aq_send_msg_to_vf(hw, abs_vf_id, VIRTCHNL_OP_EVENT,
4649 0, (u8 *)&pfe, sizeof(pfe), NULL);
4650
4651 error_out:
4652 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4653 return ret;
4654 }
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664 int i40e_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_id, bool enable)
4665 {
4666 struct i40e_netdev_priv *np = netdev_priv(netdev);
4667 struct i40e_vsi *vsi = np->vsi;
4668 struct i40e_pf *pf = vsi->back;
4669 struct i40e_vsi_context ctxt;
4670 struct i40e_hw *hw = &pf->hw;
4671 struct i40e_vf *vf;
4672 int ret = 0;
4673
4674 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4675 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4676 return -EAGAIN;
4677 }
4678
4679
4680 if (vf_id >= pf->num_alloc_vfs) {
4681 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
4682 ret = -EINVAL;
4683 goto out;
4684 }
4685
4686 vf = &(pf->vf[vf_id]);
4687 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
4688 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
4689 vf_id);
4690 ret = -EAGAIN;
4691 goto out;
4692 }
4693
4694 if (enable == vf->spoofchk)
4695 goto out;
4696
4697 vf->spoofchk = enable;
4698 memset(&ctxt, 0, sizeof(ctxt));
4699 ctxt.seid = pf->vsi[vf->lan_vsi_idx]->seid;
4700 ctxt.pf_num = pf->hw.pf_id;
4701 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
4702 if (enable)
4703 ctxt.info.sec_flags |= (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
4704 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
4705 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4706 if (ret) {
4707 dev_err(&pf->pdev->dev, "Error %d updating VSI parameters\n",
4708 ret);
4709 ret = -EIO;
4710 }
4711 out:
4712 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4713 return ret;
4714 }
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724 int i40e_ndo_set_vf_trust(struct net_device *netdev, int vf_id, bool setting)
4725 {
4726 struct i40e_netdev_priv *np = netdev_priv(netdev);
4727 struct i40e_pf *pf = np->vsi->back;
4728 struct i40e_vf *vf;
4729 int ret = 0;
4730
4731 if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
4732 dev_warn(&pf->pdev->dev, "Unable to configure VFs, other operation is pending.\n");
4733 return -EAGAIN;
4734 }
4735
4736
4737 if (vf_id >= pf->num_alloc_vfs) {
4738 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
4739 ret = -EINVAL;
4740 goto out;
4741 }
4742
4743 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4744 dev_err(&pf->pdev->dev, "Trusted VF not supported in MFP mode.\n");
4745 ret = -EINVAL;
4746 goto out;
4747 }
4748
4749 vf = &pf->vf[vf_id];
4750
4751 if (setting == vf->trusted)
4752 goto out;
4753
4754 vf->trusted = setting;
4755
4756
4757 set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state);
4758 pf->vsi[vf->lan_vsi_idx]->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
4759
4760 i40e_vc_reset_vf(vf, true);
4761 dev_info(&pf->pdev->dev, "VF %u is now %strusted\n",
4762 vf_id, setting ? "" : "un");
4763
4764 if (vf->adq_enabled) {
4765 if (!vf->trusted) {
4766 dev_info(&pf->pdev->dev,
4767 "VF %u no longer Trusted, deleting all cloud filters\n",
4768 vf_id);
4769 i40e_del_all_cloud_filters(vf);
4770 }
4771 }
4772
4773 out:
4774 clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state);
4775 return ret;
4776 }
4777
4778
4779
4780
4781
4782
4783
4784 int i40e_get_vf_stats(struct net_device *netdev, int vf_id,
4785 struct ifla_vf_stats *vf_stats)
4786 {
4787 struct i40e_netdev_priv *np = netdev_priv(netdev);
4788 struct i40e_pf *pf = np->vsi->back;
4789 struct i40e_eth_stats *stats;
4790 struct i40e_vsi *vsi;
4791 struct i40e_vf *vf;
4792
4793
4794 if (i40e_validate_vf(pf, vf_id))
4795 return -EINVAL;
4796
4797 vf = &pf->vf[vf_id];
4798 if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states)) {
4799 dev_err(&pf->pdev->dev, "VF %d in reset. Try again.\n", vf_id);
4800 return -EBUSY;
4801 }
4802
4803 vsi = pf->vsi[vf->lan_vsi_idx];
4804 if (!vsi)
4805 return -EINVAL;
4806
4807 i40e_update_eth_stats(vsi);
4808 stats = &vsi->eth_stats;
4809
4810 memset(vf_stats, 0, sizeof(*vf_stats));
4811
4812 vf_stats->rx_packets = stats->rx_unicast + stats->rx_broadcast +
4813 stats->rx_multicast;
4814 vf_stats->tx_packets = stats->tx_unicast + stats->tx_broadcast +
4815 stats->tx_multicast;
4816 vf_stats->rx_bytes = stats->rx_bytes;
4817 vf_stats->tx_bytes = stats->tx_bytes;
4818 vf_stats->broadcast = stats->rx_broadcast;
4819 vf_stats->multicast = stats->rx_multicast;
4820 vf_stats->rx_dropped = stats->rx_discards;
4821 vf_stats->tx_dropped = stats->tx_discards;
4822
4823 return 0;
4824 }