intel/i40e/i40e_txrx_common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2018 Intel Corporation. */
0003
0004 #ifndef I40E_TXRX_COMMON_
0005 #define I40E_TXRX_COMMON_
0006
0007 int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring);
0008 void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
0009                    u64 qword1);
0010 void i40e_process_skb_fields(struct i40e_ring *rx_ring,
0011                  union i40e_rx_desc *rx_desc, struct sk_buff *skb);
0012 void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring);
0013 void i40e_update_rx_stats(struct i40e_ring *rx_ring,
0014               unsigned int total_rx_bytes,
0015               unsigned int total_rx_packets);
0016 void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res);
0017 void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val);
0018
0019 #define I40E_XDP_PASS       0
0020 #define I40E_XDP_CONSUMED   BIT(0)
0021 #define I40E_XDP_TX     BIT(1)
0022 #define I40E_XDP_REDIR      BIT(2)
0023 #define I40E_XDP_EXIT       BIT(3)
0024
0025 /*
0026  * build_ctob - Builds the Tx descriptor (cmd, offset and type) qword
0027  */
0028 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
0029                 u32 td_tag)
0030 {
0031     return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
0032                ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
0033                ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
0034                ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
0035                ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
0036 }
0037
0038 /**
0039  * i40e_update_tx_stats - Update the egress statistics for the Tx ring
0040  * @tx_ring: Tx ring to update
0041  * @total_packets: total packets sent
0042  * @total_bytes: total bytes sent
0043  **/
0044 static inline void i40e_update_tx_stats(struct i40e_ring *tx_ring,
0045                     unsigned int total_packets,
0046                     unsigned int total_bytes)
0047 {
0048     u64_stats_update_begin(&tx_ring->syncp);
0049     tx_ring->stats.bytes += total_bytes;
0050     tx_ring->stats.packets += total_packets;
0051     u64_stats_update_end(&tx_ring->syncp);
0052     tx_ring->q_vector->tx.total_bytes += total_bytes;
0053     tx_ring->q_vector->tx.total_packets += total_packets;
0054 }
0055
0056 #define WB_STRIDE 4
0057
0058 /**
0059  * i40e_arm_wb - (Possibly) arms Tx write-back
0060  * @tx_ring: Tx ring to update
0061  * @vsi: the VSI
0062  * @budget: the NAPI budget left
0063  **/
0064 static inline void i40e_arm_wb(struct i40e_ring *tx_ring,
0065                    struct i40e_vsi *vsi,
0066                    int budget)
0067 {
0068     if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
0069         /* check to see if there are < 4 descriptors
0070          * waiting to be written back, then kick the hardware to force
0071          * them to be written back in case we stay in NAPI.
0072          * In this mode on X722 we do not enable Interrupt.
0073          */
0074         unsigned int j = i40e_get_tx_pending(tx_ring, false);
0075
0076         if (budget &&
0077             ((j / WB_STRIDE) == 0) && j > 0 &&
0078             !test_bit(__I40E_VSI_DOWN, vsi->state) &&
0079             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
0080             tx_ring->arm_wb = true;
0081     }
0082 }
0083
0084 /**
0085  * i40e_rx_is_programming_status - check for programming status descriptor
0086  * @qword1: qword1 representing status_error_len in CPU ordering
0087  *
0088  * The value of in the descriptor length field indicate if this
0089  * is a programming status descriptor for flow director or FCoE
0090  * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
0091  * it is a packet descriptor.
0092  **/
0093 static inline bool i40e_rx_is_programming_status(u64 qword1)
0094 {
0095     /* The Rx filter programming status and SPH bit occupy the same
0096      * spot in the descriptor. Since we don't support packet split we
0097      * can just reuse the bit as an indication that this is a
0098      * programming status descriptor.
0099      */
0100     return qword1 & I40E_RXD_QW1_LENGTH_SPH_MASK;
0101 }
0102
0103 void i40e_xsk_clean_rx_ring(struct i40e_ring *rx_ring);
0104 void i40e_xsk_clean_tx_ring(struct i40e_ring *tx_ring);
0105 bool i40e_xsk_any_rx_ring_enabled(struct i40e_vsi *vsi);
0106
0107 #endif /* I40E_TXRX_COMMON_ */