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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2013 - 2021 Intel Corporation. */
0003 
0004 #ifndef _I40E_REGISTER_H_
0005 #define _I40E_REGISTER_H_
0006 
0007 #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30
0008 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
0009 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
0010 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
0011 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
0012 #define I40E_PF_ARQH_ARQH_SHIFT 0
0013 #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
0014 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
0015 #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28
0016 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
0017 #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29
0018 #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
0019 #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
0020 #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
0021 #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
0022 #define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
0023 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
0024 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
0025 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
0026 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
0027 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
0028 #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28
0029 #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
0030 #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29
0031 #define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
0032 #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
0033 #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
0034 #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
0035 #define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
0036 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
0037 #define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */
0038 #define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0
0039 #define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT)
0040 #define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */
0041 #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
0042 #define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
0043 #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */
0044 #define I40E_PRTDCB_GENC_NUMTC_SHIFT 2
0045 #define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)
0046 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16
0047 #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
0048 #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */
0049 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
0050 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
0051 #define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */
0052 #define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0
0053 #define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
0054 #define I40E_PRTDCB_MFLCN_DPF_SHIFT 1
0055 #define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)
0056 #define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2
0057 #define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
0058 #define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3
0059 #define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
0060 #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
0061 #define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
0062 #define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */
0063 #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0
0064 #define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
0065 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
0066 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
0067 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2
0068 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
0069 #define I40E_PRTDCB_RETSC_LLTC_SHIFT 8
0070 #define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
0071 #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0072 #define I40E_PRTDCB_RETSTCC_MAX_INDEX 7
0073 #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0
0074 #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
0075 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
0076 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
0077 #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
0078 #define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
0079 #define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
0080 #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
0081 #define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
0082 #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
0083 #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
0084 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
0085 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
0086 #define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */
0087 #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
0088 #define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
0089 #define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */
0090 #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
0091 #define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
0092 #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
0093 #define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
0094 #define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6
0095 #define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
0096 #define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9
0097 #define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
0098 #define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12
0099 #define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
0100 #define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15
0101 #define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
0102 #define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18
0103 #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
0104 #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
0105 #define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
0106 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0107 #define I40E_PRTDCB_RUPTQ_MAX_INDEX 7
0108 #define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0
0109 #define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
0110 #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
0111 #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
0112 #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
0113 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0114 #define I40E_PRTDCB_TCMSTC_MAX_INDEX 7
0115 #define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0
0116 #define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
0117 #define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */
0118 #define I40E_PRTDCB_TCPMC_CPM_SHIFT 0
0119 #define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
0120 #define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13
0121 #define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
0122 #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
0123 #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
0124 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0125 #define I40E_PRTDCB_TCWSTC_MAX_INDEX 7
0126 #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
0127 #define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
0128 #define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */
0129 #define I40E_PRTDCB_TDPMC_DPM_SHIFT 0
0130 #define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
0131 #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
0132 #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
0133 #define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */
0134 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
0135 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, \
0136     I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
0137 #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8
0138 #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
0139 #define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */
0140 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
0141 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, \
0142     I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
0143 #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8
0144 #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
0145 #define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */
0146 #define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0
0147 #define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
0148 #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
0149 #define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
0150 #define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9
0151 #define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
0152 #define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10
0153 #define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
0154 #define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11
0155 #define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
0156 #define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12
0157 #define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
0158 #define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13
0159 #define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
0160 #define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14
0161 #define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
0162 #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
0163 #define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
0164 #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */
0165 #define I40E_PRTDCB_TPFCTS_MAX_INDEX 7
0166 #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
0167 #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
0168 #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */
0169 #define I40E_GL_FWSTS_FWS1B_SHIFT 16
0170 #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
0171 #define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT)
0172 #define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT)
0173 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT)
0174 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT)
0175 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT)
0176 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT)
0177 #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT)
0178 #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT)
0179 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
0180 #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29
0181 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0
0182 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
0183 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3
0184 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
0185 #define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4
0186 #define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5
0187 #define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6
0188 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7
0189 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
0190 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11
0191 #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12
0192 #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
0193 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT  19
0194 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK   I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
0195 #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
0196 #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
0197 #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5
0198 #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
0199 #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
0200 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
0201 #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0
0202 #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16
0203 #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21
0204 #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26
0205 #define I40E_GLGEN_MSCA_STCODE_SHIFT 28
0206 #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
0207 #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
0208 #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
0209 #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
0210 #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
0211 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
0212 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
0213 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
0214 #define I40E_GLGEN_PCIFCNCNT                0x001C0AB4 /* Reset: PCIR */
0215 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
0216 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
0217 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
0218 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
0219 #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
0220 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
0221 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
0222 #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2
0223 #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
0224 #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */
0225 #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0
0226 #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
0227 #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
0228 #define I40E_GLGEN_RTRIG_CORER_SHIFT 0
0229 #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
0230 #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1
0231 #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
0232 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
0233 #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
0234 #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */
0235 #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */
0236 #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
0237 #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)
0238 #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */
0239 #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
0240 #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
0241 #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */
0242 #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0
0243 #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
0244 #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */
0245 #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
0246 #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
0247 #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
0248 #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
0249 #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
0250 #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
0251 #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
0252 #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0253 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
0254 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
0255 #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0256 #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */
0257 #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0258 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
0259 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
0260 #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0261 #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */
0262 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
0263 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
0264 #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */
0265 #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */
0266 #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */
0267 #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0268 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
0269 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
0270 #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0271 #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */
0272 #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0273 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
0274 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
0275 #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0276 #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */
0277 #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */
0278 #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */
0279 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
0280 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
0281 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
0282 #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */
0283 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
0284 #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */
0285 #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */
0286 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
0287 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1
0288 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2
0289 #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */
0290 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
0291 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
0292 #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */
0293 #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0
0294 #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11
0295 #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30
0296 #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
0297 #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
0298 #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0
0299 #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11
0300 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16
0301 #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30
0302 #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
0303 #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */
0304 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1
0305 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT)
0306 #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */
0307 #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0
0308 #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
0309 #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1
0310 #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)
0311 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
0312 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
0313 #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3
0314 #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
0315 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
0316 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
0317 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
0318 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
0319 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
0320 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
0321 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
0322 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0
0323 #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
0324 #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1
0325 #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)
0326 #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
0327 #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
0328 #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3
0329 #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
0330 #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5
0331 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
0332 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
0333 #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */
0334 #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0
0335 #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)
0336 #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1
0337 #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT)
0338 #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16
0339 #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT)
0340 #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19
0341 #define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT)
0342 #define I40E_PFINT_ICR0_GRST_SHIFT 20
0343 #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT)
0344 #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21
0345 #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
0346 #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23
0347 #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT)
0348 #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26
0349 #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT)
0350 #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28
0351 #define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT)
0352 #define I40E_PFINT_ICR0_VFLR_SHIFT 29
0353 #define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT)
0354 #define I40E_PFINT_ICR0_ADMINQ_SHIFT 30
0355 #define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT)
0356 #define I40E_PFINT_ICR0_SWINT_SHIFT 31
0357 #define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT)
0358 #define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */
0359 #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16
0360 #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
0361 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19
0362 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)
0363 #define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20
0364 #define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT)
0365 #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21
0366 #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)
0367 #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22
0368 #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
0369 #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23
0370 #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
0371 #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26
0372 #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
0373 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28
0374 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)
0375 #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29
0376 #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
0377 #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30
0378 #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
0379 #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
0380 #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
0381 #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */
0382 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
0383 #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
0384 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
0385 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
0386 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
0387 #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
0388 #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */
0389 #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
0390 #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0
0391 #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
0392 #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11
0393 #define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT)
0394 #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13
0395 #define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)
0396 #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16
0397 #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
0398 #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27
0399 #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30
0400 #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
0401 #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31
0402 #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)
0403 #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
0404 #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0
0405 #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
0406 #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11
0407 #define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT)
0408 #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13
0409 #define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)
0410 #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16
0411 #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
0412 #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27
0413 #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30
0414 #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
0415 #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31
0416 #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)
0417 #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
0418 #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
0419 #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1
0420 #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
0421 #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30
0422 #define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)
0423 #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
0424 #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
0425 #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0
0426 #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11
0427 #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30
0428 #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
0429 #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */
0430 #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0
0431 #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11
0432 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16
0433 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
0434 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
0435 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
0436 #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30
0437 #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
0438 #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
0439 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
0440 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
0441 #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
0442 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
0443 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
0444 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
0445 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
0446 #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */
0447 #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
0448 #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
0449 #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */
0450 #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */
0451 #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */
0452 #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */
0453 #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0
0454 #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
0455 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
0456 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
0457 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
0458 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
0459 #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
0460 #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
0461 #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
0462 #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
0463 #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
0464 #define I40E_PFLAN_QALLOC_VALID_SHIFT 31
0465 #define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT)
0466 #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
0467 #define I40E_QRX_ENA_QENA_REQ_SHIFT 0
0468 #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
0469 #define I40E_QRX_ENA_QENA_STAT_SHIFT 2
0470 #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
0471 #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
0472 #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
0473 #define I40E_QTX_CTL_PFVF_Q_SHIFT 0
0474 #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
0475 #define I40E_QTX_CTL_PF_INDX_SHIFT 2
0476 #define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)
0477 #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
0478 #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
0479 #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
0480 #define I40E_QTX_ENA_QENA_REQ_SHIFT 0
0481 #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)
0482 #define I40E_QTX_ENA_QENA_STAT_SHIFT 2
0483 #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)
0484 #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
0485 #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
0486 #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
0487 #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
0488 #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
0489 #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */
0490 #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
0491 #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
0492 #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
0493 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
0494 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
0495 #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */
0496 #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */
0497 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
0498 #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
0499 #define I40E_PRTGL_SAH_MFS_SHIFT 16
0500 #define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)
0501 #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */
0502 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
0503 #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
0504 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */
0505 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
0506 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, \
0507     I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
0508 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */
0509 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
0510 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, \
0511     I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
0512 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */
0513 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
0514 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, \
0515     I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
0516 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */
0517 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
0518 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, \
0519     I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
0520 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */
0521 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
0522 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
0523 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, \
0524     I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
0525 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
0526 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6
0527 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
0528 #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */
0529 #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5
0530 #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)
0531 #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */
0532 #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14
0533 #define I40E_GLNVM_SRCTL_START_SHIFT 30
0534 #define I40E_GLNVM_SRCTL_DONE_SHIFT 31
0535 #define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT)
0536 #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
0537 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
0538 #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
0539 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
0540 #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3
0541 #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)
0542 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4
0543 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)
0544 #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */
0545 #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4
0546 #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
0547 #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */
0548 #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2
0549 #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
0550 #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13
0551 #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
0552 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
0553 #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6
0554 #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
0555 #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
0556 #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */
0557 #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12
0558 #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */
0559 #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */
0560 #define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */
0561 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
0562 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
0563 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
0564 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
0565 #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
0566 #define I40E_PRTPM_EEER_TX_LPI_EN_MASK  I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
0567 #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */
0568 #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */
0569 #define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0570 #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
0571 #define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
0572 #define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0573 #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
0574 #define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
0575 #define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0576 #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
0577 #define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
0578 #define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0579 #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
0580 #define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
0581 #define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */
0582 #define I40E_PRTRPB_SHW_SHW_SHIFT 0
0583 #define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
0584 #define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
0585 #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
0586 #define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
0587 #define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */
0588 #define I40E_PRTRPB_SLW_SLW_SHIFT 0
0589 #define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
0590 #define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */
0591 #define I40E_PRTRPB_SPS_SPS_SHIFT 0
0592 #define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
0593 #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */
0594 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
0595 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
0596 #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13
0597 #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
0598 #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
0599 #define I40E_GLQF_HKEY_MAX_INDEX 12
0600 #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */
0601 #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */
0602 #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0
0603 #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
0604 #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5
0605 #define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT)
0606 #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10
0607 #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)
0608 #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14
0609 #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)
0610 #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16
0611 #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)
0612 #define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17
0613 #define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT)
0614 #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18
0615 #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
0616 #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19
0617 #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
0618 #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */
0619 #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
0620 #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
0621 #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */
0622 #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
0623 #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
0624 #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16
0625 #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
0626 #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */
0627 #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */
0628 #define I40E_PFQF_HKEY_MAX_INDEX 12
0629 #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */
0630 #define I40E_PFQF_HLUT_MAX_INDEX 127
0631 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
0632 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63
0633 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
0634 #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
0635 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
0636 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63
0637 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
0638 #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
0639 #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */
0640 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
0641 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
0642 #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5
0643 #define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
0644 #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10
0645 #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
0646 #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */
0647 #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */
0648 #define I40E_VFQF_HKEY1_MAX_INDEX 12
0649 #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
0650 #define I40E_VFQF_HLUT1_MAX_INDEX 15
0651 #define I40E_GL_RXERR1H(_i)             (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
0652 #define I40E_GL_RXERR1H_MAX_INDEX       143
0653 #define I40E_GL_RXERR1H_RXERR1H_SHIFT   0
0654 #define I40E_GL_RXERR1H_RXERR1H_MASK    I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT)
0655 #define I40E_GL_RXERR1L(_i)             (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
0656 #define I40E_GL_RXERR1L_MAX_INDEX       143
0657 #define I40E_GL_RXERR1L_RXERR1L_SHIFT   0
0658 #define I40E_GL_RXERR1L_RXERR1L_MASK    I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT)
0659 #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0660 #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0661 #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0662 #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0663 #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0664 #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0665 #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0666 #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0667 #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0668 #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0669 #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0670 #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0671 #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0672 #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0673 #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0674 #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0675 #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0676 #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0677 #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0678 #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0679 #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0680 #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0681 #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0682 #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0683 #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0684 #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0685 #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0686 #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0687 #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0688 #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0689 #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0690 #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0691 #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0692 #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0693 #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0694 #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0695 #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0696 #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0697 #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0698 #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0699 #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0700 #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0701 #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0702 #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0703 #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0704 #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0705 #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0706 #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0707 #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
0708 #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
0709 #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
0710 #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
0711 #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0712 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0713 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0714 #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0715 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0716 #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0717 #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
0718 #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0719 #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0720 #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0721 #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0722 #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
0723 #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0724 #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0725 #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0726 #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0727 #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0728 #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0729 #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0730 #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0731 #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0732 #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0733 #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0734 #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0735 #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0736 #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0737 #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0738 #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0739 #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0740 #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
0741 #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0742 #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0743 #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0744 #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0745 #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0746 #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0747 #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0748 #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0749 #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0750 #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0751 #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0752 #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0753 #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0754 #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0755 #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0756 #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0757 #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0758 #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0759 #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
0760 #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0761 #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0762 #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0763 #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0764 #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0765 #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0766 #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0767 #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
0768 #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */
0769 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1
0770 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)
0771 #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2
0772 #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)
0773 #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8
0774 #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)
0775 #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31
0776 #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
0777 #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */
0778 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0
0779 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
0780 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16
0781 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
0782 #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24
0783 #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26
0784 #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
0785 #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31
0786 #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
0787 #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */
0788 #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */
0789 #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
0790 #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
0791 #define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3
0792 #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */
0793 #define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0
0794 #define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
0795 #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4
0796 #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
0797 #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */
0798 #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */
0799 #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */
0800 #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */
0801 #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
0802 #define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0803 #define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0804 #define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0805 #define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0
0806 #define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1
0807 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
0808 #define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17
0809 #define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT)
0810 #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0811 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0
0812 #define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0813 #define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0814 #define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
0815 #define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */
0816 #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
0817 #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
0818 #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
0819 #define I40E_GL_MDET_RX_EVENT_SHIFT 8
0820 #define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT)
0821 #define I40E_GL_MDET_RX_QUEUE_SHIFT 17
0822 #define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT)
0823 #define I40E_GL_MDET_RX_VALID_SHIFT 31
0824 #define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT)
0825 #define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */
0826 #define I40E_GL_MDET_TX_QUEUE_SHIFT 0
0827 #define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT)
0828 #define I40E_GL_MDET_TX_VF_NUM_SHIFT 12
0829 #define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT)
0830 #define I40E_GL_MDET_TX_PF_NUM_SHIFT 21
0831 #define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT)
0832 #define I40E_GL_MDET_TX_EVENT_SHIFT 25
0833 #define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT)
0834 #define I40E_GL_MDET_TX_VALID_SHIFT 31
0835 #define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT)
0836 #define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */
0837 #define I40E_PF_MDET_RX_VALID_SHIFT 0
0838 #define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT)
0839 #define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */
0840 #define I40E_PF_MDET_TX_VALID_SHIFT 0
0841 #define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)
0842 #define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */
0843 #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0
0844 #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
0845 #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
0846 #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
0847 #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
0848 #define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT)
0849 #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
0850 #define I40E_VP_MDET_RX_VALID_SHIFT 0
0851 #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)
0852 #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
0853 #define I40E_VP_MDET_TX_VALID_SHIFT 0
0854 #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)
0855 #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */
0856 #define I40E_PFPM_APM_APME_SHIFT 0
0857 #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)
0858 #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */
0859 #define I40E_PFPM_WUFC_MAG_SHIFT 1
0860 #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)
0861 #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
0862 #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
0863 #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
0864 #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
0865 #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
0866 #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
0867 #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
0868 #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
0869 #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
0870 #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
0871 #define I40E_VFQF_HLUT_MAX_INDEX 15
0872 
0873 
0874 
0875 
0876 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
0877 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
0878 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
0879 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
0880 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
0881 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6
0882 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
0883 
0884 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
0885 
0886 
0887 
0888 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
0889 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
0890 #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0
0891 #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT)
0892 #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5
0893 #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT)
0894 #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7
0895 #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT)
0896 #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
0897 /* Redefined for X722 family */
0898 #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */
0899 #endif /* _I40E_REGISTER_H_ */
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