intel/i40e/i40e_lan_hmc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2013 - 2018 Intel Corporation. */
0003
0004 #ifndef _I40E_LAN_HMC_H_
0005 #define _I40E_LAN_HMC_H_
0006
0007 /* forward-declare the HW struct for the compiler */
0008 struct i40e_hw;
0009
0010 /* HMC element context information */
0011
0012 /* Rx queue context data
0013  *
0014  * The sizes of the variables may be larger than needed due to crossing byte
0015  * boundaries. If we do not have the width of the variable set to the correct
0016  * size then we could end up shifting bits off the top of the variable when the
0017  * variable is at the top of a byte and crosses over into the next byte.
0018  */
0019 struct i40e_hmc_obj_rxq {
0020     u16 head;
0021     u16 cpuid; /* bigger than needed, see above for reason */
0022     u64 base;
0023     u16 qlen;
0024 #define I40E_RXQ_CTX_DBUFF_SHIFT 7
0025     u16 dbuff; /* bigger than needed, see above for reason */
0026 #define I40E_RXQ_CTX_HBUFF_SHIFT 6
0027     u16 hbuff; /* bigger than needed, see above for reason */
0028     u8  dtype;
0029     u8  dsize;
0030     u8  crcstrip;
0031     u8  fc_ena;
0032     u8  l2tsel;
0033     u8  hsplit_0;
0034     u8  hsplit_1;
0035     u8  showiv;
0036     u32 rxmax; /* bigger than needed, see above for reason */
0037     u8  tphrdesc_ena;
0038     u8  tphwdesc_ena;
0039     u8  tphdata_ena;
0040     u8  tphhead_ena;
0041     u16 lrxqthresh; /* bigger than needed, see above for reason */
0042     u8  prefena;    /* NOTE: normally must be set to 1 at init */
0043 };
0044
0045 /* Tx queue context data
0046 *
0047 * The sizes of the variables may be larger than needed due to crossing byte
0048 * boundaries. If we do not have the width of the variable set to the correct
0049 * size then we could end up shifting bits off the top of the variable when the
0050 * variable is at the top of a byte and crosses over into the next byte.
0051 */
0052 struct i40e_hmc_obj_txq {
0053     u16 head;
0054     u8  new_context;
0055     u64 base;
0056     u8  fc_ena;
0057     u8  timesync_ena;
0058     u8  fd_ena;
0059     u8  alt_vlan_ena;
0060     u16 thead_wb;
0061     u8  cpuid;
0062     u8  head_wb_ena;
0063     u16 qlen;
0064     u8  tphrdesc_ena;
0065     u8  tphrpacket_ena;
0066     u8  tphwdesc_ena;
0067     u64 head_wb_addr;
0068     u32 crc;
0069     u16 rdylist;
0070     u8  rdylist_act;
0071 };
0072
0073 /* for hsplit_0 field of Rx HMC context */
0074 enum i40e_hmc_obj_rx_hsplit_0 {
0075     I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT      = 0,
0076     I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2      = 1,
0077     I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP      = 2,
0078     I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
0079     I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP    = 8,
0080 };
0081
0082 /* fcoe_cntx and fcoe_filt are for debugging purpose only */
0083 struct i40e_hmc_obj_fcoe_cntx {
0084     u32 rsv[32];
0085 };
0086
0087 struct i40e_hmc_obj_fcoe_filt {
0088     u32 rsv[8];
0089 };
0090
0091 /* Context sizes for LAN objects */
0092 enum i40e_hmc_lan_object_size {
0093     I40E_HMC_LAN_OBJ_SZ_8   = 0x3,
0094     I40E_HMC_LAN_OBJ_SZ_16  = 0x4,
0095     I40E_HMC_LAN_OBJ_SZ_32  = 0x5,
0096     I40E_HMC_LAN_OBJ_SZ_64  = 0x6,
0097     I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
0098     I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
0099     I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
0100 };
0101
0102 #define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
0103 #define I40E_HMC_OBJ_SIZE_TXQ         128
0104 #define I40E_HMC_OBJ_SIZE_RXQ         32
0105 #define I40E_HMC_OBJ_SIZE_FCOE_CNTX   64
0106 #define I40E_HMC_OBJ_SIZE_FCOE_FILT   64
0107
0108 enum i40e_hmc_lan_rsrc_type {
0109     I40E_HMC_LAN_FULL  = 0,
0110     I40E_HMC_LAN_TX    = 1,
0111     I40E_HMC_LAN_RX    = 2,
0112     I40E_HMC_FCOE_CTX  = 3,
0113     I40E_HMC_FCOE_FILT = 4,
0114     I40E_HMC_LAN_MAX   = 5
0115 };
0116
0117 enum i40e_hmc_model {
0118     I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
0119     I40E_HMC_MODEL_DIRECT_ONLY      = 1,
0120     I40E_HMC_MODEL_PAGED_ONLY       = 2,
0121     I40E_HMC_MODEL_UNKNOWN,
0122 };
0123
0124 struct i40e_hmc_lan_create_obj_info {
0125     struct i40e_hmc_info *hmc_info;
0126     u32 rsrc_type;
0127     u32 start_idx;
0128     u32 count;
0129     enum i40e_sd_entry_type entry_type;
0130     u64 direct_mode_sz;
0131 };
0132
0133 struct i40e_hmc_lan_delete_obj_info {
0134     struct i40e_hmc_info *hmc_info;
0135     u32 rsrc_type;
0136     u32 start_idx;
0137     u32 count;
0138 };
0139
0140 i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
0141                     u32 rxq_num, u32 fcoe_cntx_num,
0142                     u32 fcoe_filt_num);
0143 i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
0144                          enum i40e_hmc_model model);
0145 i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
0146
0147 i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
0148                               u16 queue);
0149 i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
0150                             u16 queue,
0151                             struct i40e_hmc_obj_txq *s);
0152 i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
0153                               u16 queue);
0154 i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
0155                             u16 queue,
0156                             struct i40e_hmc_obj_rxq *s);
0157
0158 #endif /* _I40E_LAN_HMC_H_ */