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0006 #include "i40e.h"
0007 #include "i40e_diag.h"
0008 #include "i40e_txrx_common.h"
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0034 struct i40e_stats {
0035 char stat_string[ETH_GSTRING_LEN];
0036 int sizeof_stat;
0037 int stat_offset;
0038 };
0039
0040
0041
0042
0043
0044 #define I40E_STAT(_type, _name, _stat) { \
0045 .stat_string = _name, \
0046 .sizeof_stat = sizeof_field(_type, _stat), \
0047 .stat_offset = offsetof(_type, _stat) \
0048 }
0049
0050
0051
0052
0053 #define I40E_NETDEV_STAT(_net_stat) \
0054 I40E_STAT(struct rtnl_link_stats64, #_net_stat, _net_stat)
0055
0056
0057 #define I40E_QUEUE_STAT(_name, _stat) \
0058 I40E_STAT(struct i40e_ring, _name, _stat)
0059
0060
0061 static const struct i40e_stats i40e_gstrings_queue_stats[] = {
0062 I40E_QUEUE_STAT("%s-%u.packets", stats.packets),
0063 I40E_QUEUE_STAT("%s-%u.bytes", stats.bytes),
0064 };
0065
0066
0067
0068
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0071
0072
0073
0074
0075
0076 static void
0077 i40e_add_one_ethtool_stat(u64 *data, void *pointer,
0078 const struct i40e_stats *stat)
0079 {
0080 char *p;
0081
0082 if (!pointer) {
0083
0084
0085
0086 *data = 0;
0087 return;
0088 }
0089
0090 p = (char *)pointer + stat->stat_offset;
0091 switch (stat->sizeof_stat) {
0092 case sizeof(u64):
0093 *data = *((u64 *)p);
0094 break;
0095 case sizeof(u32):
0096 *data = *((u32 *)p);
0097 break;
0098 case sizeof(u16):
0099 *data = *((u16 *)p);
0100 break;
0101 case sizeof(u8):
0102 *data = *((u8 *)p);
0103 break;
0104 default:
0105 WARN_ONCE(1, "unexpected stat size for %s",
0106 stat->stat_string);
0107 *data = 0;
0108 }
0109 }
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124 static void
0125 __i40e_add_ethtool_stats(u64 **data, void *pointer,
0126 const struct i40e_stats stats[],
0127 const unsigned int size)
0128 {
0129 unsigned int i;
0130
0131 for (i = 0; i < size; i++)
0132 i40e_add_one_ethtool_stat((*data)++, pointer, &stats[i]);
0133 }
0134
0135
0136
0137
0138
0139
0140
0141
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0144
0145
0146
0147
0148 #define i40e_add_ethtool_stats(data, pointer, stats) \
0149 __i40e_add_ethtool_stats(data, pointer, stats, ARRAY_SIZE(stats))
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165 static void
0166 i40e_add_queue_stats(u64 **data, struct i40e_ring *ring)
0167 {
0168 const unsigned int size = ARRAY_SIZE(i40e_gstrings_queue_stats);
0169 const struct i40e_stats *stats = i40e_gstrings_queue_stats;
0170 unsigned int start;
0171 unsigned int i;
0172
0173
0174
0175
0176
0177
0178 do {
0179 start = !ring ? 0 : u64_stats_fetch_begin_irq(&ring->syncp);
0180 for (i = 0; i < size; i++) {
0181 i40e_add_one_ethtool_stat(&(*data)[i], ring,
0182 &stats[i]);
0183 }
0184 } while (ring && u64_stats_fetch_retry_irq(&ring->syncp, start));
0185
0186
0187 *data += size;
0188 }
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199 static void __i40e_add_stat_strings(u8 **p, const struct i40e_stats stats[],
0200 const unsigned int size, ...)
0201 {
0202 unsigned int i;
0203
0204 for (i = 0; i < size; i++) {
0205 va_list args;
0206
0207 va_start(args, size);
0208 vsnprintf(*p, ETH_GSTRING_LEN, stats[i].stat_string, args);
0209 *p += ETH_GSTRING_LEN;
0210 va_end(args);
0211 }
0212 }
0213
0214
0215
0216
0217
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0219
0220
0221
0222
0223
0224
0225
0226 #define i40e_add_stat_strings(p, stats, ...) \
0227 __i40e_add_stat_strings(p, stats, ARRAY_SIZE(stats), ## __VA_ARGS__)
0228
0229 #define I40E_PF_STAT(_name, _stat) \
0230 I40E_STAT(struct i40e_pf, _name, _stat)
0231 #define I40E_VSI_STAT(_name, _stat) \
0232 I40E_STAT(struct i40e_vsi, _name, _stat)
0233 #define I40E_VEB_STAT(_name, _stat) \
0234 I40E_STAT(struct i40e_veb, _name, _stat)
0235 #define I40E_VEB_TC_STAT(_name, _stat) \
0236 I40E_STAT(struct i40e_cp_veb_tc_stats, _name, _stat)
0237 #define I40E_PFC_STAT(_name, _stat) \
0238 I40E_STAT(struct i40e_pfc_stats, _name, _stat)
0239
0240 static const struct i40e_stats i40e_gstrings_net_stats[] = {
0241 I40E_NETDEV_STAT(rx_packets),
0242 I40E_NETDEV_STAT(tx_packets),
0243 I40E_NETDEV_STAT(rx_bytes),
0244 I40E_NETDEV_STAT(tx_bytes),
0245 I40E_NETDEV_STAT(rx_errors),
0246 I40E_NETDEV_STAT(tx_errors),
0247 I40E_NETDEV_STAT(rx_dropped),
0248 I40E_NETDEV_STAT(tx_dropped),
0249 I40E_NETDEV_STAT(collisions),
0250 I40E_NETDEV_STAT(rx_length_errors),
0251 I40E_NETDEV_STAT(rx_crc_errors),
0252 };
0253
0254 static const struct i40e_stats i40e_gstrings_veb_stats[] = {
0255 I40E_VEB_STAT("veb.rx_bytes", stats.rx_bytes),
0256 I40E_VEB_STAT("veb.tx_bytes", stats.tx_bytes),
0257 I40E_VEB_STAT("veb.rx_unicast", stats.rx_unicast),
0258 I40E_VEB_STAT("veb.tx_unicast", stats.tx_unicast),
0259 I40E_VEB_STAT("veb.rx_multicast", stats.rx_multicast),
0260 I40E_VEB_STAT("veb.tx_multicast", stats.tx_multicast),
0261 I40E_VEB_STAT("veb.rx_broadcast", stats.rx_broadcast),
0262 I40E_VEB_STAT("veb.tx_broadcast", stats.tx_broadcast),
0263 I40E_VEB_STAT("veb.rx_discards", stats.rx_discards),
0264 I40E_VEB_STAT("veb.tx_discards", stats.tx_discards),
0265 I40E_VEB_STAT("veb.tx_errors", stats.tx_errors),
0266 I40E_VEB_STAT("veb.rx_unknown_protocol", stats.rx_unknown_protocol),
0267 };
0268
0269 struct i40e_cp_veb_tc_stats {
0270 u64 tc_rx_packets;
0271 u64 tc_rx_bytes;
0272 u64 tc_tx_packets;
0273 u64 tc_tx_bytes;
0274 };
0275
0276 static const struct i40e_stats i40e_gstrings_veb_tc_stats[] = {
0277 I40E_VEB_TC_STAT("veb.tc_%u_tx_packets", tc_tx_packets),
0278 I40E_VEB_TC_STAT("veb.tc_%u_tx_bytes", tc_tx_bytes),
0279 I40E_VEB_TC_STAT("veb.tc_%u_rx_packets", tc_rx_packets),
0280 I40E_VEB_TC_STAT("veb.tc_%u_rx_bytes", tc_rx_bytes),
0281 };
0282
0283 static const struct i40e_stats i40e_gstrings_misc_stats[] = {
0284 I40E_VSI_STAT("rx_unicast", eth_stats.rx_unicast),
0285 I40E_VSI_STAT("tx_unicast", eth_stats.tx_unicast),
0286 I40E_VSI_STAT("rx_multicast", eth_stats.rx_multicast),
0287 I40E_VSI_STAT("tx_multicast", eth_stats.tx_multicast),
0288 I40E_VSI_STAT("rx_broadcast", eth_stats.rx_broadcast),
0289 I40E_VSI_STAT("tx_broadcast", eth_stats.tx_broadcast),
0290 I40E_VSI_STAT("rx_unknown_protocol", eth_stats.rx_unknown_protocol),
0291 I40E_VSI_STAT("tx_linearize", tx_linearize),
0292 I40E_VSI_STAT("tx_force_wb", tx_force_wb),
0293 I40E_VSI_STAT("tx_busy", tx_busy),
0294 I40E_VSI_STAT("tx_stopped", tx_stopped),
0295 I40E_VSI_STAT("rx_alloc_fail", rx_buf_failed),
0296 I40E_VSI_STAT("rx_pg_alloc_fail", rx_page_failed),
0297 I40E_VSI_STAT("rx_cache_reuse", rx_page_reuse),
0298 I40E_VSI_STAT("rx_cache_alloc", rx_page_alloc),
0299 I40E_VSI_STAT("rx_cache_waive", rx_page_waive),
0300 I40E_VSI_STAT("rx_cache_busy", rx_page_busy),
0301 I40E_VSI_STAT("tx_restart", tx_restart),
0302 };
0303
0304
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314 static const struct i40e_stats i40e_gstrings_stats[] = {
0315 I40E_PF_STAT("port.rx_bytes", stats.eth.rx_bytes),
0316 I40E_PF_STAT("port.tx_bytes", stats.eth.tx_bytes),
0317 I40E_PF_STAT("port.rx_unicast", stats.eth.rx_unicast),
0318 I40E_PF_STAT("port.tx_unicast", stats.eth.tx_unicast),
0319 I40E_PF_STAT("port.rx_multicast", stats.eth.rx_multicast),
0320 I40E_PF_STAT("port.tx_multicast", stats.eth.tx_multicast),
0321 I40E_PF_STAT("port.rx_broadcast", stats.eth.rx_broadcast),
0322 I40E_PF_STAT("port.tx_broadcast", stats.eth.tx_broadcast),
0323 I40E_PF_STAT("port.tx_errors", stats.eth.tx_errors),
0324 I40E_PF_STAT("port.rx_dropped", stats.eth.rx_discards),
0325 I40E_PF_STAT("port.tx_dropped_link_down", stats.tx_dropped_link_down),
0326 I40E_PF_STAT("port.rx_crc_errors", stats.crc_errors),
0327 I40E_PF_STAT("port.illegal_bytes", stats.illegal_bytes),
0328 I40E_PF_STAT("port.mac_local_faults", stats.mac_local_faults),
0329 I40E_PF_STAT("port.mac_remote_faults", stats.mac_remote_faults),
0330 I40E_PF_STAT("port.tx_timeout", tx_timeout_count),
0331 I40E_PF_STAT("port.rx_csum_bad", hw_csum_rx_error),
0332 I40E_PF_STAT("port.rx_length_errors", stats.rx_length_errors),
0333 I40E_PF_STAT("port.link_xon_rx", stats.link_xon_rx),
0334 I40E_PF_STAT("port.link_xoff_rx", stats.link_xoff_rx),
0335 I40E_PF_STAT("port.link_xon_tx", stats.link_xon_tx),
0336 I40E_PF_STAT("port.link_xoff_tx", stats.link_xoff_tx),
0337 I40E_PF_STAT("port.rx_size_64", stats.rx_size_64),
0338 I40E_PF_STAT("port.rx_size_127", stats.rx_size_127),
0339 I40E_PF_STAT("port.rx_size_255", stats.rx_size_255),
0340 I40E_PF_STAT("port.rx_size_511", stats.rx_size_511),
0341 I40E_PF_STAT("port.rx_size_1023", stats.rx_size_1023),
0342 I40E_PF_STAT("port.rx_size_1522", stats.rx_size_1522),
0343 I40E_PF_STAT("port.rx_size_big", stats.rx_size_big),
0344 I40E_PF_STAT("port.tx_size_64", stats.tx_size_64),
0345 I40E_PF_STAT("port.tx_size_127", stats.tx_size_127),
0346 I40E_PF_STAT("port.tx_size_255", stats.tx_size_255),
0347 I40E_PF_STAT("port.tx_size_511", stats.tx_size_511),
0348 I40E_PF_STAT("port.tx_size_1023", stats.tx_size_1023),
0349 I40E_PF_STAT("port.tx_size_1522", stats.tx_size_1522),
0350 I40E_PF_STAT("port.tx_size_big", stats.tx_size_big),
0351 I40E_PF_STAT("port.rx_undersize", stats.rx_undersize),
0352 I40E_PF_STAT("port.rx_fragments", stats.rx_fragments),
0353 I40E_PF_STAT("port.rx_oversize", stats.rx_oversize),
0354 I40E_PF_STAT("port.rx_jabber", stats.rx_jabber),
0355 I40E_PF_STAT("port.VF_admin_queue_requests", vf_aq_requests),
0356 I40E_PF_STAT("port.arq_overflows", arq_overflows),
0357 I40E_PF_STAT("port.tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
0358 I40E_PF_STAT("port.rx_hwtstamp_cleared", rx_hwtstamp_cleared),
0359 I40E_PF_STAT("port.tx_hwtstamp_skipped", tx_hwtstamp_skipped),
0360 I40E_PF_STAT("port.fdir_flush_cnt", fd_flush_cnt),
0361 I40E_PF_STAT("port.fdir_atr_match", stats.fd_atr_match),
0362 I40E_PF_STAT("port.fdir_atr_tunnel_match", stats.fd_atr_tunnel_match),
0363 I40E_PF_STAT("port.fdir_atr_status", stats.fd_atr_status),
0364 I40E_PF_STAT("port.fdir_sb_match", stats.fd_sb_match),
0365 I40E_PF_STAT("port.fdir_sb_status", stats.fd_sb_status),
0366
0367
0368 I40E_PF_STAT("port.tx_lpi_status", stats.tx_lpi_status),
0369 I40E_PF_STAT("port.rx_lpi_status", stats.rx_lpi_status),
0370 I40E_PF_STAT("port.tx_lpi_count", stats.tx_lpi_count),
0371 I40E_PF_STAT("port.rx_lpi_count", stats.rx_lpi_count),
0372 };
0373
0374 struct i40e_pfc_stats {
0375 u64 priority_xon_rx;
0376 u64 priority_xoff_rx;
0377 u64 priority_xon_tx;
0378 u64 priority_xoff_tx;
0379 u64 priority_xon_2_xoff;
0380 };
0381
0382 static const struct i40e_stats i40e_gstrings_pfc_stats[] = {
0383 I40E_PFC_STAT("port.tx_priority_%u_xon_tx", priority_xon_tx),
0384 I40E_PFC_STAT("port.tx_priority_%u_xoff_tx", priority_xoff_tx),
0385 I40E_PFC_STAT("port.rx_priority_%u_xon_rx", priority_xon_rx),
0386 I40E_PFC_STAT("port.rx_priority_%u_xoff_rx", priority_xoff_rx),
0387 I40E_PFC_STAT("port.rx_priority_%u_xon_2_xoff", priority_xon_2_xoff),
0388 };
0389
0390 #define I40E_NETDEV_STATS_LEN ARRAY_SIZE(i40e_gstrings_net_stats)
0391
0392 #define I40E_MISC_STATS_LEN ARRAY_SIZE(i40e_gstrings_misc_stats)
0393
0394 #define I40E_VSI_STATS_LEN (I40E_NETDEV_STATS_LEN + I40E_MISC_STATS_LEN)
0395
0396 #define I40E_PFC_STATS_LEN (ARRAY_SIZE(i40e_gstrings_pfc_stats) * \
0397 I40E_MAX_USER_PRIORITY)
0398
0399 #define I40E_VEB_STATS_LEN (ARRAY_SIZE(i40e_gstrings_veb_stats) + \
0400 (ARRAY_SIZE(i40e_gstrings_veb_tc_stats) * \
0401 I40E_MAX_TRAFFIC_CLASS))
0402
0403 #define I40E_GLOBAL_STATS_LEN ARRAY_SIZE(i40e_gstrings_stats)
0404
0405 #define I40E_PF_STATS_LEN (I40E_GLOBAL_STATS_LEN + \
0406 I40E_PFC_STATS_LEN + \
0407 I40E_VEB_STATS_LEN + \
0408 I40E_VSI_STATS_LEN)
0409
0410
0411 #define I40E_QUEUE_STATS_LEN ARRAY_SIZE(i40e_gstrings_queue_stats)
0412
0413 enum i40e_ethtool_test_id {
0414 I40E_ETH_TEST_REG = 0,
0415 I40E_ETH_TEST_EEPROM,
0416 I40E_ETH_TEST_INTR,
0417 I40E_ETH_TEST_LINK,
0418 };
0419
0420 static const char i40e_gstrings_test[][ETH_GSTRING_LEN] = {
0421 "Register test (offline)",
0422 "Eeprom test (offline)",
0423 "Interrupt test (offline)",
0424 "Link test (on/offline)"
0425 };
0426
0427 #define I40E_TEST_LEN (sizeof(i40e_gstrings_test) / ETH_GSTRING_LEN)
0428
0429 struct i40e_priv_flags {
0430 char flag_string[ETH_GSTRING_LEN];
0431 u64 flag;
0432 bool read_only;
0433 };
0434
0435 #define I40E_PRIV_FLAG(_name, _flag, _read_only) { \
0436 .flag_string = _name, \
0437 .flag = _flag, \
0438 .read_only = _read_only, \
0439 }
0440
0441 static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {
0442
0443 I40E_PRIV_FLAG("MFP", I40E_FLAG_MFP_ENABLED, 1),
0444 I40E_PRIV_FLAG("total-port-shutdown",
0445 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED, 1),
0446 I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),
0447 I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),
0448 I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),
0449 I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENABLED, 0),
0450 I40E_PRIV_FLAG("link-down-on-close",
0451 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED, 0),
0452 I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),
0453 I40E_PRIV_FLAG("disable-source-pruning",
0454 I40E_FLAG_SOURCE_PRUNING_DISABLED, 0),
0455 I40E_PRIV_FLAG("disable-fw-lldp", I40E_FLAG_DISABLE_FW_LLDP, 0),
0456 I40E_PRIV_FLAG("rs-fec", I40E_FLAG_RS_FEC, 0),
0457 I40E_PRIV_FLAG("base-r-fec", I40E_FLAG_BASE_R_FEC, 0),
0458 I40E_PRIV_FLAG("vf-vlan-pruning",
0459 I40E_FLAG_VF_VLAN_PRUNING, 0),
0460 };
0461
0462 #define I40E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gstrings_priv_flags)
0463
0464
0465 static const struct i40e_priv_flags i40e_gl_gstrings_priv_flags[] = {
0466 I40E_PRIV_FLAG("vf-true-promisc-support",
0467 I40E_FLAG_TRUE_PROMISC_SUPPORT, 0),
0468 };
0469
0470 #define I40E_GL_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gl_gstrings_priv_flags)
0471
0472
0473
0474
0475
0476 static void i40e_partition_setting_complaint(struct i40e_pf *pf)
0477 {
0478 dev_info(&pf->pdev->dev,
0479 "The link settings are allowed to be changed only from the first partition of a given port. Please switch to the first partition in order to change the setting.\n");
0480 }
0481
0482
0483
0484
0485
0486
0487
0488 static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,
0489 struct ethtool_link_ksettings *ks)
0490 {
0491 struct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;
0492 u64 phy_types = pf->hw.phy.phy_types;
0493
0494 ethtool_link_ksettings_zero_link_mode(ks, supported);
0495 ethtool_link_ksettings_zero_link_mode(ks, advertising);
0496
0497 if (phy_types & I40E_CAP_PHY_TYPE_SGMII) {
0498 ethtool_link_ksettings_add_link_mode(ks, supported,
0499 1000baseT_Full);
0500 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
0501 ethtool_link_ksettings_add_link_mode(ks, advertising,
0502 1000baseT_Full);
0503 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
0504 ethtool_link_ksettings_add_link_mode(ks, supported,
0505 100baseT_Full);
0506 ethtool_link_ksettings_add_link_mode(ks, advertising,
0507 100baseT_Full);
0508 }
0509 }
0510 if (phy_types & I40E_CAP_PHY_TYPE_XAUI ||
0511 phy_types & I40E_CAP_PHY_TYPE_XFI ||
0512 phy_types & I40E_CAP_PHY_TYPE_SFI ||
0513 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU ||
0514 phy_types & I40E_CAP_PHY_TYPE_10GBASE_AOC) {
0515 ethtool_link_ksettings_add_link_mode(ks, supported,
0516 10000baseT_Full);
0517 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0518 ethtool_link_ksettings_add_link_mode(ks, advertising,
0519 10000baseT_Full);
0520 }
0521 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_T) {
0522 ethtool_link_ksettings_add_link_mode(ks, supported,
0523 10000baseT_Full);
0524 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0525 ethtool_link_ksettings_add_link_mode(ks, advertising,
0526 10000baseT_Full);
0527 }
0528 if (phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T) {
0529 ethtool_link_ksettings_add_link_mode(ks, supported,
0530 2500baseT_Full);
0531 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
0532 ethtool_link_ksettings_add_link_mode(ks, advertising,
0533 2500baseT_Full);
0534 }
0535 if (phy_types & I40E_CAP_PHY_TYPE_5GBASE_T) {
0536 ethtool_link_ksettings_add_link_mode(ks, supported,
0537 5000baseT_Full);
0538 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
0539 ethtool_link_ksettings_add_link_mode(ks, advertising,
0540 5000baseT_Full);
0541 }
0542 if (phy_types & I40E_CAP_PHY_TYPE_XLAUI ||
0543 phy_types & I40E_CAP_PHY_TYPE_XLPPI ||
0544 phy_types & I40E_CAP_PHY_TYPE_40GBASE_AOC)
0545 ethtool_link_ksettings_add_link_mode(ks, supported,
0546 40000baseCR4_Full);
0547 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
0548 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4) {
0549 ethtool_link_ksettings_add_link_mode(ks, supported,
0550 40000baseCR4_Full);
0551 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_40GB)
0552 ethtool_link_ksettings_add_link_mode(ks, advertising,
0553 40000baseCR4_Full);
0554 }
0555 if (phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
0556 ethtool_link_ksettings_add_link_mode(ks, supported,
0557 100baseT_Full);
0558 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
0559 ethtool_link_ksettings_add_link_mode(ks, advertising,
0560 100baseT_Full);
0561 }
0562 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_T) {
0563 ethtool_link_ksettings_add_link_mode(ks, supported,
0564 1000baseT_Full);
0565 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
0566 ethtool_link_ksettings_add_link_mode(ks, advertising,
0567 1000baseT_Full);
0568 }
0569 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_SR4) {
0570 ethtool_link_ksettings_add_link_mode(ks, supported,
0571 40000baseSR4_Full);
0572 ethtool_link_ksettings_add_link_mode(ks, advertising,
0573 40000baseSR4_Full);
0574 }
0575 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_LR4) {
0576 ethtool_link_ksettings_add_link_mode(ks, supported,
0577 40000baseLR4_Full);
0578 ethtool_link_ksettings_add_link_mode(ks, advertising,
0579 40000baseLR4_Full);
0580 }
0581 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4) {
0582 ethtool_link_ksettings_add_link_mode(ks, supported,
0583 40000baseKR4_Full);
0584 ethtool_link_ksettings_add_link_mode(ks, advertising,
0585 40000baseKR4_Full);
0586 }
0587 if (phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2) {
0588 ethtool_link_ksettings_add_link_mode(ks, supported,
0589 20000baseKR2_Full);
0590 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_20GB)
0591 ethtool_link_ksettings_add_link_mode(ks, advertising,
0592 20000baseKR2_Full);
0593 }
0594 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4) {
0595 ethtool_link_ksettings_add_link_mode(ks, supported,
0596 10000baseKX4_Full);
0597 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0598 ethtool_link_ksettings_add_link_mode(ks, advertising,
0599 10000baseKX4_Full);
0600 }
0601 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR &&
0602 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
0603 ethtool_link_ksettings_add_link_mode(ks, supported,
0604 10000baseKR_Full);
0605 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0606 ethtool_link_ksettings_add_link_mode(ks, advertising,
0607 10000baseKR_Full);
0608 }
0609 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX &&
0610 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
0611 ethtool_link_ksettings_add_link_mode(ks, supported,
0612 1000baseKX_Full);
0613 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
0614 ethtool_link_ksettings_add_link_mode(ks, advertising,
0615 1000baseKX_Full);
0616 }
0617
0618 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR) {
0619 ethtool_link_ksettings_add_link_mode(ks, supported,
0620 25000baseKR_Full);
0621 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
0622 ethtool_link_ksettings_add_link_mode(ks, advertising,
0623 25000baseKR_Full);
0624 }
0625 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR) {
0626 ethtool_link_ksettings_add_link_mode(ks, supported,
0627 25000baseCR_Full);
0628 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
0629 ethtool_link_ksettings_add_link_mode(ks, advertising,
0630 25000baseCR_Full);
0631 }
0632 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
0633 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR) {
0634 ethtool_link_ksettings_add_link_mode(ks, supported,
0635 25000baseSR_Full);
0636 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
0637 ethtool_link_ksettings_add_link_mode(ks, advertising,
0638 25000baseSR_Full);
0639 }
0640 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
0641 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
0642 ethtool_link_ksettings_add_link_mode(ks, supported,
0643 25000baseCR_Full);
0644 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
0645 ethtool_link_ksettings_add_link_mode(ks, advertising,
0646 25000baseCR_Full);
0647 }
0648 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
0649 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
0650 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
0651 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
0652 phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
0653 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
0654 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
0655 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
0656 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
0657 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB) {
0658 ethtool_link_ksettings_add_link_mode(ks, advertising,
0659 FEC_NONE);
0660 ethtool_link_ksettings_add_link_mode(ks, advertising,
0661 FEC_RS);
0662 ethtool_link_ksettings_add_link_mode(ks, advertising,
0663 FEC_BASER);
0664 }
0665 }
0666
0667 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
0668 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU) {
0669 ethtool_link_ksettings_add_link_mode(ks, supported,
0670 10000baseCR_Full);
0671 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0672 ethtool_link_ksettings_add_link_mode(ks, advertising,
0673 10000baseCR_Full);
0674 }
0675 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR) {
0676 ethtool_link_ksettings_add_link_mode(ks, supported,
0677 10000baseSR_Full);
0678 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0679 ethtool_link_ksettings_add_link_mode(ks, advertising,
0680 10000baseSR_Full);
0681 }
0682 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR) {
0683 ethtool_link_ksettings_add_link_mode(ks, supported,
0684 10000baseLR_Full);
0685 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0686 ethtool_link_ksettings_add_link_mode(ks, advertising,
0687 10000baseLR_Full);
0688 }
0689 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
0690 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
0691 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL) {
0692 ethtool_link_ksettings_add_link_mode(ks, supported,
0693 1000baseX_Full);
0694 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
0695 ethtool_link_ksettings_add_link_mode(ks, advertising,
0696 1000baseX_Full);
0697 }
0698
0699 if (phy_types & I40E_CAP_PHY_TYPE_SGMII ||
0700 phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4 ||
0701 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
0702 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4 ||
0703 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
0704 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
0705 phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
0706 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
0707 phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2 ||
0708 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR ||
0709 phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR ||
0710 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4 ||
0711 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR ||
0712 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU ||
0713 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
0714 phy_types & I40E_CAP_PHY_TYPE_10GBASE_T ||
0715 phy_types & I40E_CAP_PHY_TYPE_5GBASE_T ||
0716 phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T ||
0717 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL ||
0718 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T ||
0719 phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
0720 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
0721 phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX ||
0722 phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
0723 ethtool_link_ksettings_add_link_mode(ks, supported,
0724 Autoneg);
0725 ethtool_link_ksettings_add_link_mode(ks, advertising,
0726 Autoneg);
0727 }
0728 }
0729
0730
0731
0732
0733
0734
0735 static void i40e_get_settings_link_up_fec(u8 req_fec_info,
0736 struct ethtool_link_ksettings *ks)
0737 {
0738 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
0739 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
0740 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
0741
0742 if ((I40E_AQ_SET_FEC_REQUEST_RS & req_fec_info) &&
0743 (I40E_AQ_SET_FEC_REQUEST_KR & req_fec_info)) {
0744 ethtool_link_ksettings_add_link_mode(ks, advertising,
0745 FEC_NONE);
0746 ethtool_link_ksettings_add_link_mode(ks, advertising,
0747 FEC_BASER);
0748 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
0749 } else if (I40E_AQ_SET_FEC_REQUEST_RS & req_fec_info) {
0750 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
0751 } else if (I40E_AQ_SET_FEC_REQUEST_KR & req_fec_info) {
0752 ethtool_link_ksettings_add_link_mode(ks, advertising,
0753 FEC_BASER);
0754 } else {
0755 ethtool_link_ksettings_add_link_mode(ks, advertising,
0756 FEC_NONE);
0757 }
0758 }
0759
0760
0761
0762
0763
0764
0765
0766
0767 static void i40e_get_settings_link_up(struct i40e_hw *hw,
0768 struct ethtool_link_ksettings *ks,
0769 struct net_device *netdev,
0770 struct i40e_pf *pf)
0771 {
0772 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
0773 struct ethtool_link_ksettings cap_ksettings;
0774 u32 link_speed = hw_link_info->link_speed;
0775
0776
0777 switch (hw_link_info->phy_type) {
0778 case I40E_PHY_TYPE_40GBASE_CR4:
0779 case I40E_PHY_TYPE_40GBASE_CR4_CU:
0780 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0781 ethtool_link_ksettings_add_link_mode(ks, supported,
0782 40000baseCR4_Full);
0783 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0784 ethtool_link_ksettings_add_link_mode(ks, advertising,
0785 40000baseCR4_Full);
0786 break;
0787 case I40E_PHY_TYPE_XLAUI:
0788 case I40E_PHY_TYPE_XLPPI:
0789 case I40E_PHY_TYPE_40GBASE_AOC:
0790 ethtool_link_ksettings_add_link_mode(ks, supported,
0791 40000baseCR4_Full);
0792 ethtool_link_ksettings_add_link_mode(ks, advertising,
0793 40000baseCR4_Full);
0794 break;
0795 case I40E_PHY_TYPE_40GBASE_SR4:
0796 ethtool_link_ksettings_add_link_mode(ks, supported,
0797 40000baseSR4_Full);
0798 ethtool_link_ksettings_add_link_mode(ks, advertising,
0799 40000baseSR4_Full);
0800 break;
0801 case I40E_PHY_TYPE_40GBASE_LR4:
0802 ethtool_link_ksettings_add_link_mode(ks, supported,
0803 40000baseLR4_Full);
0804 ethtool_link_ksettings_add_link_mode(ks, advertising,
0805 40000baseLR4_Full);
0806 break;
0807 case I40E_PHY_TYPE_25GBASE_SR:
0808 case I40E_PHY_TYPE_25GBASE_LR:
0809 case I40E_PHY_TYPE_10GBASE_SR:
0810 case I40E_PHY_TYPE_10GBASE_LR:
0811 case I40E_PHY_TYPE_1000BASE_SX:
0812 case I40E_PHY_TYPE_1000BASE_LX:
0813 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0814 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0815 ethtool_link_ksettings_add_link_mode(ks, supported,
0816 25000baseSR_Full);
0817 ethtool_link_ksettings_add_link_mode(ks, advertising,
0818 25000baseSR_Full);
0819 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
0820 ethtool_link_ksettings_add_link_mode(ks, supported,
0821 10000baseSR_Full);
0822 ethtool_link_ksettings_add_link_mode(ks, advertising,
0823 10000baseSR_Full);
0824 ethtool_link_ksettings_add_link_mode(ks, supported,
0825 10000baseLR_Full);
0826 ethtool_link_ksettings_add_link_mode(ks, advertising,
0827 10000baseLR_Full);
0828 ethtool_link_ksettings_add_link_mode(ks, supported,
0829 1000baseX_Full);
0830 ethtool_link_ksettings_add_link_mode(ks, advertising,
0831 1000baseX_Full);
0832 ethtool_link_ksettings_add_link_mode(ks, supported,
0833 10000baseT_Full);
0834 if (hw_link_info->module_type[2] &
0835 I40E_MODULE_TYPE_1000BASE_SX ||
0836 hw_link_info->module_type[2] &
0837 I40E_MODULE_TYPE_1000BASE_LX) {
0838 ethtool_link_ksettings_add_link_mode(ks, supported,
0839 1000baseT_Full);
0840 if (hw_link_info->requested_speeds &
0841 I40E_LINK_SPEED_1GB)
0842 ethtool_link_ksettings_add_link_mode(
0843 ks, advertising, 1000baseT_Full);
0844 }
0845 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0846 ethtool_link_ksettings_add_link_mode(ks, advertising,
0847 10000baseT_Full);
0848 break;
0849 case I40E_PHY_TYPE_10GBASE_T:
0850 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
0851 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
0852 case I40E_PHY_TYPE_1000BASE_T:
0853 case I40E_PHY_TYPE_100BASE_TX:
0854 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0855 ethtool_link_ksettings_add_link_mode(ks, supported,
0856 10000baseT_Full);
0857 ethtool_link_ksettings_add_link_mode(ks, supported,
0858 5000baseT_Full);
0859 ethtool_link_ksettings_add_link_mode(ks, supported,
0860 2500baseT_Full);
0861 ethtool_link_ksettings_add_link_mode(ks, supported,
0862 1000baseT_Full);
0863 ethtool_link_ksettings_add_link_mode(ks, supported,
0864 100baseT_Full);
0865 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0866 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0867 ethtool_link_ksettings_add_link_mode(ks, advertising,
0868 10000baseT_Full);
0869 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
0870 ethtool_link_ksettings_add_link_mode(ks, advertising,
0871 5000baseT_Full);
0872 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
0873 ethtool_link_ksettings_add_link_mode(ks, advertising,
0874 2500baseT_Full);
0875 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
0876 ethtool_link_ksettings_add_link_mode(ks, advertising,
0877 1000baseT_Full);
0878 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
0879 ethtool_link_ksettings_add_link_mode(ks, advertising,
0880 100baseT_Full);
0881 break;
0882 case I40E_PHY_TYPE_1000BASE_T_OPTICAL:
0883 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0884 ethtool_link_ksettings_add_link_mode(ks, supported,
0885 1000baseT_Full);
0886 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0887 ethtool_link_ksettings_add_link_mode(ks, advertising,
0888 1000baseT_Full);
0889 break;
0890 case I40E_PHY_TYPE_10GBASE_CR1_CU:
0891 case I40E_PHY_TYPE_10GBASE_CR1:
0892 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0893 ethtool_link_ksettings_add_link_mode(ks, supported,
0894 10000baseT_Full);
0895 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0896 ethtool_link_ksettings_add_link_mode(ks, advertising,
0897 10000baseT_Full);
0898 break;
0899 case I40E_PHY_TYPE_XAUI:
0900 case I40E_PHY_TYPE_XFI:
0901 case I40E_PHY_TYPE_SFI:
0902 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
0903 case I40E_PHY_TYPE_10GBASE_AOC:
0904 ethtool_link_ksettings_add_link_mode(ks, supported,
0905 10000baseT_Full);
0906 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
0907 ethtool_link_ksettings_add_link_mode(ks, advertising,
0908 10000baseT_Full);
0909 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
0910 break;
0911 case I40E_PHY_TYPE_SGMII:
0912 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0913 ethtool_link_ksettings_add_link_mode(ks, supported,
0914 1000baseT_Full);
0915 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
0916 ethtool_link_ksettings_add_link_mode(ks, advertising,
0917 1000baseT_Full);
0918 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
0919 ethtool_link_ksettings_add_link_mode(ks, supported,
0920 100baseT_Full);
0921 if (hw_link_info->requested_speeds &
0922 I40E_LINK_SPEED_100MB)
0923 ethtool_link_ksettings_add_link_mode(
0924 ks, advertising, 100baseT_Full);
0925 }
0926 break;
0927 case I40E_PHY_TYPE_40GBASE_KR4:
0928 case I40E_PHY_TYPE_25GBASE_KR:
0929 case I40E_PHY_TYPE_20GBASE_KR2:
0930 case I40E_PHY_TYPE_10GBASE_KR:
0931 case I40E_PHY_TYPE_10GBASE_KX4:
0932 case I40E_PHY_TYPE_1000BASE_KX:
0933 ethtool_link_ksettings_add_link_mode(ks, supported,
0934 40000baseKR4_Full);
0935 ethtool_link_ksettings_add_link_mode(ks, supported,
0936 25000baseKR_Full);
0937 ethtool_link_ksettings_add_link_mode(ks, supported,
0938 20000baseKR2_Full);
0939 ethtool_link_ksettings_add_link_mode(ks, supported,
0940 10000baseKR_Full);
0941 ethtool_link_ksettings_add_link_mode(ks, supported,
0942 10000baseKX4_Full);
0943 ethtool_link_ksettings_add_link_mode(ks, supported,
0944 1000baseKX_Full);
0945 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0946 ethtool_link_ksettings_add_link_mode(ks, advertising,
0947 40000baseKR4_Full);
0948 ethtool_link_ksettings_add_link_mode(ks, advertising,
0949 25000baseKR_Full);
0950 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
0951 ethtool_link_ksettings_add_link_mode(ks, advertising,
0952 20000baseKR2_Full);
0953 ethtool_link_ksettings_add_link_mode(ks, advertising,
0954 10000baseKR_Full);
0955 ethtool_link_ksettings_add_link_mode(ks, advertising,
0956 10000baseKX4_Full);
0957 ethtool_link_ksettings_add_link_mode(ks, advertising,
0958 1000baseKX_Full);
0959 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0960 break;
0961 case I40E_PHY_TYPE_25GBASE_CR:
0962 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0963 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0964 ethtool_link_ksettings_add_link_mode(ks, supported,
0965 25000baseCR_Full);
0966 ethtool_link_ksettings_add_link_mode(ks, advertising,
0967 25000baseCR_Full);
0968 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
0969
0970 break;
0971 case I40E_PHY_TYPE_25GBASE_AOC:
0972 case I40E_PHY_TYPE_25GBASE_ACC:
0973 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
0974 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
0975 ethtool_link_ksettings_add_link_mode(ks, supported,
0976 25000baseCR_Full);
0977 ethtool_link_ksettings_add_link_mode(ks, advertising,
0978 25000baseCR_Full);
0979 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
0980
0981 ethtool_link_ksettings_add_link_mode(ks, supported,
0982 10000baseCR_Full);
0983 ethtool_link_ksettings_add_link_mode(ks, advertising,
0984 10000baseCR_Full);
0985 break;
0986 default:
0987
0988 netdev_info(netdev,
0989 "WARNING: Link is up but PHY type 0x%x is not recognized, or incorrect cable is in use\n",
0990 hw_link_info->phy_type);
0991 }
0992
0993
0994
0995
0996
0997 memset(&cap_ksettings, 0, sizeof(struct ethtool_link_ksettings));
0998 i40e_phy_type_to_ethtool(pf, &cap_ksettings);
0999 ethtool_intersect_link_masks(ks, &cap_ksettings);
1000
1001
1002 switch (link_speed) {
1003 case I40E_LINK_SPEED_40GB:
1004 ks->base.speed = SPEED_40000;
1005 break;
1006 case I40E_LINK_SPEED_25GB:
1007 ks->base.speed = SPEED_25000;
1008 break;
1009 case I40E_LINK_SPEED_20GB:
1010 ks->base.speed = SPEED_20000;
1011 break;
1012 case I40E_LINK_SPEED_10GB:
1013 ks->base.speed = SPEED_10000;
1014 break;
1015 case I40E_LINK_SPEED_5GB:
1016 ks->base.speed = SPEED_5000;
1017 break;
1018 case I40E_LINK_SPEED_2_5GB:
1019 ks->base.speed = SPEED_2500;
1020 break;
1021 case I40E_LINK_SPEED_1GB:
1022 ks->base.speed = SPEED_1000;
1023 break;
1024 case I40E_LINK_SPEED_100MB:
1025 ks->base.speed = SPEED_100;
1026 break;
1027 default:
1028 ks->base.speed = SPEED_UNKNOWN;
1029 break;
1030 }
1031 ks->base.duplex = DUPLEX_FULL;
1032 }
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042 static void i40e_get_settings_link_down(struct i40e_hw *hw,
1043 struct ethtool_link_ksettings *ks,
1044 struct i40e_pf *pf)
1045 {
1046
1047
1048
1049 i40e_phy_type_to_ethtool(pf, ks);
1050
1051
1052 ks->base.speed = SPEED_UNKNOWN;
1053 ks->base.duplex = DUPLEX_UNKNOWN;
1054 }
1055
1056
1057
1058
1059
1060
1061
1062
1063 static int i40e_get_link_ksettings(struct net_device *netdev,
1064 struct ethtool_link_ksettings *ks)
1065 {
1066 struct i40e_netdev_priv *np = netdev_priv(netdev);
1067 struct i40e_pf *pf = np->vsi->back;
1068 struct i40e_hw *hw = &pf->hw;
1069 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1070 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1071
1072 ethtool_link_ksettings_zero_link_mode(ks, supported);
1073 ethtool_link_ksettings_zero_link_mode(ks, advertising);
1074
1075 if (link_up)
1076 i40e_get_settings_link_up(hw, ks, netdev, pf);
1077 else
1078 i40e_get_settings_link_down(hw, ks, pf);
1079
1080
1081
1082 ks->base.autoneg = ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1083 AUTONEG_ENABLE : AUTONEG_DISABLE);
1084
1085
1086 switch (hw->phy.media_type) {
1087 case I40E_MEDIA_TYPE_BACKPLANE:
1088 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
1089 ethtool_link_ksettings_add_link_mode(ks, supported, Backplane);
1090 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
1091 ethtool_link_ksettings_add_link_mode(ks, advertising,
1092 Backplane);
1093 ks->base.port = PORT_NONE;
1094 break;
1095 case I40E_MEDIA_TYPE_BASET:
1096 ethtool_link_ksettings_add_link_mode(ks, supported, TP);
1097 ethtool_link_ksettings_add_link_mode(ks, advertising, TP);
1098 ks->base.port = PORT_TP;
1099 break;
1100 case I40E_MEDIA_TYPE_DA:
1101 case I40E_MEDIA_TYPE_CX4:
1102 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1103 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1104 ks->base.port = PORT_DA;
1105 break;
1106 case I40E_MEDIA_TYPE_FIBER:
1107 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1108 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1109 ks->base.port = PORT_FIBRE;
1110 break;
1111 case I40E_MEDIA_TYPE_UNKNOWN:
1112 default:
1113 ks->base.port = PORT_OTHER;
1114 break;
1115 }
1116
1117
1118 ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
1119 ethtool_link_ksettings_add_link_mode(ks, supported, Asym_Pause);
1120
1121 switch (hw->fc.requested_mode) {
1122 case I40E_FC_FULL:
1123 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1124 break;
1125 case I40E_FC_TX_PAUSE:
1126 ethtool_link_ksettings_add_link_mode(ks, advertising,
1127 Asym_Pause);
1128 break;
1129 case I40E_FC_RX_PAUSE:
1130 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1131 ethtool_link_ksettings_add_link_mode(ks, advertising,
1132 Asym_Pause);
1133 break;
1134 default:
1135 ethtool_link_ksettings_del_link_mode(ks, advertising, Pause);
1136 ethtool_link_ksettings_del_link_mode(ks, advertising,
1137 Asym_Pause);
1138 break;
1139 }
1140
1141 return 0;
1142 }
1143
1144 #define I40E_LBIT_SIZE 8
1145
1146
1147
1148
1149
1150
1151
1152 static enum i40e_aq_link_speed
1153 i40e_speed_to_link_speed(__u32 speed, const struct ethtool_link_ksettings *ks)
1154 {
1155 enum i40e_aq_link_speed link_speed = I40E_LINK_SPEED_UNKNOWN;
1156 bool speed_changed = false;
1157 int i, j;
1158
1159 static const struct {
1160 __u32 speed;
1161 enum i40e_aq_link_speed link_speed;
1162 __u8 bit[I40E_LBIT_SIZE];
1163 } i40e_speed_lut[] = {
1164 #define I40E_LBIT(mode) ETHTOOL_LINK_MODE_ ## mode ##_Full_BIT
1165 {SPEED_100, I40E_LINK_SPEED_100MB, {I40E_LBIT(100baseT)} },
1166 {SPEED_1000, I40E_LINK_SPEED_1GB,
1167 {I40E_LBIT(1000baseT), I40E_LBIT(1000baseX),
1168 I40E_LBIT(1000baseKX)} },
1169 {SPEED_10000, I40E_LINK_SPEED_10GB,
1170 {I40E_LBIT(10000baseT), I40E_LBIT(10000baseKR),
1171 I40E_LBIT(10000baseLR), I40E_LBIT(10000baseCR),
1172 I40E_LBIT(10000baseSR), I40E_LBIT(10000baseKX4)} },
1173
1174 {SPEED_25000, I40E_LINK_SPEED_25GB,
1175 {I40E_LBIT(25000baseCR), I40E_LBIT(25000baseKR),
1176 I40E_LBIT(25000baseSR)} },
1177 {SPEED_40000, I40E_LINK_SPEED_40GB,
1178 {I40E_LBIT(40000baseKR4), I40E_LBIT(40000baseCR4),
1179 I40E_LBIT(40000baseSR4), I40E_LBIT(40000baseLR4)} },
1180 {SPEED_20000, I40E_LINK_SPEED_20GB,
1181 {I40E_LBIT(20000baseKR2)} },
1182 {SPEED_2500, I40E_LINK_SPEED_2_5GB, {I40E_LBIT(2500baseT)} },
1183 {SPEED_5000, I40E_LINK_SPEED_5GB, {I40E_LBIT(2500baseT)} }
1184 #undef I40E_LBIT
1185 };
1186
1187 for (i = 0; i < ARRAY_SIZE(i40e_speed_lut); i++) {
1188 if (i40e_speed_lut[i].speed == speed) {
1189 for (j = 0; j < I40E_LBIT_SIZE; j++) {
1190 if (test_bit(i40e_speed_lut[i].bit[j],
1191 ks->link_modes.supported)) {
1192 speed_changed = true;
1193 break;
1194 }
1195 if (!i40e_speed_lut[i].bit[j])
1196 break;
1197 }
1198 if (speed_changed) {
1199 link_speed = i40e_speed_lut[i].link_speed;
1200 break;
1201 }
1202 }
1203 }
1204 return link_speed;
1205 }
1206
1207 #undef I40E_LBIT_SIZE
1208
1209
1210
1211
1212
1213
1214
1215
1216 static int i40e_set_link_ksettings(struct net_device *netdev,
1217 const struct ethtool_link_ksettings *ks)
1218 {
1219 struct i40e_netdev_priv *np = netdev_priv(netdev);
1220 struct i40e_aq_get_phy_abilities_resp abilities;
1221 struct ethtool_link_ksettings safe_ks;
1222 struct ethtool_link_ksettings copy_ks;
1223 struct i40e_aq_set_phy_config config;
1224 struct i40e_pf *pf = np->vsi->back;
1225 enum i40e_aq_link_speed link_speed;
1226 struct i40e_vsi *vsi = np->vsi;
1227 struct i40e_hw *hw = &pf->hw;
1228 bool autoneg_changed = false;
1229 i40e_status status = 0;
1230 int timeout = 50;
1231 int err = 0;
1232 __u32 speed;
1233 u8 autoneg;
1234
1235
1236
1237
1238 if (hw->partition_id != 1) {
1239 i40e_partition_setting_complaint(pf);
1240 return -EOPNOTSUPP;
1241 }
1242 if (vsi != pf->vsi[pf->lan_vsi])
1243 return -EOPNOTSUPP;
1244 if (hw->phy.media_type != I40E_MEDIA_TYPE_BASET &&
1245 hw->phy.media_type != I40E_MEDIA_TYPE_FIBER &&
1246 hw->phy.media_type != I40E_MEDIA_TYPE_BACKPLANE &&
1247 hw->phy.media_type != I40E_MEDIA_TYPE_DA &&
1248 hw->phy.link_info.link_info & I40E_AQ_LINK_UP)
1249 return -EOPNOTSUPP;
1250 if (hw->device_id == I40E_DEV_ID_KX_B ||
1251 hw->device_id == I40E_DEV_ID_KX_C ||
1252 hw->device_id == I40E_DEV_ID_20G_KR2 ||
1253 hw->device_id == I40E_DEV_ID_20G_KR2_A ||
1254 hw->device_id == I40E_DEV_ID_25G_B ||
1255 hw->device_id == I40E_DEV_ID_KX_X722) {
1256 netdev_info(netdev, "Changing settings is not supported on backplane.\n");
1257 return -EOPNOTSUPP;
1258 }
1259
1260
1261 memcpy(©_ks, ks, sizeof(struct ethtool_link_ksettings));
1262
1263
1264 autoneg = copy_ks.base.autoneg;
1265 speed = copy_ks.base.speed;
1266
1267
1268 memset(&safe_ks, 0, sizeof(struct ethtool_link_ksettings));
1269 safe_ks.base.cmd = copy_ks.base.cmd;
1270 safe_ks.base.link_mode_masks_nwords =
1271 copy_ks.base.link_mode_masks_nwords;
1272 i40e_get_link_ksettings(netdev, &safe_ks);
1273
1274
1275
1276
1277 if (!bitmap_subset(copy_ks.link_modes.advertising,
1278 safe_ks.link_modes.supported,
1279 __ETHTOOL_LINK_MODE_MASK_NBITS))
1280 return -EINVAL;
1281
1282
1283 copy_ks.base.autoneg = safe_ks.base.autoneg;
1284 copy_ks.base.speed = safe_ks.base.speed;
1285
1286
1287
1288
1289 if (memcmp(©_ks.base, &safe_ks.base,
1290 sizeof(struct ethtool_link_settings)))
1291 return -EOPNOTSUPP;
1292
1293 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1294 timeout--;
1295 if (!timeout)
1296 return -EBUSY;
1297 usleep_range(1000, 2000);
1298 }
1299
1300
1301 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1302 NULL);
1303 if (status) {
1304 err = -EAGAIN;
1305 goto done;
1306 }
1307
1308
1309
1310
1311 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1312 config.abilities = abilities.abilities;
1313
1314
1315 if (autoneg == AUTONEG_ENABLE) {
1316
1317 if (!(hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED)) {
1318
1319 if (!ethtool_link_ksettings_test_link_mode(&safe_ks,
1320 supported,
1321 Autoneg)) {
1322 netdev_info(netdev, "Autoneg not supported on this phy\n");
1323 err = -EINVAL;
1324 goto done;
1325 }
1326
1327 config.abilities = abilities.abilities |
1328 I40E_AQ_PHY_ENABLE_AN;
1329 autoneg_changed = true;
1330 }
1331 } else {
1332
1333 if (hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) {
1334
1335
1336
1337 if (ethtool_link_ksettings_test_link_mode(&safe_ks,
1338 supported,
1339 Autoneg) &&
1340 hw->phy.media_type != I40E_MEDIA_TYPE_BASET) {
1341 netdev_info(netdev, "Autoneg cannot be disabled on this phy\n");
1342 err = -EINVAL;
1343 goto done;
1344 }
1345
1346 config.abilities = abilities.abilities &
1347 ~I40E_AQ_PHY_ENABLE_AN;
1348 autoneg_changed = true;
1349 }
1350 }
1351
1352 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1353 100baseT_Full))
1354 config.link_speed |= I40E_LINK_SPEED_100MB;
1355 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1356 1000baseT_Full) ||
1357 ethtool_link_ksettings_test_link_mode(ks, advertising,
1358 1000baseX_Full) ||
1359 ethtool_link_ksettings_test_link_mode(ks, advertising,
1360 1000baseKX_Full))
1361 config.link_speed |= I40E_LINK_SPEED_1GB;
1362 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1363 10000baseT_Full) ||
1364 ethtool_link_ksettings_test_link_mode(ks, advertising,
1365 10000baseKX4_Full) ||
1366 ethtool_link_ksettings_test_link_mode(ks, advertising,
1367 10000baseKR_Full) ||
1368 ethtool_link_ksettings_test_link_mode(ks, advertising,
1369 10000baseCR_Full) ||
1370 ethtool_link_ksettings_test_link_mode(ks, advertising,
1371 10000baseSR_Full) ||
1372 ethtool_link_ksettings_test_link_mode(ks, advertising,
1373 10000baseLR_Full))
1374 config.link_speed |= I40E_LINK_SPEED_10GB;
1375 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1376 2500baseT_Full))
1377 config.link_speed |= I40E_LINK_SPEED_2_5GB;
1378 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1379 5000baseT_Full))
1380 config.link_speed |= I40E_LINK_SPEED_5GB;
1381 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1382 20000baseKR2_Full))
1383 config.link_speed |= I40E_LINK_SPEED_20GB;
1384 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1385 25000baseCR_Full) ||
1386 ethtool_link_ksettings_test_link_mode(ks, advertising,
1387 25000baseKR_Full) ||
1388 ethtool_link_ksettings_test_link_mode(ks, advertising,
1389 25000baseSR_Full))
1390 config.link_speed |= I40E_LINK_SPEED_25GB;
1391 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1392 40000baseKR4_Full) ||
1393 ethtool_link_ksettings_test_link_mode(ks, advertising,
1394 40000baseCR4_Full) ||
1395 ethtool_link_ksettings_test_link_mode(ks, advertising,
1396 40000baseSR4_Full) ||
1397 ethtool_link_ksettings_test_link_mode(ks, advertising,
1398 40000baseLR4_Full))
1399 config.link_speed |= I40E_LINK_SPEED_40GB;
1400
1401
1402 if ((speed != SPEED_UNKNOWN && safe_ks.base.speed != speed) &&
1403 (autoneg == AUTONEG_DISABLE ||
1404 (safe_ks.base.autoneg == AUTONEG_DISABLE && !autoneg_changed))) {
1405 link_speed = i40e_speed_to_link_speed(speed, ks);
1406 if (link_speed == I40E_LINK_SPEED_UNKNOWN) {
1407 netdev_info(netdev, "Given speed is not supported\n");
1408 err = -EOPNOTSUPP;
1409 goto done;
1410 } else {
1411 config.link_speed = link_speed;
1412 }
1413 } else {
1414 if (safe_ks.base.speed != speed) {
1415 netdev_info(netdev,
1416 "Unable to set speed, disable autoneg\n");
1417 err = -EOPNOTSUPP;
1418 goto done;
1419 }
1420 }
1421
1422
1423
1424
1425
1426 if (!config.link_speed)
1427 config.link_speed = abilities.link_speed;
1428 if (autoneg_changed || abilities.link_speed != config.link_speed) {
1429
1430 config.phy_type = abilities.phy_type;
1431 config.phy_type_ext = abilities.phy_type_ext;
1432 config.eee_capability = abilities.eee_capability;
1433 config.eeer = abilities.eeer_val;
1434 config.low_power_ctrl = abilities.d3_lpan;
1435 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1436 I40E_AQ_PHY_FEC_CONFIG_MASK;
1437
1438
1439 hw->phy.link_info.requested_speeds = config.link_speed;
1440
1441 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1442
1443 if (hw->phy.link_info.link_info & I40E_AQ_LINK_UP) {
1444
1445
1446
1447 i40e_print_link_message(vsi, false);
1448 netif_carrier_off(netdev);
1449 netif_tx_stop_all_queues(netdev);
1450 }
1451
1452
1453 status = i40e_aq_set_phy_config(hw, &config, NULL);
1454 if (status) {
1455 netdev_info(netdev,
1456 "Set phy config failed, err %s aq_err %s\n",
1457 i40e_stat_str(hw, status),
1458 i40e_aq_str(hw, hw->aq.asq_last_status));
1459 err = -EAGAIN;
1460 goto done;
1461 }
1462
1463 status = i40e_update_link_info(hw);
1464 if (status)
1465 netdev_dbg(netdev,
1466 "Updating link info failed with err %s aq_err %s\n",
1467 i40e_stat_str(hw, status),
1468 i40e_aq_str(hw, hw->aq.asq_last_status));
1469
1470 } else {
1471 netdev_info(netdev, "Nothing changed, exiting without setting anything.\n");
1472 }
1473
1474 done:
1475 clear_bit(__I40E_CONFIG_BUSY, pf->state);
1476
1477 return err;
1478 }
1479
1480 static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
1481 {
1482 struct i40e_netdev_priv *np = netdev_priv(netdev);
1483 struct i40e_aq_get_phy_abilities_resp abilities;
1484 struct i40e_pf *pf = np->vsi->back;
1485 struct i40e_hw *hw = &pf->hw;
1486 i40e_status status = 0;
1487 u32 flags = 0;
1488 int err = 0;
1489
1490 flags = READ_ONCE(pf->flags);
1491 i40e_set_fec_in_flags(fec_cfg, &flags);
1492
1493
1494 memset(&abilities, 0, sizeof(abilities));
1495 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1496 NULL);
1497 if (status) {
1498 err = -EAGAIN;
1499 goto done;
1500 }
1501
1502 if (abilities.fec_cfg_curr_mod_ext_info != fec_cfg) {
1503 struct i40e_aq_set_phy_config config;
1504
1505 memset(&config, 0, sizeof(config));
1506 config.phy_type = abilities.phy_type;
1507 config.abilities = abilities.abilities |
1508 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1509 config.phy_type_ext = abilities.phy_type_ext;
1510 config.link_speed = abilities.link_speed;
1511 config.eee_capability = abilities.eee_capability;
1512 config.eeer = abilities.eeer_val;
1513 config.low_power_ctrl = abilities.d3_lpan;
1514 config.fec_config = fec_cfg & I40E_AQ_PHY_FEC_CONFIG_MASK;
1515 status = i40e_aq_set_phy_config(hw, &config, NULL);
1516 if (status) {
1517 netdev_info(netdev,
1518 "Set phy config failed, err %s aq_err %s\n",
1519 i40e_stat_str(hw, status),
1520 i40e_aq_str(hw, hw->aq.asq_last_status));
1521 err = -EAGAIN;
1522 goto done;
1523 }
1524 pf->flags = flags;
1525 status = i40e_update_link_info(hw);
1526 if (status)
1527
1528
1529
1530
1531 netdev_dbg(netdev,
1532 "Updating link info failed with err %s aq_err %s\n",
1533 i40e_stat_str(hw, status),
1534 i40e_aq_str(hw, hw->aq.asq_last_status));
1535 }
1536
1537 done:
1538 return err;
1539 }
1540
1541 static int i40e_get_fec_param(struct net_device *netdev,
1542 struct ethtool_fecparam *fecparam)
1543 {
1544 struct i40e_netdev_priv *np = netdev_priv(netdev);
1545 struct i40e_aq_get_phy_abilities_resp abilities;
1546 struct i40e_pf *pf = np->vsi->back;
1547 struct i40e_hw *hw = &pf->hw;
1548 i40e_status status = 0;
1549 int err = 0;
1550 u8 fec_cfg;
1551
1552
1553 memset(&abilities, 0, sizeof(abilities));
1554 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1555 NULL);
1556 if (status) {
1557 err = -EAGAIN;
1558 goto done;
1559 }
1560
1561 fecparam->fec = 0;
1562 fec_cfg = abilities.fec_cfg_curr_mod_ext_info;
1563 if (fec_cfg & I40E_AQ_SET_FEC_AUTO)
1564 fecparam->fec |= ETHTOOL_FEC_AUTO;
1565 else if (fec_cfg & (I40E_AQ_SET_FEC_REQUEST_RS |
1566 I40E_AQ_SET_FEC_ABILITY_RS))
1567 fecparam->fec |= ETHTOOL_FEC_RS;
1568 else if (fec_cfg & (I40E_AQ_SET_FEC_REQUEST_KR |
1569 I40E_AQ_SET_FEC_ABILITY_KR))
1570 fecparam->fec |= ETHTOOL_FEC_BASER;
1571 if (fec_cfg == 0)
1572 fecparam->fec |= ETHTOOL_FEC_OFF;
1573
1574 if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA)
1575 fecparam->active_fec = ETHTOOL_FEC_BASER;
1576 else if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA)
1577 fecparam->active_fec = ETHTOOL_FEC_RS;
1578 else
1579 fecparam->active_fec = ETHTOOL_FEC_OFF;
1580 done:
1581 return err;
1582 }
1583
1584 static int i40e_set_fec_param(struct net_device *netdev,
1585 struct ethtool_fecparam *fecparam)
1586 {
1587 struct i40e_netdev_priv *np = netdev_priv(netdev);
1588 struct i40e_pf *pf = np->vsi->back;
1589 struct i40e_hw *hw = &pf->hw;
1590 u8 fec_cfg = 0;
1591
1592 if (hw->device_id != I40E_DEV_ID_25G_SFP28 &&
1593 hw->device_id != I40E_DEV_ID_25G_B &&
1594 hw->device_id != I40E_DEV_ID_KX_X722)
1595 return -EPERM;
1596
1597 if (hw->mac.type == I40E_MAC_X722 &&
1598 !(hw->flags & I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE)) {
1599 netdev_err(netdev, "Setting FEC encoding not supported by firmware. Please update the NVM image.\n");
1600 return -EOPNOTSUPP;
1601 }
1602
1603 switch (fecparam->fec) {
1604 case ETHTOOL_FEC_AUTO:
1605 fec_cfg = I40E_AQ_SET_FEC_AUTO;
1606 break;
1607 case ETHTOOL_FEC_RS:
1608 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
1609 I40E_AQ_SET_FEC_ABILITY_RS);
1610 break;
1611 case ETHTOOL_FEC_BASER:
1612 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
1613 I40E_AQ_SET_FEC_ABILITY_KR);
1614 break;
1615 case ETHTOOL_FEC_OFF:
1616 case ETHTOOL_FEC_NONE:
1617 fec_cfg = 0;
1618 break;
1619 default:
1620 dev_warn(&pf->pdev->dev, "Unsupported FEC mode: %d",
1621 fecparam->fec);
1622 return -EINVAL;
1623 }
1624
1625 return i40e_set_fec_cfg(netdev, fec_cfg);
1626 }
1627
1628 static int i40e_nway_reset(struct net_device *netdev)
1629 {
1630
1631 struct i40e_netdev_priv *np = netdev_priv(netdev);
1632 struct i40e_pf *pf = np->vsi->back;
1633 struct i40e_hw *hw = &pf->hw;
1634 bool link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1635 i40e_status ret = 0;
1636
1637 ret = i40e_aq_set_link_restart_an(hw, link_up, NULL);
1638 if (ret) {
1639 netdev_info(netdev, "link restart failed, err %s aq_err %s\n",
1640 i40e_stat_str(hw, ret),
1641 i40e_aq_str(hw, hw->aq.asq_last_status));
1642 return -EIO;
1643 }
1644
1645 return 0;
1646 }
1647
1648
1649
1650
1651
1652
1653
1654
1655 static void i40e_get_pauseparam(struct net_device *netdev,
1656 struct ethtool_pauseparam *pause)
1657 {
1658 struct i40e_netdev_priv *np = netdev_priv(netdev);
1659 struct i40e_pf *pf = np->vsi->back;
1660 struct i40e_hw *hw = &pf->hw;
1661 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1662 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1663
1664 pause->autoneg =
1665 ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1666 AUTONEG_ENABLE : AUTONEG_DISABLE);
1667
1668
1669 if (dcbx_cfg->pfc.pfcenable) {
1670 pause->rx_pause = 0;
1671 pause->tx_pause = 0;
1672 return;
1673 }
1674
1675 if (hw->fc.current_mode == I40E_FC_RX_PAUSE) {
1676 pause->rx_pause = 1;
1677 } else if (hw->fc.current_mode == I40E_FC_TX_PAUSE) {
1678 pause->tx_pause = 1;
1679 } else if (hw->fc.current_mode == I40E_FC_FULL) {
1680 pause->rx_pause = 1;
1681 pause->tx_pause = 1;
1682 }
1683 }
1684
1685
1686
1687
1688
1689
1690 static int i40e_set_pauseparam(struct net_device *netdev,
1691 struct ethtool_pauseparam *pause)
1692 {
1693 struct i40e_netdev_priv *np = netdev_priv(netdev);
1694 struct i40e_pf *pf = np->vsi->back;
1695 struct i40e_vsi *vsi = np->vsi;
1696 struct i40e_hw *hw = &pf->hw;
1697 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1698 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1699 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1700 i40e_status status;
1701 u8 aq_failures;
1702 int err = 0;
1703 u32 is_an;
1704
1705
1706
1707
1708 if (hw->partition_id != 1) {
1709 i40e_partition_setting_complaint(pf);
1710 return -EOPNOTSUPP;
1711 }
1712
1713 if (vsi != pf->vsi[pf->lan_vsi])
1714 return -EOPNOTSUPP;
1715
1716 is_an = hw_link_info->an_info & I40E_AQ_AN_COMPLETED;
1717 if (pause->autoneg != is_an) {
1718 netdev_info(netdev, "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
1719 return -EOPNOTSUPP;
1720 }
1721
1722
1723 if (!test_bit(__I40E_DOWN, pf->state) && !is_an) {
1724
1725 netdev_info(netdev, "Autoneg did not complete so changing settings may not result in an actual change.\n");
1726 }
1727
1728 if (dcbx_cfg->pfc.pfcenable) {
1729 netdev_info(netdev,
1730 "Priority flow control enabled. Cannot set link flow control.\n");
1731 return -EOPNOTSUPP;
1732 }
1733
1734 if (pause->rx_pause && pause->tx_pause)
1735 hw->fc.requested_mode = I40E_FC_FULL;
1736 else if (pause->rx_pause && !pause->tx_pause)
1737 hw->fc.requested_mode = I40E_FC_RX_PAUSE;
1738 else if (!pause->rx_pause && pause->tx_pause)
1739 hw->fc.requested_mode = I40E_FC_TX_PAUSE;
1740 else if (!pause->rx_pause && !pause->tx_pause)
1741 hw->fc.requested_mode = I40E_FC_NONE;
1742 else
1743 return -EINVAL;
1744
1745
1746
1747
1748 i40e_print_link_message(vsi, false);
1749 netif_carrier_off(netdev);
1750 netif_tx_stop_all_queues(netdev);
1751
1752
1753 status = i40e_set_fc(hw, &aq_failures, link_up);
1754
1755 if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) {
1756 netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %s aq_err %s\n",
1757 i40e_stat_str(hw, status),
1758 i40e_aq_str(hw, hw->aq.asq_last_status));
1759 err = -EAGAIN;
1760 }
1761 if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) {
1762 netdev_info(netdev, "Set fc failed on the set_phy_config call with err %s aq_err %s\n",
1763 i40e_stat_str(hw, status),
1764 i40e_aq_str(hw, hw->aq.asq_last_status));
1765 err = -EAGAIN;
1766 }
1767 if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) {
1768 netdev_info(netdev, "Set fc failed on the get_link_info call with err %s aq_err %s\n",
1769 i40e_stat_str(hw, status),
1770 i40e_aq_str(hw, hw->aq.asq_last_status));
1771 err = -EAGAIN;
1772 }
1773
1774 if (!test_bit(__I40E_DOWN, pf->state) && is_an) {
1775
1776 msleep(75);
1777 if (!test_bit(__I40E_DOWN, pf->state))
1778 return i40e_nway_reset(netdev);
1779 }
1780
1781 return err;
1782 }
1783
1784 static u32 i40e_get_msglevel(struct net_device *netdev)
1785 {
1786 struct i40e_netdev_priv *np = netdev_priv(netdev);
1787 struct i40e_pf *pf = np->vsi->back;
1788 u32 debug_mask = pf->hw.debug_mask;
1789
1790 if (debug_mask)
1791 netdev_info(netdev, "i40e debug_mask: 0x%08X\n", debug_mask);
1792
1793 return pf->msg_enable;
1794 }
1795
1796 static void i40e_set_msglevel(struct net_device *netdev, u32 data)
1797 {
1798 struct i40e_netdev_priv *np = netdev_priv(netdev);
1799 struct i40e_pf *pf = np->vsi->back;
1800
1801 if (I40E_DEBUG_USER & data)
1802 pf->hw.debug_mask = data;
1803 else
1804 pf->msg_enable = data;
1805 }
1806
1807 static int i40e_get_regs_len(struct net_device *netdev)
1808 {
1809 int reg_count = 0;
1810 int i;
1811
1812 for (i = 0; i40e_reg_list[i].offset != 0; i++)
1813 reg_count += i40e_reg_list[i].elements;
1814
1815 return reg_count * sizeof(u32);
1816 }
1817
1818 static void i40e_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
1819 void *p)
1820 {
1821 struct i40e_netdev_priv *np = netdev_priv(netdev);
1822 struct i40e_pf *pf = np->vsi->back;
1823 struct i40e_hw *hw = &pf->hw;
1824 u32 *reg_buf = p;
1825 unsigned int i, j, ri;
1826 u32 reg;
1827
1828
1829
1830
1831
1832
1833
1834
1835 regs->version = 1;
1836
1837
1838 ri = 0;
1839 for (i = 0; i40e_reg_list[i].offset != 0; i++) {
1840 for (j = 0; j < i40e_reg_list[i].elements; j++) {
1841 reg = i40e_reg_list[i].offset
1842 + (j * i40e_reg_list[i].stride);
1843 reg_buf[ri++] = rd32(hw, reg);
1844 }
1845 }
1846
1847 }
1848
1849 static int i40e_get_eeprom(struct net_device *netdev,
1850 struct ethtool_eeprom *eeprom, u8 *bytes)
1851 {
1852 struct i40e_netdev_priv *np = netdev_priv(netdev);
1853 struct i40e_hw *hw = &np->vsi->back->hw;
1854 struct i40e_pf *pf = np->vsi->back;
1855 int ret_val = 0, len, offset;
1856 u8 *eeprom_buff;
1857 u16 i, sectors;
1858 bool last;
1859 u32 magic;
1860
1861 #define I40E_NVM_SECTOR_SIZE 4096
1862 if (eeprom->len == 0)
1863 return -EINVAL;
1864
1865
1866 magic = hw->vendor_id | (hw->device_id << 16);
1867 if (eeprom->magic && eeprom->magic != magic) {
1868 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1869 int errno = 0;
1870
1871
1872 if ((eeprom->magic >> 16) != hw->device_id)
1873 errno = -EINVAL;
1874 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1875 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1876 errno = -EBUSY;
1877 else
1878 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1879
1880 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1881 dev_info(&pf->pdev->dev,
1882 "NVMUpdate read failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1883 ret_val, hw->aq.asq_last_status, errno,
1884 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1885 cmd->offset, cmd->data_size);
1886
1887 return errno;
1888 }
1889
1890
1891 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1892
1893 eeprom_buff = kzalloc(eeprom->len, GFP_KERNEL);
1894 if (!eeprom_buff)
1895 return -ENOMEM;
1896
1897 ret_val = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
1898 if (ret_val) {
1899 dev_info(&pf->pdev->dev,
1900 "Failed Acquiring NVM resource for read err=%d status=0x%x\n",
1901 ret_val, hw->aq.asq_last_status);
1902 goto free_buff;
1903 }
1904
1905 sectors = eeprom->len / I40E_NVM_SECTOR_SIZE;
1906 sectors += (eeprom->len % I40E_NVM_SECTOR_SIZE) ? 1 : 0;
1907 len = I40E_NVM_SECTOR_SIZE;
1908 last = false;
1909 for (i = 0; i < sectors; i++) {
1910 if (i == (sectors - 1)) {
1911 len = eeprom->len - (I40E_NVM_SECTOR_SIZE * i);
1912 last = true;
1913 }
1914 offset = eeprom->offset + (I40E_NVM_SECTOR_SIZE * i),
1915 ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,
1916 (u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),
1917 last, NULL);
1918 if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
1919 dev_info(&pf->pdev->dev,
1920 "read NVM failed, invalid offset 0x%x\n",
1921 offset);
1922 break;
1923 } else if (ret_val &&
1924 hw->aq.asq_last_status == I40E_AQ_RC_EACCES) {
1925 dev_info(&pf->pdev->dev,
1926 "read NVM failed, access, offset 0x%x\n",
1927 offset);
1928 break;
1929 } else if (ret_val) {
1930 dev_info(&pf->pdev->dev,
1931 "read NVM failed offset %d err=%d status=0x%x\n",
1932 offset, ret_val, hw->aq.asq_last_status);
1933 break;
1934 }
1935 }
1936
1937 i40e_release_nvm(hw);
1938 memcpy(bytes, (u8 *)eeprom_buff, eeprom->len);
1939 free_buff:
1940 kfree(eeprom_buff);
1941 return ret_val;
1942 }
1943
1944 static int i40e_get_eeprom_len(struct net_device *netdev)
1945 {
1946 struct i40e_netdev_priv *np = netdev_priv(netdev);
1947 struct i40e_hw *hw = &np->vsi->back->hw;
1948 u32 val;
1949
1950 #define X722_EEPROM_SCOPE_LIMIT 0x5B9FFF
1951 if (hw->mac.type == I40E_MAC_X722) {
1952 val = X722_EEPROM_SCOPE_LIMIT + 1;
1953 return val;
1954 }
1955 val = (rd32(hw, I40E_GLPCI_LBARCTRL)
1956 & I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)
1957 >> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;
1958
1959 val = (64 * 1024) * BIT(val);
1960 return val;
1961 }
1962
1963 static int i40e_set_eeprom(struct net_device *netdev,
1964 struct ethtool_eeprom *eeprom, u8 *bytes)
1965 {
1966 struct i40e_netdev_priv *np = netdev_priv(netdev);
1967 struct i40e_hw *hw = &np->vsi->back->hw;
1968 struct i40e_pf *pf = np->vsi->back;
1969 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1970 int ret_val = 0;
1971 int errno = 0;
1972 u32 magic;
1973
1974
1975 magic = hw->vendor_id | (hw->device_id << 16);
1976 if (eeprom->magic == magic)
1977 errno = -EOPNOTSUPP;
1978
1979 else if (!eeprom->magic || (eeprom->magic >> 16) != hw->device_id)
1980 errno = -EINVAL;
1981 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1982 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1983 errno = -EBUSY;
1984 else
1985 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1986
1987 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1988 dev_info(&pf->pdev->dev,
1989 "NVMUpdate write failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1990 ret_val, hw->aq.asq_last_status, errno,
1991 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1992 cmd->offset, cmd->data_size);
1993
1994 return errno;
1995 }
1996
1997 static void i40e_get_drvinfo(struct net_device *netdev,
1998 struct ethtool_drvinfo *drvinfo)
1999 {
2000 struct i40e_netdev_priv *np = netdev_priv(netdev);
2001 struct i40e_vsi *vsi = np->vsi;
2002 struct i40e_pf *pf = vsi->back;
2003
2004 strlcpy(drvinfo->driver, i40e_driver_name, sizeof(drvinfo->driver));
2005 strlcpy(drvinfo->fw_version, i40e_nvm_version_str(&pf->hw),
2006 sizeof(drvinfo->fw_version));
2007 strlcpy(drvinfo->bus_info, pci_name(pf->pdev),
2008 sizeof(drvinfo->bus_info));
2009 drvinfo->n_priv_flags = I40E_PRIV_FLAGS_STR_LEN;
2010 if (pf->hw.pf_id == 0)
2011 drvinfo->n_priv_flags += I40E_GL_PRIV_FLAGS_STR_LEN;
2012 }
2013
2014 static void i40e_get_ringparam(struct net_device *netdev,
2015 struct ethtool_ringparam *ring,
2016 struct kernel_ethtool_ringparam *kernel_ring,
2017 struct netlink_ext_ack *extack)
2018 {
2019 struct i40e_netdev_priv *np = netdev_priv(netdev);
2020 struct i40e_pf *pf = np->vsi->back;
2021 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
2022
2023 ring->rx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
2024 ring->tx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
2025 ring->rx_mini_max_pending = 0;
2026 ring->rx_jumbo_max_pending = 0;
2027 ring->rx_pending = vsi->rx_rings[0]->count;
2028 ring->tx_pending = vsi->tx_rings[0]->count;
2029 ring->rx_mini_pending = 0;
2030 ring->rx_jumbo_pending = 0;
2031 }
2032
2033 static bool i40e_active_tx_ring_index(struct i40e_vsi *vsi, u16 index)
2034 {
2035 if (i40e_enabled_xdp_vsi(vsi)) {
2036 return index < vsi->num_queue_pairs ||
2037 (index >= vsi->alloc_queue_pairs &&
2038 index < vsi->alloc_queue_pairs + vsi->num_queue_pairs);
2039 }
2040
2041 return index < vsi->num_queue_pairs;
2042 }
2043
2044 static int i40e_set_ringparam(struct net_device *netdev,
2045 struct ethtool_ringparam *ring,
2046 struct kernel_ethtool_ringparam *kernel_ring,
2047 struct netlink_ext_ack *extack)
2048 {
2049 struct i40e_ring *tx_rings = NULL, *rx_rings = NULL;
2050 struct i40e_netdev_priv *np = netdev_priv(netdev);
2051 struct i40e_hw *hw = &np->vsi->back->hw;
2052 struct i40e_vsi *vsi = np->vsi;
2053 struct i40e_pf *pf = vsi->back;
2054 u32 new_rx_count, new_tx_count;
2055 u16 tx_alloc_queue_pairs;
2056 int timeout = 50;
2057 int i, err = 0;
2058
2059 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2060 return -EINVAL;
2061
2062 if (ring->tx_pending > I40E_MAX_NUM_DESCRIPTORS ||
2063 ring->tx_pending < I40E_MIN_NUM_DESCRIPTORS ||
2064 ring->rx_pending > I40E_MAX_NUM_DESCRIPTORS ||
2065 ring->rx_pending < I40E_MIN_NUM_DESCRIPTORS) {
2066 netdev_info(netdev,
2067 "Descriptors requested (Tx: %d / Rx: %d) out of range [%d-%d]\n",
2068 ring->tx_pending, ring->rx_pending,
2069 I40E_MIN_NUM_DESCRIPTORS, I40E_MAX_NUM_DESCRIPTORS);
2070 return -EINVAL;
2071 }
2072
2073 new_tx_count = ALIGN(ring->tx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
2074 new_rx_count = ALIGN(ring->rx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
2075
2076
2077 if ((new_tx_count == vsi->tx_rings[0]->count) &&
2078 (new_rx_count == vsi->rx_rings[0]->count))
2079 return 0;
2080
2081
2082
2083
2084
2085 if (i40e_xsk_any_rx_ring_enabled(vsi))
2086 return -EBUSY;
2087
2088 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
2089 timeout--;
2090 if (!timeout)
2091 return -EBUSY;
2092 usleep_range(1000, 2000);
2093 }
2094
2095 if (!netif_running(vsi->netdev)) {
2096
2097 for (i = 0; i < vsi->num_queue_pairs; i++) {
2098 vsi->tx_rings[i]->count = new_tx_count;
2099 vsi->rx_rings[i]->count = new_rx_count;
2100 if (i40e_enabled_xdp_vsi(vsi))
2101 vsi->xdp_rings[i]->count = new_tx_count;
2102 }
2103 vsi->num_tx_desc = new_tx_count;
2104 vsi->num_rx_desc = new_rx_count;
2105 goto done;
2106 }
2107
2108
2109
2110
2111
2112
2113
2114 tx_alloc_queue_pairs = vsi->alloc_queue_pairs *
2115 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
2116 if (new_tx_count != vsi->tx_rings[0]->count) {
2117 netdev_info(netdev,
2118 "Changing Tx descriptor count from %d to %d.\n",
2119 vsi->tx_rings[0]->count, new_tx_count);
2120 tx_rings = kcalloc(tx_alloc_queue_pairs,
2121 sizeof(struct i40e_ring), GFP_KERNEL);
2122 if (!tx_rings) {
2123 err = -ENOMEM;
2124 goto done;
2125 }
2126
2127 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2128 if (!i40e_active_tx_ring_index(vsi, i))
2129 continue;
2130
2131 tx_rings[i] = *vsi->tx_rings[i];
2132 tx_rings[i].count = new_tx_count;
2133
2134
2135
2136 tx_rings[i].desc = NULL;
2137 tx_rings[i].rx_bi = NULL;
2138 err = i40e_setup_tx_descriptors(&tx_rings[i]);
2139 if (err) {
2140 while (i) {
2141 i--;
2142 if (!i40e_active_tx_ring_index(vsi, i))
2143 continue;
2144 i40e_free_tx_resources(&tx_rings[i]);
2145 }
2146 kfree(tx_rings);
2147 tx_rings = NULL;
2148
2149 goto done;
2150 }
2151 }
2152 }
2153
2154
2155 if (new_rx_count != vsi->rx_rings[0]->count) {
2156 netdev_info(netdev,
2157 "Changing Rx descriptor count from %d to %d\n",
2158 vsi->rx_rings[0]->count, new_rx_count);
2159 rx_rings = kcalloc(vsi->alloc_queue_pairs,
2160 sizeof(struct i40e_ring), GFP_KERNEL);
2161 if (!rx_rings) {
2162 err = -ENOMEM;
2163 goto free_tx;
2164 }
2165
2166 for (i = 0; i < vsi->num_queue_pairs; i++) {
2167 u16 unused;
2168
2169
2170 rx_rings[i] = *vsi->rx_rings[i];
2171 rx_rings[i].count = new_rx_count;
2172
2173
2174
2175 rx_rings[i].desc = NULL;
2176 rx_rings[i].rx_bi = NULL;
2177
2178 memset(&rx_rings[i].xdp_rxq, 0, sizeof(rx_rings[i].xdp_rxq));
2179
2180
2181
2182 rx_rings[i].tail = hw->hw_addr + I40E_PRTGEN_STATUS;
2183 err = i40e_setup_rx_descriptors(&rx_rings[i]);
2184 if (err)
2185 goto rx_unwind;
2186 err = i40e_alloc_rx_bi(&rx_rings[i]);
2187 if (err)
2188 goto rx_unwind;
2189
2190
2191
2192
2193 unused = I40E_DESC_UNUSED(&rx_rings[i]);
2194 err = i40e_alloc_rx_buffers(&rx_rings[i], unused);
2195 rx_unwind:
2196 if (err) {
2197 do {
2198 i40e_free_rx_resources(&rx_rings[i]);
2199 } while (i--);
2200 kfree(rx_rings);
2201 rx_rings = NULL;
2202
2203 goto free_tx;
2204 }
2205 }
2206 }
2207
2208
2209
2210
2211 i40e_down(vsi);
2212
2213 if (tx_rings) {
2214 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2215 if (i40e_active_tx_ring_index(vsi, i)) {
2216 i40e_free_tx_resources(vsi->tx_rings[i]);
2217 *vsi->tx_rings[i] = tx_rings[i];
2218 }
2219 }
2220 kfree(tx_rings);
2221 tx_rings = NULL;
2222 }
2223
2224 if (rx_rings) {
2225 for (i = 0; i < vsi->num_queue_pairs; i++) {
2226 i40e_free_rx_resources(vsi->rx_rings[i]);
2227
2228 rx_rings[i].tail = vsi->rx_rings[i]->tail;
2229
2230
2231
2232
2233
2234 rx_rings[i].next_to_use = 0;
2235 rx_rings[i].next_to_clean = 0;
2236 rx_rings[i].next_to_alloc = 0;
2237
2238 *vsi->rx_rings[i] = rx_rings[i];
2239 }
2240 kfree(rx_rings);
2241 rx_rings = NULL;
2242 }
2243
2244 vsi->num_tx_desc = new_tx_count;
2245 vsi->num_rx_desc = new_rx_count;
2246 i40e_up(vsi);
2247
2248 free_tx:
2249
2250 if (tx_rings) {
2251 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2252 if (i40e_active_tx_ring_index(vsi, i))
2253 i40e_free_tx_resources(vsi->tx_rings[i]);
2254 }
2255 kfree(tx_rings);
2256 tx_rings = NULL;
2257 }
2258
2259 done:
2260 clear_bit(__I40E_CONFIG_BUSY, pf->state);
2261
2262 return err;
2263 }
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279 static int i40e_get_stats_count(struct net_device *netdev)
2280 {
2281 struct i40e_netdev_priv *np = netdev_priv(netdev);
2282 struct i40e_vsi *vsi = np->vsi;
2283 struct i40e_pf *pf = vsi->back;
2284 int stats_len;
2285
2286 if (vsi == pf->vsi[pf->lan_vsi] && pf->hw.partition_id == 1)
2287 stats_len = I40E_PF_STATS_LEN;
2288 else
2289 stats_len = I40E_VSI_STATS_LEN;
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305 stats_len += I40E_QUEUE_STATS_LEN * 2 * netdev->num_tx_queues;
2306
2307 return stats_len;
2308 }
2309
2310 static int i40e_get_sset_count(struct net_device *netdev, int sset)
2311 {
2312 struct i40e_netdev_priv *np = netdev_priv(netdev);
2313 struct i40e_vsi *vsi = np->vsi;
2314 struct i40e_pf *pf = vsi->back;
2315
2316 switch (sset) {
2317 case ETH_SS_TEST:
2318 return I40E_TEST_LEN;
2319 case ETH_SS_STATS:
2320 return i40e_get_stats_count(netdev);
2321 case ETH_SS_PRIV_FLAGS:
2322 return I40E_PRIV_FLAGS_STR_LEN +
2323 (pf->hw.pf_id == 0 ? I40E_GL_PRIV_FLAGS_STR_LEN : 0);
2324 default:
2325 return -EOPNOTSUPP;
2326 }
2327 }
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339 static struct i40e_cp_veb_tc_stats
2340 i40e_get_veb_tc_stats(struct i40e_veb_tc_stats *tc, unsigned int i)
2341 {
2342 struct i40e_cp_veb_tc_stats veb_tc = {
2343 .tc_rx_packets = tc->tc_rx_packets[i],
2344 .tc_rx_bytes = tc->tc_rx_bytes[i],
2345 .tc_tx_packets = tc->tc_tx_packets[i],
2346 .tc_tx_bytes = tc->tc_tx_bytes[i],
2347 };
2348
2349 return veb_tc;
2350 }
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361 static inline struct i40e_pfc_stats
2362 i40e_get_pfc_stats(struct i40e_pf *pf, unsigned int i)
2363 {
2364 #define I40E_GET_PFC_STAT(stat, priority) \
2365 .stat = pf->stats.stat[priority]
2366
2367 struct i40e_pfc_stats pfc = {
2368 I40E_GET_PFC_STAT(priority_xon_rx, i),
2369 I40E_GET_PFC_STAT(priority_xoff_rx, i),
2370 I40E_GET_PFC_STAT(priority_xon_tx, i),
2371 I40E_GET_PFC_STAT(priority_xoff_tx, i),
2372 I40E_GET_PFC_STAT(priority_xon_2_xoff, i),
2373 };
2374 return pfc;
2375 }
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391 static void i40e_get_ethtool_stats(struct net_device *netdev,
2392 struct ethtool_stats *stats, u64 *data)
2393 {
2394 struct i40e_netdev_priv *np = netdev_priv(netdev);
2395 struct i40e_vsi *vsi = np->vsi;
2396 struct i40e_pf *pf = vsi->back;
2397 struct i40e_veb *veb = NULL;
2398 unsigned int i;
2399 bool veb_stats;
2400 u64 *p = data;
2401
2402 i40e_update_stats(vsi);
2403
2404 i40e_add_ethtool_stats(&data, i40e_get_vsi_stats_struct(vsi),
2405 i40e_gstrings_net_stats);
2406
2407 i40e_add_ethtool_stats(&data, vsi, i40e_gstrings_misc_stats);
2408
2409 rcu_read_lock();
2410 for (i = 0; i < netdev->num_tx_queues; i++) {
2411 i40e_add_queue_stats(&data, READ_ONCE(vsi->tx_rings[i]));
2412 i40e_add_queue_stats(&data, READ_ONCE(vsi->rx_rings[i]));
2413 }
2414 rcu_read_unlock();
2415
2416 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2417 goto check_data_pointer;
2418
2419 veb_stats = ((pf->lan_veb != I40E_NO_VEB) &&
2420 (pf->lan_veb < I40E_MAX_VEB) &&
2421 (pf->flags & I40E_FLAG_VEB_STATS_ENABLED));
2422
2423 if (veb_stats) {
2424 veb = pf->veb[pf->lan_veb];
2425 i40e_update_veb_stats(veb);
2426 }
2427
2428
2429
2430
2431
2432 i40e_add_ethtool_stats(&data, veb_stats ? veb : NULL,
2433 i40e_gstrings_veb_stats);
2434
2435 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2436 if (veb_stats) {
2437 struct i40e_cp_veb_tc_stats veb_tc =
2438 i40e_get_veb_tc_stats(&veb->tc_stats, i);
2439
2440 i40e_add_ethtool_stats(&data, &veb_tc,
2441 i40e_gstrings_veb_tc_stats);
2442 } else {
2443 i40e_add_ethtool_stats(&data, NULL,
2444 i40e_gstrings_veb_tc_stats);
2445 }
2446
2447 i40e_add_ethtool_stats(&data, pf, i40e_gstrings_stats);
2448
2449 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
2450 struct i40e_pfc_stats pfc = i40e_get_pfc_stats(pf, i);
2451
2452 i40e_add_ethtool_stats(&data, &pfc, i40e_gstrings_pfc_stats);
2453 }
2454
2455 check_data_pointer:
2456 WARN_ONCE(data - p != i40e_get_stats_count(netdev),
2457 "ethtool stats count mismatch!");
2458 }
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470 static void i40e_get_stat_strings(struct net_device *netdev, u8 *data)
2471 {
2472 struct i40e_netdev_priv *np = netdev_priv(netdev);
2473 struct i40e_vsi *vsi = np->vsi;
2474 struct i40e_pf *pf = vsi->back;
2475 unsigned int i;
2476 u8 *p = data;
2477
2478 i40e_add_stat_strings(&data, i40e_gstrings_net_stats);
2479
2480 i40e_add_stat_strings(&data, i40e_gstrings_misc_stats);
2481
2482 for (i = 0; i < netdev->num_tx_queues; i++) {
2483 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2484 "tx", i);
2485 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2486 "rx", i);
2487 }
2488
2489 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2490 goto check_data_pointer;
2491
2492 i40e_add_stat_strings(&data, i40e_gstrings_veb_stats);
2493
2494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2495 i40e_add_stat_strings(&data, i40e_gstrings_veb_tc_stats, i);
2496
2497 i40e_add_stat_strings(&data, i40e_gstrings_stats);
2498
2499 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
2500 i40e_add_stat_strings(&data, i40e_gstrings_pfc_stats, i);
2501
2502 check_data_pointer:
2503 WARN_ONCE(data - p != i40e_get_stats_count(netdev) * ETH_GSTRING_LEN,
2504 "stat strings count mismatch!");
2505 }
2506
2507 static void i40e_get_priv_flag_strings(struct net_device *netdev, u8 *data)
2508 {
2509 struct i40e_netdev_priv *np = netdev_priv(netdev);
2510 struct i40e_vsi *vsi = np->vsi;
2511 struct i40e_pf *pf = vsi->back;
2512 unsigned int i;
2513 u8 *p = data;
2514
2515 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++)
2516 ethtool_sprintf(&p, i40e_gstrings_priv_flags[i].flag_string);
2517 if (pf->hw.pf_id != 0)
2518 return;
2519 for (i = 0; i < I40E_GL_PRIV_FLAGS_STR_LEN; i++)
2520 ethtool_sprintf(&p, i40e_gl_gstrings_priv_flags[i].flag_string);
2521 }
2522
2523 static void i40e_get_strings(struct net_device *netdev, u32 stringset,
2524 u8 *data)
2525 {
2526 switch (stringset) {
2527 case ETH_SS_TEST:
2528 memcpy(data, i40e_gstrings_test,
2529 I40E_TEST_LEN * ETH_GSTRING_LEN);
2530 break;
2531 case ETH_SS_STATS:
2532 i40e_get_stat_strings(netdev, data);
2533 break;
2534 case ETH_SS_PRIV_FLAGS:
2535 i40e_get_priv_flag_strings(netdev, data);
2536 break;
2537 default:
2538 break;
2539 }
2540 }
2541
2542 static int i40e_get_ts_info(struct net_device *dev,
2543 struct ethtool_ts_info *info)
2544 {
2545 struct i40e_pf *pf = i40e_netdev_to_pf(dev);
2546
2547
2548 if (!(pf->flags & I40E_FLAG_PTP))
2549 return ethtool_op_get_ts_info(dev, info);
2550
2551 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2552 SOF_TIMESTAMPING_RX_SOFTWARE |
2553 SOF_TIMESTAMPING_SOFTWARE |
2554 SOF_TIMESTAMPING_TX_HARDWARE |
2555 SOF_TIMESTAMPING_RX_HARDWARE |
2556 SOF_TIMESTAMPING_RAW_HARDWARE;
2557
2558 if (pf->ptp_clock)
2559 info->phc_index = ptp_clock_index(pf->ptp_clock);
2560 else
2561 info->phc_index = -1;
2562
2563 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
2564
2565 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
2566 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2567 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2568 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
2569
2570 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE)
2571 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2572 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2573 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
2574 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2575 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
2576 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2577 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2578 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
2579
2580 return 0;
2581 }
2582
2583 static u64 i40e_link_test(struct net_device *netdev, u64 *data)
2584 {
2585 struct i40e_netdev_priv *np = netdev_priv(netdev);
2586 struct i40e_pf *pf = np->vsi->back;
2587 i40e_status status;
2588 bool link_up = false;
2589
2590 netif_info(pf, hw, netdev, "link test\n");
2591 status = i40e_get_link_status(&pf->hw, &link_up);
2592 if (status) {
2593 netif_err(pf, drv, netdev, "link query timed out, please retry test\n");
2594 *data = 1;
2595 return *data;
2596 }
2597
2598 if (link_up)
2599 *data = 0;
2600 else
2601 *data = 1;
2602
2603 return *data;
2604 }
2605
2606 static u64 i40e_reg_test(struct net_device *netdev, u64 *data)
2607 {
2608 struct i40e_netdev_priv *np = netdev_priv(netdev);
2609 struct i40e_pf *pf = np->vsi->back;
2610
2611 netif_info(pf, hw, netdev, "register test\n");
2612 *data = i40e_diag_reg_test(&pf->hw);
2613
2614 return *data;
2615 }
2616
2617 static u64 i40e_eeprom_test(struct net_device *netdev, u64 *data)
2618 {
2619 struct i40e_netdev_priv *np = netdev_priv(netdev);
2620 struct i40e_pf *pf = np->vsi->back;
2621
2622 netif_info(pf, hw, netdev, "eeprom test\n");
2623 *data = i40e_diag_eeprom_test(&pf->hw);
2624
2625
2626 pf->hw.nvmupd_state = I40E_NVMUPD_STATE_INIT;
2627
2628 return *data;
2629 }
2630
2631 static u64 i40e_intr_test(struct net_device *netdev, u64 *data)
2632 {
2633 struct i40e_netdev_priv *np = netdev_priv(netdev);
2634 struct i40e_pf *pf = np->vsi->back;
2635 u16 swc_old = pf->sw_int_count;
2636
2637 netif_info(pf, hw, netdev, "interrupt test\n");
2638 wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
2639 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
2640 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
2641 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
2642 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
2643 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
2644 usleep_range(1000, 2000);
2645 *data = (swc_old == pf->sw_int_count);
2646
2647 return *data;
2648 }
2649
2650 static inline bool i40e_active_vfs(struct i40e_pf *pf)
2651 {
2652 struct i40e_vf *vfs = pf->vf;
2653 int i;
2654
2655 for (i = 0; i < pf->num_alloc_vfs; i++)
2656 if (test_bit(I40E_VF_STATE_ACTIVE, &vfs[i].vf_states))
2657 return true;
2658 return false;
2659 }
2660
2661 static inline bool i40e_active_vmdqs(struct i40e_pf *pf)
2662 {
2663 return !!i40e_find_vsi_by_type(pf, I40E_VSI_VMDQ2);
2664 }
2665
2666 static void i40e_diag_test(struct net_device *netdev,
2667 struct ethtool_test *eth_test, u64 *data)
2668 {
2669 struct i40e_netdev_priv *np = netdev_priv(netdev);
2670 bool if_running = netif_running(netdev);
2671 struct i40e_pf *pf = np->vsi->back;
2672
2673 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2674
2675 netif_info(pf, drv, netdev, "offline testing starting\n");
2676
2677 set_bit(__I40E_TESTING, pf->state);
2678
2679 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
2680 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) {
2681 dev_warn(&pf->pdev->dev,
2682 "Cannot start offline testing when PF is in reset state.\n");
2683 goto skip_ol_tests;
2684 }
2685
2686 if (i40e_active_vfs(pf) || i40e_active_vmdqs(pf)) {
2687 dev_warn(&pf->pdev->dev,
2688 "Please take active VFs and Netqueues offline and restart the adapter before running NIC diagnostics\n");
2689 goto skip_ol_tests;
2690 }
2691
2692
2693 if (if_running)
2694
2695 i40e_close(netdev);
2696 else
2697
2698
2699
2700
2701
2702 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2703
2704 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2705 eth_test->flags |= ETH_TEST_FL_FAILED;
2706
2707 if (i40e_eeprom_test(netdev, &data[I40E_ETH_TEST_EEPROM]))
2708 eth_test->flags |= ETH_TEST_FL_FAILED;
2709
2710 if (i40e_intr_test(netdev, &data[I40E_ETH_TEST_INTR]))
2711 eth_test->flags |= ETH_TEST_FL_FAILED;
2712
2713
2714 if (i40e_reg_test(netdev, &data[I40E_ETH_TEST_REG]))
2715 eth_test->flags |= ETH_TEST_FL_FAILED;
2716
2717 clear_bit(__I40E_TESTING, pf->state);
2718 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2719
2720 if (if_running)
2721 i40e_open(netdev);
2722 } else {
2723
2724 netif_info(pf, drv, netdev, "online testing starting\n");
2725
2726 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2727 eth_test->flags |= ETH_TEST_FL_FAILED;
2728
2729
2730 data[I40E_ETH_TEST_REG] = 0;
2731 data[I40E_ETH_TEST_EEPROM] = 0;
2732 data[I40E_ETH_TEST_INTR] = 0;
2733 }
2734
2735 netif_info(pf, drv, netdev, "testing finished\n");
2736 return;
2737
2738 skip_ol_tests:
2739 data[I40E_ETH_TEST_REG] = 1;
2740 data[I40E_ETH_TEST_EEPROM] = 1;
2741 data[I40E_ETH_TEST_INTR] = 1;
2742 data[I40E_ETH_TEST_LINK] = 1;
2743 eth_test->flags |= ETH_TEST_FL_FAILED;
2744 clear_bit(__I40E_TESTING, pf->state);
2745 netif_info(pf, drv, netdev, "testing failed\n");
2746 }
2747
2748 static void i40e_get_wol(struct net_device *netdev,
2749 struct ethtool_wolinfo *wol)
2750 {
2751 struct i40e_netdev_priv *np = netdev_priv(netdev);
2752 struct i40e_pf *pf = np->vsi->back;
2753 struct i40e_hw *hw = &pf->hw;
2754 u16 wol_nvm_bits;
2755
2756
2757 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2758 if ((BIT(hw->port) & wol_nvm_bits) || (hw->partition_id != 1)) {
2759 wol->supported = 0;
2760 wol->wolopts = 0;
2761 } else {
2762 wol->supported = WAKE_MAGIC;
2763 wol->wolopts = (pf->wol_en ? WAKE_MAGIC : 0);
2764 }
2765 }
2766
2767
2768
2769
2770
2771
2772 static int i40e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2773 {
2774 struct i40e_netdev_priv *np = netdev_priv(netdev);
2775 struct i40e_pf *pf = np->vsi->back;
2776 struct i40e_vsi *vsi = np->vsi;
2777 struct i40e_hw *hw = &pf->hw;
2778 u16 wol_nvm_bits;
2779
2780
2781 if (hw->partition_id != 1) {
2782 i40e_partition_setting_complaint(pf);
2783 return -EOPNOTSUPP;
2784 }
2785
2786 if (vsi != pf->vsi[pf->lan_vsi])
2787 return -EOPNOTSUPP;
2788
2789
2790 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2791 if (BIT(hw->port) & wol_nvm_bits)
2792 return -EOPNOTSUPP;
2793
2794
2795 if (wol->wolopts & ~WAKE_MAGIC)
2796 return -EOPNOTSUPP;
2797
2798
2799 if (pf->wol_en != !!wol->wolopts) {
2800 pf->wol_en = !!wol->wolopts;
2801 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
2802 }
2803
2804 return 0;
2805 }
2806
2807 static int i40e_set_phys_id(struct net_device *netdev,
2808 enum ethtool_phys_id_state state)
2809 {
2810 struct i40e_netdev_priv *np = netdev_priv(netdev);
2811 i40e_status ret = 0;
2812 struct i40e_pf *pf = np->vsi->back;
2813 struct i40e_hw *hw = &pf->hw;
2814 int blink_freq = 2;
2815 u16 temp_status;
2816
2817 switch (state) {
2818 case ETHTOOL_ID_ACTIVE:
2819 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2820 pf->led_status = i40e_led_get(hw);
2821 } else {
2822 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2823 i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL,
2824 NULL);
2825 ret = i40e_led_get_phy(hw, &temp_status,
2826 &pf->phy_led_val);
2827 pf->led_status = temp_status;
2828 }
2829 return blink_freq;
2830 case ETHTOOL_ID_ON:
2831 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2832 i40e_led_set(hw, 0xf, false);
2833 else
2834 ret = i40e_led_set_phy(hw, true, pf->led_status, 0);
2835 break;
2836 case ETHTOOL_ID_OFF:
2837 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2838 i40e_led_set(hw, 0x0, false);
2839 else
2840 ret = i40e_led_set_phy(hw, false, pf->led_status, 0);
2841 break;
2842 case ETHTOOL_ID_INACTIVE:
2843 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2844 i40e_led_set(hw, pf->led_status, false);
2845 } else {
2846 ret = i40e_led_set_phy(hw, false, pf->led_status,
2847 (pf->phy_led_val |
2848 I40E_PHY_LED_MODE_ORIG));
2849 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2850 i40e_aq_set_phy_debug(hw, 0, NULL);
2851 }
2852 break;
2853 default:
2854 break;
2855 }
2856 if (ret)
2857 return -ENOENT;
2858 else
2859 return 0;
2860 }
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877 static int __i40e_get_coalesce(struct net_device *netdev,
2878 struct ethtool_coalesce *ec,
2879 int queue)
2880 {
2881 struct i40e_netdev_priv *np = netdev_priv(netdev);
2882 struct i40e_ring *rx_ring, *tx_ring;
2883 struct i40e_vsi *vsi = np->vsi;
2884
2885 ec->tx_max_coalesced_frames_irq = vsi->work_limit;
2886 ec->rx_max_coalesced_frames_irq = vsi->work_limit;
2887
2888
2889
2890
2891 if (queue < 0)
2892 queue = 0;
2893 else if (queue >= vsi->num_queue_pairs)
2894 return -EINVAL;
2895
2896 rx_ring = vsi->rx_rings[queue];
2897 tx_ring = vsi->tx_rings[queue];
2898
2899 if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
2900 ec->use_adaptive_rx_coalesce = 1;
2901
2902 if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
2903 ec->use_adaptive_tx_coalesce = 1;
2904
2905 ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2906 ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2907
2908
2909
2910
2911
2912
2913
2914 ec->rx_coalesce_usecs_high = vsi->int_rate_limit;
2915 ec->tx_coalesce_usecs_high = vsi->int_rate_limit;
2916
2917 return 0;
2918 }
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931 static int i40e_get_coalesce(struct net_device *netdev,
2932 struct ethtool_coalesce *ec,
2933 struct kernel_ethtool_coalesce *kernel_coal,
2934 struct netlink_ext_ack *extack)
2935 {
2936 return __i40e_get_coalesce(netdev, ec, -1);
2937 }
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947 static int i40e_get_per_queue_coalesce(struct net_device *netdev, u32 queue,
2948 struct ethtool_coalesce *ec)
2949 {
2950 return __i40e_get_coalesce(netdev, ec, queue);
2951 }
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961 static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,
2962 struct ethtool_coalesce *ec,
2963 int queue)
2964 {
2965 struct i40e_ring *rx_ring = vsi->rx_rings[queue];
2966 struct i40e_ring *tx_ring = vsi->tx_rings[queue];
2967 struct i40e_pf *pf = vsi->back;
2968 struct i40e_hw *hw = &pf->hw;
2969 struct i40e_q_vector *q_vector;
2970 u16 intrl;
2971
2972 intrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);
2973
2974 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);
2975 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);
2976
2977 if (ec->use_adaptive_rx_coalesce)
2978 rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2979 else
2980 rx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2981
2982 if (ec->use_adaptive_tx_coalesce)
2983 tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2984 else
2985 tx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2986
2987 q_vector = rx_ring->q_vector;
2988 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting);
2989
2990 q_vector = tx_ring->q_vector;
2991 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting);
2992
2993
2994
2995
2996
2997
2998 wr32(hw, I40E_PFINT_RATEN(q_vector->reg_idx), intrl);
2999 i40e_flush(hw);
3000 }
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010 static int __i40e_set_coalesce(struct net_device *netdev,
3011 struct ethtool_coalesce *ec,
3012 int queue)
3013 {
3014 struct i40e_netdev_priv *np = netdev_priv(netdev);
3015 u16 intrl_reg, cur_rx_itr, cur_tx_itr;
3016 struct i40e_vsi *vsi = np->vsi;
3017 struct i40e_pf *pf = vsi->back;
3018 int i;
3019
3020 if (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)
3021 vsi->work_limit = ec->tx_max_coalesced_frames_irq;
3022
3023 if (queue < 0) {
3024 cur_rx_itr = vsi->rx_rings[0]->itr_setting;
3025 cur_tx_itr = vsi->tx_rings[0]->itr_setting;
3026 } else if (queue < vsi->num_queue_pairs) {
3027 cur_rx_itr = vsi->rx_rings[queue]->itr_setting;
3028 cur_tx_itr = vsi->tx_rings[queue]->itr_setting;
3029 } else {
3030 netif_info(pf, drv, netdev, "Invalid queue value, queue range is 0 - %d\n",
3031 vsi->num_queue_pairs - 1);
3032 return -EINVAL;
3033 }
3034
3035 cur_tx_itr &= ~I40E_ITR_DYNAMIC;
3036 cur_rx_itr &= ~I40E_ITR_DYNAMIC;
3037
3038
3039 if (ec->tx_coalesce_usecs_high != vsi->int_rate_limit) {
3040 netif_info(pf, drv, netdev, "tx-usecs-high is not used, please program rx-usecs-high\n");
3041 return -EINVAL;
3042 }
3043
3044 if (ec->rx_coalesce_usecs_high > INTRL_REG_TO_USEC(I40E_MAX_INTRL)) {
3045 netif_info(pf, drv, netdev, "Invalid value, rx-usecs-high range is 0-%lu\n",
3046 INTRL_REG_TO_USEC(I40E_MAX_INTRL));
3047 return -EINVAL;
3048 }
3049
3050 if (ec->rx_coalesce_usecs != cur_rx_itr &&
3051 ec->use_adaptive_rx_coalesce) {
3052 netif_info(pf, drv, netdev, "RX interrupt moderation cannot be changed if adaptive-rx is enabled.\n");
3053 return -EINVAL;
3054 }
3055
3056 if (ec->rx_coalesce_usecs > I40E_MAX_ITR) {
3057 netif_info(pf, drv, netdev, "Invalid value, rx-usecs range is 0-8160\n");
3058 return -EINVAL;
3059 }
3060
3061 if (ec->tx_coalesce_usecs != cur_tx_itr &&
3062 ec->use_adaptive_tx_coalesce) {
3063 netif_info(pf, drv, netdev, "TX interrupt moderation cannot be changed if adaptive-tx is enabled.\n");
3064 return -EINVAL;
3065 }
3066
3067 if (ec->tx_coalesce_usecs > I40E_MAX_ITR) {
3068 netif_info(pf, drv, netdev, "Invalid value, tx-usecs range is 0-8160\n");
3069 return -EINVAL;
3070 }
3071
3072 if (ec->use_adaptive_rx_coalesce && !cur_rx_itr)
3073 ec->rx_coalesce_usecs = I40E_MIN_ITR;
3074
3075 if (ec->use_adaptive_tx_coalesce && !cur_tx_itr)
3076 ec->tx_coalesce_usecs = I40E_MIN_ITR;
3077
3078 intrl_reg = i40e_intrl_usec_to_reg(ec->rx_coalesce_usecs_high);
3079 vsi->int_rate_limit = INTRL_REG_TO_USEC(intrl_reg);
3080 if (vsi->int_rate_limit != ec->rx_coalesce_usecs_high) {
3081 netif_info(pf, drv, netdev, "Interrupt rate limit rounded down to %d\n",
3082 vsi->int_rate_limit);
3083 }
3084
3085
3086
3087
3088 if (queue < 0) {
3089 for (i = 0; i < vsi->num_queue_pairs; i++)
3090 i40e_set_itr_per_queue(vsi, ec, i);
3091 } else {
3092 i40e_set_itr_per_queue(vsi, ec, queue);
3093 }
3094
3095 return 0;
3096 }
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107 static int i40e_set_coalesce(struct net_device *netdev,
3108 struct ethtool_coalesce *ec,
3109 struct kernel_ethtool_coalesce *kernel_coal,
3110 struct netlink_ext_ack *extack)
3111 {
3112 return __i40e_set_coalesce(netdev, ec, -1);
3113 }
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123 static int i40e_set_per_queue_coalesce(struct net_device *netdev, u32 queue,
3124 struct ethtool_coalesce *ec)
3125 {
3126 return __i40e_set_coalesce(netdev, ec, queue);
3127 }
3128
3129
3130
3131
3132
3133
3134
3135
3136 static int i40e_get_rss_hash_opts(struct i40e_pf *pf, struct ethtool_rxnfc *cmd)
3137 {
3138 struct i40e_hw *hw = &pf->hw;
3139 u8 flow_pctype = 0;
3140 u64 i_set = 0;
3141
3142 cmd->data = 0;
3143
3144 switch (cmd->flow_type) {
3145 case TCP_V4_FLOW:
3146 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3147 break;
3148 case UDP_V4_FLOW:
3149 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3150 break;
3151 case TCP_V6_FLOW:
3152 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3153 break;
3154 case UDP_V6_FLOW:
3155 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3156 break;
3157 case SCTP_V4_FLOW:
3158 case AH_ESP_V4_FLOW:
3159 case AH_V4_FLOW:
3160 case ESP_V4_FLOW:
3161 case IPV4_FLOW:
3162 case SCTP_V6_FLOW:
3163 case AH_ESP_V6_FLOW:
3164 case AH_V6_FLOW:
3165 case ESP_V6_FLOW:
3166 case IPV6_FLOW:
3167
3168 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
3169 break;
3170 default:
3171 return -EINVAL;
3172 }
3173
3174
3175 if (flow_pctype) {
3176 i_set = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3177 flow_pctype)) |
3178 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3179 flow_pctype)) << 32);
3180 }
3181
3182
3183 if (i_set) {
3184 if (i_set & I40E_L4_SRC_MASK)
3185 cmd->data |= RXH_L4_B_0_1;
3186 if (i_set & I40E_L4_DST_MASK)
3187 cmd->data |= RXH_L4_B_2_3;
3188
3189 if (cmd->flow_type == TCP_V4_FLOW ||
3190 cmd->flow_type == UDP_V4_FLOW) {
3191 if (i_set & I40E_L3_SRC_MASK)
3192 cmd->data |= RXH_IP_SRC;
3193 if (i_set & I40E_L3_DST_MASK)
3194 cmd->data |= RXH_IP_DST;
3195 } else if (cmd->flow_type == TCP_V6_FLOW ||
3196 cmd->flow_type == UDP_V6_FLOW) {
3197 if (i_set & I40E_L3_V6_SRC_MASK)
3198 cmd->data |= RXH_IP_SRC;
3199 if (i_set & I40E_L3_V6_DST_MASK)
3200 cmd->data |= RXH_IP_DST;
3201 }
3202 }
3203
3204 return 0;
3205 }
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215 static int i40e_check_mask(u64 mask, u64 field)
3216 {
3217 u64 value = mask & field;
3218
3219 if (value == field)
3220 return 1;
3221 else if (!value)
3222 return 0;
3223 else
3224 return -1;
3225 }
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246 static int i40e_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3247 struct i40e_rx_flow_userdef *data)
3248 {
3249 u64 value, mask;
3250 int valid;
3251
3252
3253 memset(data, 0, sizeof(*data));
3254
3255 if (!(fsp->flow_type & FLOW_EXT))
3256 return 0;
3257
3258 value = be64_to_cpu(*((__be64 *)fsp->h_ext.data));
3259 mask = be64_to_cpu(*((__be64 *)fsp->m_ext.data));
3260
3261 #define I40E_USERDEF_FLEX_WORD GENMASK_ULL(15, 0)
3262 #define I40E_USERDEF_FLEX_OFFSET GENMASK_ULL(31, 16)
3263 #define I40E_USERDEF_FLEX_FILTER GENMASK_ULL(31, 0)
3264
3265 valid = i40e_check_mask(mask, I40E_USERDEF_FLEX_FILTER);
3266 if (valid < 0) {
3267 return -EINVAL;
3268 } else if (valid) {
3269 data->flex_word = value & I40E_USERDEF_FLEX_WORD;
3270 data->flex_offset =
3271 (value & I40E_USERDEF_FLEX_OFFSET) >> 16;
3272 data->flex_filter = true;
3273 }
3274
3275 return 0;
3276 }
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286 static void i40e_fill_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3287 struct i40e_rx_flow_userdef *data)
3288 {
3289 u64 value = 0, mask = 0;
3290
3291 if (data->flex_filter) {
3292 value |= data->flex_word;
3293 value |= (u64)data->flex_offset << 16;
3294 mask |= I40E_USERDEF_FLEX_FILTER;
3295 }
3296
3297 if (value || mask)
3298 fsp->flow_type |= FLOW_EXT;
3299
3300 *((__be64 *)fsp->h_ext.data) = cpu_to_be64(value);
3301 *((__be64 *)fsp->m_ext.data) = cpu_to_be64(mask);
3302 }
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315 static int i40e_get_ethtool_fdir_all(struct i40e_pf *pf,
3316 struct ethtool_rxnfc *cmd,
3317 u32 *rule_locs)
3318 {
3319 struct i40e_fdir_filter *rule;
3320 struct hlist_node *node2;
3321 int cnt = 0;
3322
3323
3324 cmd->data = i40e_get_fd_cnt_all(pf);
3325
3326 hlist_for_each_entry_safe(rule, node2,
3327 &pf->fdir_filter_list, fdir_node) {
3328 if (cnt == cmd->rule_cnt)
3329 return -EMSGSIZE;
3330
3331 rule_locs[cnt] = rule->fd_id;
3332 cnt++;
3333 }
3334
3335 cmd->rule_cnt = cnt;
3336
3337 return 0;
3338 }
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350 static int i40e_get_ethtool_fdir_entry(struct i40e_pf *pf,
3351 struct ethtool_rxnfc *cmd)
3352 {
3353 struct ethtool_rx_flow_spec *fsp =
3354 (struct ethtool_rx_flow_spec *)&cmd->fs;
3355 struct i40e_rx_flow_userdef userdef = {0};
3356 struct i40e_fdir_filter *rule = NULL;
3357 struct hlist_node *node2;
3358 u64 input_set;
3359 u16 index;
3360
3361 hlist_for_each_entry_safe(rule, node2,
3362 &pf->fdir_filter_list, fdir_node) {
3363 if (fsp->location <= rule->fd_id)
3364 break;
3365 }
3366
3367 if (!rule || fsp->location != rule->fd_id)
3368 return -EINVAL;
3369
3370 fsp->flow_type = rule->flow_type;
3371 if (fsp->flow_type == IP_USER_FLOW) {
3372 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
3373 fsp->h_u.usr_ip4_spec.proto = 0;
3374 fsp->m_u.usr_ip4_spec.proto = 0;
3375 }
3376
3377 if (fsp->flow_type == IPV6_USER_FLOW ||
3378 fsp->flow_type == UDP_V6_FLOW ||
3379 fsp->flow_type == TCP_V6_FLOW ||
3380 fsp->flow_type == SCTP_V6_FLOW) {
3381
3382
3383
3384
3385 fsp->h_u.tcp_ip6_spec.psrc = rule->dst_port;
3386 fsp->h_u.tcp_ip6_spec.pdst = rule->src_port;
3387 memcpy(fsp->h_u.tcp_ip6_spec.ip6dst, rule->src_ip6,
3388 sizeof(__be32) * 4);
3389 memcpy(fsp->h_u.tcp_ip6_spec.ip6src, rule->dst_ip6,
3390 sizeof(__be32) * 4);
3391 } else {
3392
3393
3394
3395
3396 fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port;
3397 fsp->h_u.tcp_ip4_spec.pdst = rule->src_port;
3398 fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip;
3399 fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip;
3400 }
3401
3402 switch (rule->flow_type) {
3403 case SCTP_V4_FLOW:
3404 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3405 break;
3406 case TCP_V4_FLOW:
3407 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3408 break;
3409 case UDP_V4_FLOW:
3410 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3411 break;
3412 case SCTP_V6_FLOW:
3413 index = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3414 break;
3415 case TCP_V6_FLOW:
3416 index = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3417 break;
3418 case UDP_V6_FLOW:
3419 index = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3420 break;
3421 case IP_USER_FLOW:
3422 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3423 break;
3424 case IPV6_USER_FLOW:
3425 index = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3426 break;
3427 default:
3428
3429
3430
3431
3432
3433 WARN(1, "Missing input set index for flow_type %d\n",
3434 rule->flow_type);
3435 input_set = 0xFFFFFFFFFFFFFFFFULL;
3436 goto no_input_set;
3437 }
3438
3439 input_set = i40e_read_fd_input_set(pf, index);
3440
3441 no_input_set:
3442 if (input_set & I40E_L3_V6_SRC_MASK) {
3443 fsp->m_u.tcp_ip6_spec.ip6src[0] = htonl(0xFFFFFFFF);
3444 fsp->m_u.tcp_ip6_spec.ip6src[1] = htonl(0xFFFFFFFF);
3445 fsp->m_u.tcp_ip6_spec.ip6src[2] = htonl(0xFFFFFFFF);
3446 fsp->m_u.tcp_ip6_spec.ip6src[3] = htonl(0xFFFFFFFF);
3447 }
3448
3449 if (input_set & I40E_L3_V6_DST_MASK) {
3450 fsp->m_u.tcp_ip6_spec.ip6dst[0] = htonl(0xFFFFFFFF);
3451 fsp->m_u.tcp_ip6_spec.ip6dst[1] = htonl(0xFFFFFFFF);
3452 fsp->m_u.tcp_ip6_spec.ip6dst[2] = htonl(0xFFFFFFFF);
3453 fsp->m_u.tcp_ip6_spec.ip6dst[3] = htonl(0xFFFFFFFF);
3454 }
3455
3456 if (input_set & I40E_L3_SRC_MASK)
3457 fsp->m_u.tcp_ip4_spec.ip4src = htonl(0xFFFFFFFF);
3458
3459 if (input_set & I40E_L3_DST_MASK)
3460 fsp->m_u.tcp_ip4_spec.ip4dst = htonl(0xFFFFFFFF);
3461
3462 if (input_set & I40E_L4_SRC_MASK)
3463 fsp->m_u.tcp_ip4_spec.psrc = htons(0xFFFF);
3464
3465 if (input_set & I40E_L4_DST_MASK)
3466 fsp->m_u.tcp_ip4_spec.pdst = htons(0xFFFF);
3467
3468 if (rule->dest_ctl == I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET)
3469 fsp->ring_cookie = RX_CLS_FLOW_DISC;
3470 else
3471 fsp->ring_cookie = rule->q_index;
3472
3473 if (rule->vlan_tag) {
3474 fsp->h_ext.vlan_etype = rule->vlan_etype;
3475 fsp->m_ext.vlan_etype = htons(0xFFFF);
3476 fsp->h_ext.vlan_tci = rule->vlan_tag;
3477 fsp->m_ext.vlan_tci = htons(0xFFFF);
3478 fsp->flow_type |= FLOW_EXT;
3479 }
3480
3481 if (rule->dest_vsi != pf->vsi[pf->lan_vsi]->id) {
3482 struct i40e_vsi *vsi;
3483
3484 vsi = i40e_find_vsi_from_id(pf, rule->dest_vsi);
3485 if (vsi && vsi->type == I40E_VSI_SRIOV) {
3486
3487
3488
3489 u64 ring_vf = vsi->vf_id + 1;
3490
3491 ring_vf <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
3492 fsp->ring_cookie |= ring_vf;
3493 }
3494 }
3495
3496 if (rule->flex_filter) {
3497 userdef.flex_filter = true;
3498 userdef.flex_word = be16_to_cpu(rule->flex_word);
3499 userdef.flex_offset = rule->flex_offset;
3500 }
3501
3502 i40e_fill_rx_flow_user_data(fsp, &userdef);
3503
3504 return 0;
3505 }
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515 static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3516 u32 *rule_locs)
3517 {
3518 struct i40e_netdev_priv *np = netdev_priv(netdev);
3519 struct i40e_vsi *vsi = np->vsi;
3520 struct i40e_pf *pf = vsi->back;
3521 int ret = -EOPNOTSUPP;
3522
3523 switch (cmd->cmd) {
3524 case ETHTOOL_GRXRINGS:
3525 cmd->data = vsi->rss_size;
3526 ret = 0;
3527 break;
3528 case ETHTOOL_GRXFH:
3529 ret = i40e_get_rss_hash_opts(pf, cmd);
3530 break;
3531 case ETHTOOL_GRXCLSRLCNT:
3532 cmd->rule_cnt = pf->fdir_pf_active_filters;
3533
3534 cmd->data = i40e_get_fd_cnt_all(pf);
3535 ret = 0;
3536 break;
3537 case ETHTOOL_GRXCLSRULE:
3538 ret = i40e_get_ethtool_fdir_entry(pf, cmd);
3539 break;
3540 case ETHTOOL_GRXCLSRLALL:
3541 ret = i40e_get_ethtool_fdir_all(pf, cmd, rule_locs);
3542 break;
3543 default:
3544 break;
3545 }
3546
3547 return ret;
3548 }
3549
3550
3551
3552
3553
3554
3555
3556
3557 static u64 i40e_get_rss_hash_bits(struct ethtool_rxnfc *nfc, u64 i_setc)
3558 {
3559 u64 i_set = i_setc;
3560 u64 src_l3 = 0, dst_l3 = 0;
3561
3562 if (nfc->data & RXH_L4_B_0_1)
3563 i_set |= I40E_L4_SRC_MASK;
3564 else
3565 i_set &= ~I40E_L4_SRC_MASK;
3566 if (nfc->data & RXH_L4_B_2_3)
3567 i_set |= I40E_L4_DST_MASK;
3568 else
3569 i_set &= ~I40E_L4_DST_MASK;
3570
3571 if (nfc->flow_type == TCP_V6_FLOW || nfc->flow_type == UDP_V6_FLOW) {
3572 src_l3 = I40E_L3_V6_SRC_MASK;
3573 dst_l3 = I40E_L3_V6_DST_MASK;
3574 } else if (nfc->flow_type == TCP_V4_FLOW ||
3575 nfc->flow_type == UDP_V4_FLOW) {
3576 src_l3 = I40E_L3_SRC_MASK;
3577 dst_l3 = I40E_L3_DST_MASK;
3578 } else {
3579
3580 return i_set;
3581 }
3582
3583 if (nfc->data & RXH_IP_SRC)
3584 i_set |= src_l3;
3585 else
3586 i_set &= ~src_l3;
3587 if (nfc->data & RXH_IP_DST)
3588 i_set |= dst_l3;
3589 else
3590 i_set &= ~dst_l3;
3591
3592 return i_set;
3593 }
3594
3595
3596
3597
3598
3599
3600
3601
3602 static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
3603 {
3604 struct i40e_hw *hw = &pf->hw;
3605 u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
3606 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
3607 u8 flow_pctype = 0;
3608 u64 i_set, i_setc;
3609
3610 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3611 dev_err(&pf->pdev->dev,
3612 "Change of RSS hash input set is not supported when MFP mode is enabled\n");
3613 return -EOPNOTSUPP;
3614 }
3615
3616
3617
3618
3619 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3620 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3621 return -EINVAL;
3622
3623 switch (nfc->flow_type) {
3624 case TCP_V4_FLOW:
3625 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3626 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3627 hena |=
3628 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3629 break;
3630 case TCP_V6_FLOW:
3631 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3632 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3633 hena |=
3634 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3635 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3636 hena |=
3637 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3638 break;
3639 case UDP_V4_FLOW:
3640 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3641 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3642 hena |=
3643 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
3644 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3645
3646 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3647 break;
3648 case UDP_V6_FLOW:
3649 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3650 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3651 hena |=
3652 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
3653 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3654
3655 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3656 break;
3657 case AH_ESP_V4_FLOW:
3658 case AH_V4_FLOW:
3659 case ESP_V4_FLOW:
3660 case SCTP_V4_FLOW:
3661 if ((nfc->data & RXH_L4_B_0_1) ||
3662 (nfc->data & RXH_L4_B_2_3))
3663 return -EINVAL;
3664 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3665 break;
3666 case AH_ESP_V6_FLOW:
3667 case AH_V6_FLOW:
3668 case ESP_V6_FLOW:
3669 case SCTP_V6_FLOW:
3670 if ((nfc->data & RXH_L4_B_0_1) ||
3671 (nfc->data & RXH_L4_B_2_3))
3672 return -EINVAL;
3673 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3674 break;
3675 case IPV4_FLOW:
3676 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
3677 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3678 break;
3679 case IPV6_FLOW:
3680 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
3681 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3682 break;
3683 default:
3684 return -EINVAL;
3685 }
3686
3687 if (flow_pctype) {
3688 i_setc = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3689 flow_pctype)) |
3690 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3691 flow_pctype)) << 32);
3692 i_set = i40e_get_rss_hash_bits(nfc, i_setc);
3693 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_pctype),
3694 (u32)i_set);
3695 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_pctype),
3696 (u32)(i_set >> 32));
3697 hena |= BIT_ULL(flow_pctype);
3698 }
3699
3700 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
3701 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
3702 i40e_flush(hw);
3703
3704 return 0;
3705 }
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719 static int i40e_update_ethtool_fdir_entry(struct i40e_vsi *vsi,
3720 struct i40e_fdir_filter *input,
3721 u16 sw_idx,
3722 struct ethtool_rxnfc *cmd)
3723 {
3724 struct i40e_fdir_filter *rule, *parent;
3725 struct i40e_pf *pf = vsi->back;
3726 struct hlist_node *node2;
3727 int err = -EINVAL;
3728
3729 parent = NULL;
3730 rule = NULL;
3731
3732 hlist_for_each_entry_safe(rule, node2,
3733 &pf->fdir_filter_list, fdir_node) {
3734
3735 if (rule->fd_id >= sw_idx)
3736 break;
3737 parent = rule;
3738 }
3739
3740
3741 if (rule && (rule->fd_id == sw_idx)) {
3742
3743
3744
3745 err = i40e_add_del_fdir(vsi, rule, false);
3746 hlist_del(&rule->fdir_node);
3747 kfree(rule);
3748 pf->fdir_pf_active_filters--;
3749 }
3750
3751
3752
3753
3754 if (!input)
3755 return err;
3756
3757
3758 INIT_HLIST_NODE(&input->fdir_node);
3759
3760
3761 if (parent)
3762 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
3763 else
3764 hlist_add_head(&input->fdir_node,
3765 &pf->fdir_filter_list);
3766
3767
3768 pf->fdir_pf_active_filters++;
3769
3770 return 0;
3771 }
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781 static void i40e_prune_flex_pit_list(struct i40e_pf *pf)
3782 {
3783 struct i40e_flex_pit *entry, *tmp;
3784 struct i40e_fdir_filter *rule;
3785
3786
3787 list_for_each_entry_safe(entry, tmp, &pf->l3_flex_pit_list, list) {
3788 bool found = false;
3789
3790 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3791 if (rule->flow_type != IP_USER_FLOW)
3792 continue;
3793 if (rule->flex_filter &&
3794 rule->flex_offset == entry->src_offset) {
3795 found = true;
3796 break;
3797 }
3798 }
3799
3800
3801
3802
3803 if (!found) {
3804 list_del(&entry->list);
3805 kfree(entry);
3806 }
3807 }
3808
3809
3810 list_for_each_entry_safe(entry, tmp, &pf->l4_flex_pit_list, list) {
3811 bool found = false;
3812
3813 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3814
3815
3816
3817 if (rule->flow_type == IP_USER_FLOW)
3818 continue;
3819 if (rule->flex_filter &&
3820 rule->flex_offset == entry->src_offset) {
3821 found = true;
3822 break;
3823 }
3824 }
3825
3826
3827
3828
3829 if (!found) {
3830 list_del(&entry->list);
3831 kfree(entry);
3832 }
3833 }
3834 }
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846 static int i40e_del_fdir_entry(struct i40e_vsi *vsi,
3847 struct ethtool_rxnfc *cmd)
3848 {
3849 struct ethtool_rx_flow_spec *fsp =
3850 (struct ethtool_rx_flow_spec *)&cmd->fs;
3851 struct i40e_pf *pf = vsi->back;
3852 int ret = 0;
3853
3854 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
3855 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
3856 return -EBUSY;
3857
3858 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
3859 return -EBUSY;
3860
3861 ret = i40e_update_ethtool_fdir_entry(vsi, NULL, fsp->location, cmd);
3862
3863 i40e_prune_flex_pit_list(pf);
3864
3865 i40e_fdir_check_and_reenable(pf);
3866 return ret;
3867 }
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878 static u8 i40e_unused_pit_index(struct i40e_pf *pf)
3879 {
3880 unsigned long available_index = 0xFF;
3881 struct i40e_flex_pit *entry;
3882
3883
3884
3885
3886
3887
3888 list_for_each_entry(entry, &pf->l4_flex_pit_list, list)
3889 clear_bit(entry->pit_index, &available_index);
3890
3891 list_for_each_entry(entry, &pf->l3_flex_pit_list, list)
3892 clear_bit(entry->pit_index, &available_index);
3893
3894 return find_first_bit(&available_index, 8);
3895 }
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906 static
3907 struct i40e_flex_pit *i40e_find_flex_offset(struct list_head *flex_pit_list,
3908 u16 src_offset)
3909 {
3910 struct i40e_flex_pit *entry;
3911 int size = 0;
3912
3913
3914
3915
3916 list_for_each_entry(entry, flex_pit_list, list) {
3917 size++;
3918 if (entry->src_offset == src_offset)
3919 return entry;
3920 }
3921
3922
3923
3924
3925
3926
3927 if (size >= I40E_FLEX_PIT_TABLE_SIZE)
3928 return ERR_PTR(-ENOSPC);
3929
3930 return NULL;
3931 }
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946 static int i40e_add_flex_offset(struct list_head *flex_pit_list,
3947 u16 src_offset,
3948 u8 pit_index)
3949 {
3950 struct i40e_flex_pit *new_pit, *entry;
3951
3952 new_pit = kzalloc(sizeof(*entry), GFP_KERNEL);
3953 if (!new_pit)
3954 return -ENOMEM;
3955
3956 new_pit->src_offset = src_offset;
3957 new_pit->pit_index = pit_index;
3958
3959
3960
3961
3962 list_for_each_entry(entry, flex_pit_list, list) {
3963 if (new_pit->src_offset < entry->src_offset) {
3964 list_add_tail(&new_pit->list, &entry->list);
3965 return 0;
3966 }
3967
3968
3969
3970
3971
3972 if (new_pit->src_offset == entry->src_offset) {
3973 int err = 0;
3974
3975
3976
3977
3978 if (new_pit->pit_index != entry->pit_index)
3979 err = -EINVAL;
3980
3981 kfree(new_pit);
3982 return err;
3983 }
3984 }
3985
3986
3987
3988
3989 list_add_tail(&new_pit->list, flex_pit_list);
3990 return 0;
3991 }
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014 static void __i40e_reprogram_flex_pit(struct i40e_pf *pf,
4015 struct list_head *flex_pit_list,
4016 int flex_pit_start)
4017 {
4018 struct i40e_flex_pit *entry = NULL;
4019 u16 last_offset = 0;
4020 int i = 0, j = 0;
4021
4022
4023
4024
4025 list_for_each_entry(entry, flex_pit_list, list) {
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040 for (j = i + 1; j < 3; j++) {
4041 u16 offset = entry->src_offset + j;
4042 int index = flex_pit_start + i;
4043 u32 value = I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
4044 1,
4045 offset - 3);
4046
4047 if (offset > I40E_MAX_FLEX_SRC_OFFSET) {
4048 i40e_write_rx_ctl(&pf->hw,
4049 I40E_PRTQF_FLX_PIT(index),
4050 value);
4051 i++;
4052 }
4053 }
4054
4055
4056 i40e_write_rx_ctl(&pf->hw,
4057 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
4058 I40E_FLEX_PREP_VAL(entry->pit_index + 50,
4059 1,
4060 entry->src_offset));
4061 i++;
4062 }
4063
4064
4065
4066
4067
4068
4069
4070 if (!list_empty(flex_pit_list))
4071 last_offset = list_prev_entry(entry, list)->src_offset + 1;
4072
4073 for (; i < 3; i++, last_offset++) {
4074 i40e_write_rx_ctl(&pf->hw,
4075 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
4076 I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
4077 1,
4078 last_offset));
4079 }
4080 }
4081
4082
4083
4084
4085
4086
4087
4088
4089 static void i40e_reprogram_flex_pit(struct i40e_pf *pf)
4090 {
4091 __i40e_reprogram_flex_pit(pf, &pf->l3_flex_pit_list,
4092 I40E_FLEX_PIT_IDX_START_L3);
4093
4094 __i40e_reprogram_flex_pit(pf, &pf->l4_flex_pit_list,
4095 I40E_FLEX_PIT_IDX_START_L4);
4096
4097
4098 i40e_write_rx_ctl(&pf->hw,
4099 I40E_GLQF_ORT(I40E_L3_GLQF_ORT_IDX),
4100 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L3,
4101 3, 1));
4102
4103 i40e_write_rx_ctl(&pf->hw,
4104 I40E_GLQF_ORT(I40E_L4_GLQF_ORT_IDX),
4105 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L4,
4106 3, 1));
4107 }
4108
4109
4110
4111
4112
4113
4114
4115
4116 static const char *i40e_flow_str(struct ethtool_rx_flow_spec *fsp)
4117 {
4118 switch (fsp->flow_type & ~FLOW_EXT) {
4119 case TCP_V4_FLOW:
4120 return "tcp4";
4121 case UDP_V4_FLOW:
4122 return "udp4";
4123 case SCTP_V4_FLOW:
4124 return "sctp4";
4125 case IP_USER_FLOW:
4126 return "ip4";
4127 case TCP_V6_FLOW:
4128 return "tcp6";
4129 case UDP_V6_FLOW:
4130 return "udp6";
4131 case SCTP_V6_FLOW:
4132 return "sctp6";
4133 case IPV6_USER_FLOW:
4134 return "ip6";
4135 default:
4136 return "unknown";
4137 }
4138 }
4139
4140
4141
4142
4143
4144
4145
4146
4147 static u64 i40e_pit_index_to_mask(int pit_index)
4148 {
4149 switch (pit_index) {
4150 case 0:
4151 return I40E_FLEX_50_MASK;
4152 case 1:
4153 return I40E_FLEX_51_MASK;
4154 case 2:
4155 return I40E_FLEX_52_MASK;
4156 case 3:
4157 return I40E_FLEX_53_MASK;
4158 case 4:
4159 return I40E_FLEX_54_MASK;
4160 case 5:
4161 return I40E_FLEX_55_MASK;
4162 case 6:
4163 return I40E_FLEX_56_MASK;
4164 case 7:
4165 return I40E_FLEX_57_MASK;
4166 default:
4167 return 0;
4168 }
4169 }
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181 static void i40e_print_input_set(struct i40e_vsi *vsi, u64 old, u64 new)
4182 {
4183 struct i40e_pf *pf = vsi->back;
4184 bool old_value, new_value;
4185 int i;
4186
4187 old_value = !!(old & I40E_L3_SRC_MASK);
4188 new_value = !!(new & I40E_L3_SRC_MASK);
4189 if (old_value != new_value)
4190 netif_info(pf, drv, vsi->netdev, "L3 source address: %s -> %s\n",
4191 old_value ? "ON" : "OFF",
4192 new_value ? "ON" : "OFF");
4193
4194 old_value = !!(old & I40E_L3_DST_MASK);
4195 new_value = !!(new & I40E_L3_DST_MASK);
4196 if (old_value != new_value)
4197 netif_info(pf, drv, vsi->netdev, "L3 destination address: %s -> %s\n",
4198 old_value ? "ON" : "OFF",
4199 new_value ? "ON" : "OFF");
4200
4201 old_value = !!(old & I40E_L4_SRC_MASK);
4202 new_value = !!(new & I40E_L4_SRC_MASK);
4203 if (old_value != new_value)
4204 netif_info(pf, drv, vsi->netdev, "L4 source port: %s -> %s\n",
4205 old_value ? "ON" : "OFF",
4206 new_value ? "ON" : "OFF");
4207
4208 old_value = !!(old & I40E_L4_DST_MASK);
4209 new_value = !!(new & I40E_L4_DST_MASK);
4210 if (old_value != new_value)
4211 netif_info(pf, drv, vsi->netdev, "L4 destination port: %s -> %s\n",
4212 old_value ? "ON" : "OFF",
4213 new_value ? "ON" : "OFF");
4214
4215 old_value = !!(old & I40E_VERIFY_TAG_MASK);
4216 new_value = !!(new & I40E_VERIFY_TAG_MASK);
4217 if (old_value != new_value)
4218 netif_info(pf, drv, vsi->netdev, "SCTP verification tag: %s -> %s\n",
4219 old_value ? "ON" : "OFF",
4220 new_value ? "ON" : "OFF");
4221
4222
4223 for (i = 0; i < I40E_FLEX_INDEX_ENTRIES; i++) {
4224 u64 flex_mask = i40e_pit_index_to_mask(i);
4225
4226 old_value = !!(old & flex_mask);
4227 new_value = !!(new & flex_mask);
4228 if (old_value != new_value)
4229 netif_info(pf, drv, vsi->netdev, "FLEX index %d: %s -> %s\n",
4230 i,
4231 old_value ? "ON" : "OFF",
4232 new_value ? "ON" : "OFF");
4233 }
4234
4235 netif_info(pf, drv, vsi->netdev, " Current input set: %0llx\n",
4236 old);
4237 netif_info(pf, drv, vsi->netdev, "Requested input set: %0llx\n",
4238 new);
4239 }
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266 static int i40e_check_fdir_input_set(struct i40e_vsi *vsi,
4267 struct ethtool_rx_flow_spec *fsp,
4268 struct i40e_rx_flow_userdef *userdef)
4269 {
4270 static const __be32 ipv6_full_mask[4] = {cpu_to_be32(0xffffffff),
4271 cpu_to_be32(0xffffffff), cpu_to_be32(0xffffffff),
4272 cpu_to_be32(0xffffffff)};
4273 struct ethtool_tcpip6_spec *tcp_ip6_spec;
4274 struct ethtool_usrip6_spec *usr_ip6_spec;
4275 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4276 struct ethtool_usrip4_spec *usr_ip4_spec;
4277 struct i40e_pf *pf = vsi->back;
4278 u64 current_mask, new_mask;
4279 bool new_flex_offset = false;
4280 bool flex_l3 = false;
4281 u16 *fdir_filter_count;
4282 u16 index, src_offset = 0;
4283 u8 pit_index = 0;
4284 int err;
4285
4286 switch (fsp->flow_type & ~FLOW_EXT) {
4287 case SCTP_V4_FLOW:
4288 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4289 fdir_filter_count = &pf->fd_sctp4_filter_cnt;
4290 break;
4291 case TCP_V4_FLOW:
4292 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4293 fdir_filter_count = &pf->fd_tcp4_filter_cnt;
4294 break;
4295 case UDP_V4_FLOW:
4296 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4297 fdir_filter_count = &pf->fd_udp4_filter_cnt;
4298 break;
4299 case SCTP_V6_FLOW:
4300 index = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4301 fdir_filter_count = &pf->fd_sctp6_filter_cnt;
4302 break;
4303 case TCP_V6_FLOW:
4304 index = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4305 fdir_filter_count = &pf->fd_tcp6_filter_cnt;
4306 break;
4307 case UDP_V6_FLOW:
4308 index = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4309 fdir_filter_count = &pf->fd_udp6_filter_cnt;
4310 break;
4311 case IP_USER_FLOW:
4312 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4313 fdir_filter_count = &pf->fd_ip4_filter_cnt;
4314 flex_l3 = true;
4315 break;
4316 case IPV6_USER_FLOW:
4317 index = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4318 fdir_filter_count = &pf->fd_ip6_filter_cnt;
4319 flex_l3 = true;
4320 break;
4321 default:
4322 return -EOPNOTSUPP;
4323 }
4324
4325
4326 current_mask = i40e_read_fd_input_set(pf, index);
4327 new_mask = current_mask;
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338 switch (fsp->flow_type & ~FLOW_EXT) {
4339 case SCTP_V4_FLOW:
4340 new_mask &= ~I40E_VERIFY_TAG_MASK;
4341 fallthrough;
4342 case TCP_V4_FLOW:
4343 case UDP_V4_FLOW:
4344 tcp_ip4_spec = &fsp->m_u.tcp_ip4_spec;
4345
4346
4347 if (tcp_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4348 new_mask |= I40E_L3_SRC_MASK;
4349 else if (!tcp_ip4_spec->ip4src)
4350 new_mask &= ~I40E_L3_SRC_MASK;
4351 else
4352 return -EOPNOTSUPP;
4353
4354
4355 if (tcp_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4356 new_mask |= I40E_L3_DST_MASK;
4357 else if (!tcp_ip4_spec->ip4dst)
4358 new_mask &= ~I40E_L3_DST_MASK;
4359 else
4360 return -EOPNOTSUPP;
4361
4362
4363 if (tcp_ip4_spec->psrc == htons(0xFFFF))
4364 new_mask |= I40E_L4_SRC_MASK;
4365 else if (!tcp_ip4_spec->psrc)
4366 new_mask &= ~I40E_L4_SRC_MASK;
4367 else
4368 return -EOPNOTSUPP;
4369
4370
4371 if (tcp_ip4_spec->pdst == htons(0xFFFF))
4372 new_mask |= I40E_L4_DST_MASK;
4373 else if (!tcp_ip4_spec->pdst)
4374 new_mask &= ~I40E_L4_DST_MASK;
4375 else
4376 return -EOPNOTSUPP;
4377
4378
4379 if (tcp_ip4_spec->tos)
4380 return -EOPNOTSUPP;
4381
4382 break;
4383 case SCTP_V6_FLOW:
4384 new_mask &= ~I40E_VERIFY_TAG_MASK;
4385 fallthrough;
4386 case TCP_V6_FLOW:
4387 case UDP_V6_FLOW:
4388 tcp_ip6_spec = &fsp->m_u.tcp_ip6_spec;
4389
4390
4391 if (ipv6_addr_equal((struct in6_addr *)&tcp_ip6_spec->ip6src,
4392 (struct in6_addr *)&ipv6_full_mask))
4393 new_mask |= I40E_L3_V6_SRC_MASK;
4394 else if (ipv6_addr_any((struct in6_addr *)
4395 &tcp_ip6_spec->ip6src))
4396 new_mask &= ~I40E_L3_V6_SRC_MASK;
4397 else
4398 return -EOPNOTSUPP;
4399
4400
4401 if (ipv6_addr_equal((struct in6_addr *)&tcp_ip6_spec->ip6dst,
4402 (struct in6_addr *)&ipv6_full_mask))
4403 new_mask |= I40E_L3_V6_DST_MASK;
4404 else if (ipv6_addr_any((struct in6_addr *)
4405 &tcp_ip6_spec->ip6dst))
4406 new_mask &= ~I40E_L3_V6_DST_MASK;
4407 else
4408 return -EOPNOTSUPP;
4409
4410
4411 if (tcp_ip6_spec->psrc == htons(0xFFFF))
4412 new_mask |= I40E_L4_SRC_MASK;
4413 else if (!tcp_ip6_spec->psrc)
4414 new_mask &= ~I40E_L4_SRC_MASK;
4415 else
4416 return -EOPNOTSUPP;
4417
4418
4419 if (tcp_ip6_spec->pdst == htons(0xFFFF))
4420 new_mask |= I40E_L4_DST_MASK;
4421 else if (!tcp_ip6_spec->pdst)
4422 new_mask &= ~I40E_L4_DST_MASK;
4423 else
4424 return -EOPNOTSUPP;
4425
4426
4427 if (tcp_ip6_spec->tclass)
4428 return -EOPNOTSUPP;
4429 break;
4430 case IP_USER_FLOW:
4431 usr_ip4_spec = &fsp->m_u.usr_ip4_spec;
4432
4433
4434 if (usr_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4435 new_mask |= I40E_L3_SRC_MASK;
4436 else if (!usr_ip4_spec->ip4src)
4437 new_mask &= ~I40E_L3_SRC_MASK;
4438 else
4439 return -EOPNOTSUPP;
4440
4441
4442 if (usr_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4443 new_mask |= I40E_L3_DST_MASK;
4444 else if (!usr_ip4_spec->ip4dst)
4445 new_mask &= ~I40E_L3_DST_MASK;
4446 else
4447 return -EOPNOTSUPP;
4448
4449
4450 if (usr_ip4_spec->l4_4_bytes == htonl(0xFFFFFFFF))
4451 new_mask |= I40E_L4_SRC_MASK | I40E_L4_DST_MASK;
4452 else if (!usr_ip4_spec->l4_4_bytes)
4453 new_mask &= ~(I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
4454 else
4455 return -EOPNOTSUPP;
4456
4457
4458 if (usr_ip4_spec->tos)
4459 return -EOPNOTSUPP;
4460
4461
4462 if (usr_ip4_spec->ip_ver)
4463 return -EINVAL;
4464
4465
4466 if (usr_ip4_spec->proto)
4467 return -EINVAL;
4468
4469 break;
4470 case IPV6_USER_FLOW:
4471 usr_ip6_spec = &fsp->m_u.usr_ip6_spec;
4472
4473
4474 if (ipv6_addr_equal((struct in6_addr *)&usr_ip6_spec->ip6src,
4475 (struct in6_addr *)&ipv6_full_mask))
4476 new_mask |= I40E_L3_V6_SRC_MASK;
4477 else if (ipv6_addr_any((struct in6_addr *)
4478 &usr_ip6_spec->ip6src))
4479 new_mask &= ~I40E_L3_V6_SRC_MASK;
4480 else
4481 return -EOPNOTSUPP;
4482
4483
4484 if (ipv6_addr_equal((struct in6_addr *)&usr_ip6_spec->ip6dst,
4485 (struct in6_addr *)&ipv6_full_mask))
4486 new_mask |= I40E_L3_V6_DST_MASK;
4487 else if (ipv6_addr_any((struct in6_addr *)
4488 &usr_ip6_spec->ip6dst))
4489 new_mask &= ~I40E_L3_V6_DST_MASK;
4490 else
4491 return -EOPNOTSUPP;
4492
4493 if (usr_ip6_spec->l4_4_bytes == htonl(0xFFFFFFFF))
4494 new_mask |= I40E_L4_SRC_MASK | I40E_L4_DST_MASK;
4495 else if (!usr_ip6_spec->l4_4_bytes)
4496 new_mask &= ~(I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
4497 else
4498 return -EOPNOTSUPP;
4499
4500
4501 if (usr_ip6_spec->tclass)
4502 return -EOPNOTSUPP;
4503
4504
4505 if (usr_ip6_spec->l4_proto)
4506 return -EINVAL;
4507
4508 break;
4509 default:
4510 return -EOPNOTSUPP;
4511 }
4512
4513 if (fsp->flow_type & FLOW_EXT) {
4514
4515
4516
4517 if (fsp->h_ext.vlan_etype != htons(ETH_P_8021Q) &&
4518 fsp->h_ext.vlan_etype != 0)
4519 return -EOPNOTSUPP;
4520 if (fsp->m_ext.vlan_tci == htons(0xFFFF))
4521 new_mask |= I40E_VLAN_SRC_MASK;
4522 else
4523 new_mask &= ~I40E_VLAN_SRC_MASK;
4524 }
4525
4526
4527 new_mask &= ~I40E_FLEX_INPUT_MASK;
4528
4529
4530
4531
4532
4533
4534 if (userdef->flex_filter) {
4535 struct i40e_flex_pit *l3_flex_pit = NULL, *flex_pit = NULL;
4536
4537
4538
4539
4540 if (userdef->flex_offset & 0x1) {
4541 dev_warn(&pf->pdev->dev,
4542 "Flexible data offset must be 2-byte aligned\n");
4543 return -EINVAL;
4544 }
4545
4546 src_offset = userdef->flex_offset >> 1;
4547
4548
4549 if (src_offset > I40E_MAX_FLEX_SRC_OFFSET) {
4550 dev_warn(&pf->pdev->dev,
4551 "Flexible data must reside within first 64 bytes of the packet payload\n");
4552 return -EINVAL;
4553 }
4554
4555
4556
4557
4558
4559
4560 flex_pit = i40e_find_flex_offset(&pf->l4_flex_pit_list,
4561 src_offset);
4562 if (IS_ERR(flex_pit))
4563 return PTR_ERR(flex_pit);
4564
4565
4566
4567
4568
4569
4570
4571
4572 if (flex_l3) {
4573 l3_flex_pit =
4574 i40e_find_flex_offset(&pf->l3_flex_pit_list,
4575 src_offset);
4576 if (IS_ERR(l3_flex_pit))
4577 return PTR_ERR(l3_flex_pit);
4578
4579 if (flex_pit) {
4580
4581
4582
4583
4584 if (l3_flex_pit) {
4585 if (l3_flex_pit->pit_index !=
4586 flex_pit->pit_index) {
4587 return -EINVAL;
4588 }
4589 } else {
4590 new_flex_offset = true;
4591 }
4592 } else {
4593 flex_pit = l3_flex_pit;
4594 }
4595 }
4596
4597
4598
4599
4600
4601
4602 if (!flex_pit) {
4603 new_flex_offset = true;
4604 pit_index = i40e_unused_pit_index(pf);
4605 } else {
4606 pit_index = flex_pit->pit_index;
4607 }
4608
4609
4610 new_mask |= i40e_pit_index_to_mask(pit_index);
4611 }
4612
4613
4614
4615
4616
4617 if (new_mask == current_mask && !new_flex_offset)
4618 return 0;
4619
4620 netif_info(pf, drv, vsi->netdev, "Input set change requested for %s flows:\n",
4621 i40e_flow_str(fsp));
4622 i40e_print_input_set(vsi, current_mask, new_mask);
4623 if (new_flex_offset) {
4624 netif_info(pf, drv, vsi->netdev, "FLEX index %d: Offset -> %d",
4625 pit_index, src_offset);
4626 }
4627
4628
4629
4630
4631
4632 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4633 netif_err(pf, drv, vsi->netdev, "Cannot change Flow Director input sets while MFP is enabled\n");
4634 return -EOPNOTSUPP;
4635 }
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646 if (*fdir_filter_count) {
4647 netif_err(pf, drv, vsi->netdev, "Cannot change input set for %s flows until %d preexisting filters are removed\n",
4648 i40e_flow_str(fsp),
4649 *fdir_filter_count);
4650 return -EOPNOTSUPP;
4651 }
4652
4653 i40e_write_fd_input_set(pf, index, new_mask);
4654
4655
4656
4657
4658
4659
4660
4661 if (index == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER)
4662 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4,
4663 new_mask);
4664
4665
4666 if (new_flex_offset) {
4667 err = i40e_add_flex_offset(&pf->l4_flex_pit_list, src_offset,
4668 pit_index);
4669 if (err)
4670 return err;
4671
4672 if (flex_l3) {
4673 err = i40e_add_flex_offset(&pf->l3_flex_pit_list,
4674 src_offset,
4675 pit_index);
4676 if (err)
4677 return err;
4678 }
4679
4680 i40e_reprogram_flex_pit(pf);
4681 }
4682
4683 return 0;
4684 }
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696 static bool i40e_match_fdir_filter(struct i40e_fdir_filter *a,
4697 struct i40e_fdir_filter *b)
4698 {
4699
4700 if (a->dst_ip != b->dst_ip ||
4701 a->src_ip != b->src_ip ||
4702 a->dst_port != b->dst_port ||
4703 a->src_port != b->src_port ||
4704 a->flow_type != b->flow_type ||
4705 a->ipl4_proto != b->ipl4_proto ||
4706 a->vlan_tag != b->vlan_tag ||
4707 a->vlan_etype != b->vlan_etype)
4708 return false;
4709
4710 return true;
4711 }
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738 static int i40e_disallow_matching_filters(struct i40e_vsi *vsi,
4739 struct i40e_fdir_filter *input)
4740 {
4741 struct i40e_pf *pf = vsi->back;
4742 struct i40e_fdir_filter *rule;
4743 struct hlist_node *node2;
4744
4745
4746 hlist_for_each_entry_safe(rule, node2,
4747 &pf->fdir_filter_list, fdir_node) {
4748
4749
4750
4751
4752 if (rule->fd_id == input->fd_id)
4753 continue;
4754
4755
4756
4757
4758 if (i40e_match_fdir_filter(rule, input)) {
4759 dev_warn(&pf->pdev->dev,
4760 "Existing user defined filter %d already matches this flow.\n",
4761 rule->fd_id);
4762 return -EINVAL;
4763 }
4764 }
4765
4766 return 0;
4767 }
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777 static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi,
4778 struct ethtool_rxnfc *cmd)
4779 {
4780 struct i40e_rx_flow_userdef userdef;
4781 struct ethtool_rx_flow_spec *fsp;
4782 struct i40e_fdir_filter *input;
4783 u16 dest_vsi = 0, q_index = 0;
4784 struct i40e_pf *pf;
4785 int ret = -EINVAL;
4786 u8 dest_ctl;
4787
4788 if (!vsi)
4789 return -EINVAL;
4790 pf = vsi->back;
4791
4792 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
4793 return -EOPNOTSUPP;
4794
4795 if (test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
4796 return -ENOSPC;
4797
4798 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
4799 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
4800 return -EBUSY;
4801
4802 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
4803 return -EBUSY;
4804
4805 fsp = (struct ethtool_rx_flow_spec *)&cmd->fs;
4806
4807
4808 if (i40e_parse_rx_flow_user_data(fsp, &userdef))
4809 return -EINVAL;
4810
4811
4812 if (fsp->flow_type & FLOW_MAC_EXT)
4813 return -EINVAL;
4814
4815 ret = i40e_check_fdir_input_set(vsi, fsp, &userdef);
4816 if (ret)
4817 return ret;
4818
4819 if (fsp->location >= (pf->hw.func_caps.fd_filters_best_effort +
4820 pf->hw.func_caps.fd_filters_guaranteed)) {
4821 return -EINVAL;
4822 }
4823
4824
4825
4826
4827 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
4828 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4829 } else {
4830 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
4831 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
4832
4833 if (!vf) {
4834 if (ring >= vsi->num_queue_pairs)
4835 return -EINVAL;
4836 dest_vsi = vsi->id;
4837 } else {
4838
4839 vf--;
4840
4841 if (vf >= pf->num_alloc_vfs)
4842 return -EINVAL;
4843 if (ring >= pf->vf[vf].num_queue_pairs)
4844 return -EINVAL;
4845 dest_vsi = pf->vf[vf].lan_vsi_id;
4846 }
4847 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
4848 q_index = ring;
4849 }
4850
4851 input = kzalloc(sizeof(*input), GFP_KERNEL);
4852
4853 if (!input)
4854 return -ENOMEM;
4855
4856 input->fd_id = fsp->location;
4857 input->q_index = q_index;
4858 input->dest_vsi = dest_vsi;
4859 input->dest_ctl = dest_ctl;
4860 input->fd_status = I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID;
4861 input->cnt_index = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
4862 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4863 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4864 input->flow_type = fsp->flow_type & ~FLOW_EXT;
4865
4866 input->vlan_etype = fsp->h_ext.vlan_etype;
4867 if (!fsp->m_ext.vlan_etype && fsp->h_ext.vlan_tci)
4868 input->vlan_etype = cpu_to_be16(ETH_P_8021Q);
4869 if (fsp->m_ext.vlan_tci && input->vlan_etype)
4870 input->vlan_tag = fsp->h_ext.vlan_tci;
4871 if (input->flow_type == IPV6_USER_FLOW ||
4872 input->flow_type == UDP_V6_FLOW ||
4873 input->flow_type == TCP_V6_FLOW ||
4874 input->flow_type == SCTP_V6_FLOW) {
4875
4876
4877
4878
4879 input->ipl4_proto = fsp->h_u.usr_ip6_spec.l4_proto;
4880 input->dst_port = fsp->h_u.tcp_ip6_spec.psrc;
4881 input->src_port = fsp->h_u.tcp_ip6_spec.pdst;
4882 memcpy(input->dst_ip6, fsp->h_u.ah_ip6_spec.ip6src,
4883 sizeof(__be32) * 4);
4884 memcpy(input->src_ip6, fsp->h_u.ah_ip6_spec.ip6dst,
4885 sizeof(__be32) * 4);
4886 } else {
4887
4888
4889
4890
4891 input->ipl4_proto = fsp->h_u.usr_ip4_spec.proto;
4892 input->dst_port = fsp->h_u.tcp_ip4_spec.psrc;
4893 input->src_port = fsp->h_u.tcp_ip4_spec.pdst;
4894 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4895 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4896 }
4897
4898 if (userdef.flex_filter) {
4899 input->flex_filter = true;
4900 input->flex_word = cpu_to_be16(userdef.flex_word);
4901 input->flex_offset = userdef.flex_offset;
4902 }
4903
4904
4905 ret = i40e_disallow_matching_filters(vsi, input);
4906 if (ret)
4907 goto free_filter_memory;
4908
4909
4910
4911
4912
4913 i40e_update_ethtool_fdir_entry(vsi, input, fsp->location, NULL);
4914 ret = i40e_add_del_fdir(vsi, input, true);
4915 if (ret)
4916 goto remove_sw_rule;
4917 return 0;
4918
4919 remove_sw_rule:
4920 hlist_del(&input->fdir_node);
4921 pf->fdir_pf_active_filters--;
4922 free_filter_memory:
4923 kfree(input);
4924 return ret;
4925 }
4926
4927
4928
4929
4930
4931
4932
4933
4934 static int i40e_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
4935 {
4936 struct i40e_netdev_priv *np = netdev_priv(netdev);
4937 struct i40e_vsi *vsi = np->vsi;
4938 struct i40e_pf *pf = vsi->back;
4939 int ret = -EOPNOTSUPP;
4940
4941 switch (cmd->cmd) {
4942 case ETHTOOL_SRXFH:
4943 ret = i40e_set_rss_hash_opt(pf, cmd);
4944 break;
4945 case ETHTOOL_SRXCLSRLINS:
4946 ret = i40e_add_fdir_ethtool(vsi, cmd);
4947 break;
4948 case ETHTOOL_SRXCLSRLDEL:
4949 ret = i40e_del_fdir_entry(vsi, cmd);
4950 break;
4951 default:
4952 break;
4953 }
4954
4955 return ret;
4956 }
4957
4958
4959
4960
4961
4962 static unsigned int i40e_max_channels(struct i40e_vsi *vsi)
4963 {
4964
4965 return vsi->alloc_queue_pairs;
4966 }
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978 static void i40e_get_channels(struct net_device *dev,
4979 struct ethtool_channels *ch)
4980 {
4981 struct i40e_netdev_priv *np = netdev_priv(dev);
4982 struct i40e_vsi *vsi = np->vsi;
4983 struct i40e_pf *pf = vsi->back;
4984
4985
4986 ch->max_combined = i40e_max_channels(vsi);
4987
4988
4989 ch->other_count = (pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0;
4990 ch->max_other = ch->other_count;
4991
4992
4993 ch->combined_count = vsi->num_queue_pairs;
4994 }
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004 static int i40e_set_channels(struct net_device *dev,
5005 struct ethtool_channels *ch)
5006 {
5007 const u8 drop = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
5008 struct i40e_netdev_priv *np = netdev_priv(dev);
5009 unsigned int count = ch->combined_count;
5010 struct i40e_vsi *vsi = np->vsi;
5011 struct i40e_pf *pf = vsi->back;
5012 struct i40e_fdir_filter *rule;
5013 struct hlist_node *node2;
5014 int new_count;
5015 int err = 0;
5016
5017
5018 if (vsi->type != I40E_VSI_MAIN)
5019 return -EINVAL;
5020
5021
5022
5023
5024 if (i40e_is_tc_mqprio_enabled(pf))
5025 return -EINVAL;
5026
5027
5028 if (!count || ch->rx_count || ch->tx_count)
5029 return -EINVAL;
5030
5031
5032 if (ch->other_count != ((pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0))
5033 return -EINVAL;
5034
5035
5036 if (count > i40e_max_channels(vsi))
5037 return -EINVAL;
5038
5039
5040
5041
5042 hlist_for_each_entry_safe(rule, node2,
5043 &pf->fdir_filter_list, fdir_node) {
5044 if (rule->dest_ctl != drop && count <= rule->q_index) {
5045 dev_warn(&pf->pdev->dev,
5046 "Existing user defined filter %d assigns flow to queue %d\n",
5047 rule->fd_id, rule->q_index);
5048 err = -EINVAL;
5049 }
5050 }
5051
5052 if (err) {
5053 dev_err(&pf->pdev->dev,
5054 "Existing filter rules must be deleted to reduce combined channel count to %d\n",
5055 count);
5056 return err;
5057 }
5058
5059
5060
5061
5062
5063
5064
5065 new_count = i40e_reconfig_rss_queues(pf, count);
5066 if (new_count > 0)
5067 return 0;
5068 else
5069 return -EINVAL;
5070 }
5071
5072
5073
5074
5075
5076
5077
5078 static u32 i40e_get_rxfh_key_size(struct net_device *netdev)
5079 {
5080 return I40E_HKEY_ARRAY_SIZE;
5081 }
5082
5083
5084
5085
5086
5087
5088
5089 static u32 i40e_get_rxfh_indir_size(struct net_device *netdev)
5090 {
5091 return I40E_HLUT_ARRAY_SIZE;
5092 }
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104 static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
5105 u8 *hfunc)
5106 {
5107 struct i40e_netdev_priv *np = netdev_priv(netdev);
5108 struct i40e_vsi *vsi = np->vsi;
5109 u8 *lut, *seed = NULL;
5110 int ret;
5111 u16 i;
5112
5113 if (hfunc)
5114 *hfunc = ETH_RSS_HASH_TOP;
5115
5116 if (!indir)
5117 return 0;
5118
5119 seed = key;
5120 lut = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
5121 if (!lut)
5122 return -ENOMEM;
5123 ret = i40e_get_rss(vsi, seed, lut, I40E_HLUT_ARRAY_SIZE);
5124 if (ret)
5125 goto out;
5126 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
5127 indir[i] = (u32)(lut[i]);
5128
5129 out:
5130 kfree(lut);
5131
5132 return ret;
5133 }
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145 static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,
5146 const u8 *key, const u8 hfunc)
5147 {
5148 struct i40e_netdev_priv *np = netdev_priv(netdev);
5149 struct i40e_vsi *vsi = np->vsi;
5150 struct i40e_pf *pf = vsi->back;
5151 u8 *seed = NULL;
5152 u16 i;
5153
5154 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
5155 return -EOPNOTSUPP;
5156
5157 if (key) {
5158 if (!vsi->rss_hkey_user) {
5159 vsi->rss_hkey_user = kzalloc(I40E_HKEY_ARRAY_SIZE,
5160 GFP_KERNEL);
5161 if (!vsi->rss_hkey_user)
5162 return -ENOMEM;
5163 }
5164 memcpy(vsi->rss_hkey_user, key, I40E_HKEY_ARRAY_SIZE);
5165 seed = vsi->rss_hkey_user;
5166 }
5167 if (!vsi->rss_lut_user) {
5168 vsi->rss_lut_user = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
5169 if (!vsi->rss_lut_user)
5170 return -ENOMEM;
5171 }
5172
5173
5174 if (indir)
5175 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
5176 vsi->rss_lut_user[i] = (u8)(indir[i]);
5177 else
5178 i40e_fill_rss_lut(pf, vsi->rss_lut_user, I40E_HLUT_ARRAY_SIZE,
5179 vsi->rss_size);
5180
5181 return i40e_config_rss(vsi, seed, vsi->rss_lut_user,
5182 I40E_HLUT_ARRAY_SIZE);
5183 }
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195 static u32 i40e_get_priv_flags(struct net_device *dev)
5196 {
5197 struct i40e_netdev_priv *np = netdev_priv(dev);
5198 struct i40e_vsi *vsi = np->vsi;
5199 struct i40e_pf *pf = vsi->back;
5200 u32 i, j, ret_flags = 0;
5201
5202 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
5203 const struct i40e_priv_flags *priv_flags;
5204
5205 priv_flags = &i40e_gstrings_priv_flags[i];
5206
5207 if (priv_flags->flag & pf->flags)
5208 ret_flags |= BIT(i);
5209 }
5210
5211 if (pf->hw.pf_id != 0)
5212 return ret_flags;
5213
5214 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
5215 const struct i40e_priv_flags *priv_flags;
5216
5217 priv_flags = &i40e_gl_gstrings_priv_flags[j];
5218
5219 if (priv_flags->flag & pf->flags)
5220 ret_flags |= BIT(i + j);
5221 }
5222
5223 return ret_flags;
5224 }
5225
5226
5227
5228
5229
5230
5231 static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
5232 {
5233 struct i40e_netdev_priv *np = netdev_priv(dev);
5234 u64 orig_flags, new_flags, changed_flags;
5235 enum i40e_admin_queue_err adq_err;
5236 struct i40e_vsi *vsi = np->vsi;
5237 struct i40e_pf *pf = vsi->back;
5238 u32 reset_needed = 0;
5239 i40e_status status;
5240 u32 i, j;
5241
5242 orig_flags = READ_ONCE(pf->flags);
5243 new_flags = orig_flags;
5244
5245 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
5246 const struct i40e_priv_flags *priv_flags;
5247
5248 priv_flags = &i40e_gstrings_priv_flags[i];
5249
5250 if (flags & BIT(i))
5251 new_flags |= priv_flags->flag;
5252 else
5253 new_flags &= ~(priv_flags->flag);
5254
5255
5256 if (priv_flags->read_only &&
5257 ((orig_flags ^ new_flags) & ~BIT(i)))
5258 return -EOPNOTSUPP;
5259 }
5260
5261 if (pf->hw.pf_id != 0)
5262 goto flags_complete;
5263
5264 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
5265 const struct i40e_priv_flags *priv_flags;
5266
5267 priv_flags = &i40e_gl_gstrings_priv_flags[j];
5268
5269 if (flags & BIT(i + j))
5270 new_flags |= priv_flags->flag;
5271 else
5272 new_flags &= ~(priv_flags->flag);
5273
5274
5275 if (priv_flags->read_only &&
5276 ((orig_flags ^ new_flags) & ~BIT(i)))
5277 return -EOPNOTSUPP;
5278 }
5279
5280 flags_complete:
5281 changed_flags = orig_flags ^ new_flags;
5282
5283 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP)
5284 reset_needed = I40E_PF_RESET_AND_REBUILD_FLAG;
5285 if (changed_flags & (I40E_FLAG_VEB_STATS_ENABLED |
5286 I40E_FLAG_LEGACY_RX | I40E_FLAG_SOURCE_PRUNING_DISABLED))
5287 reset_needed = BIT(__I40E_PF_RESET_REQUESTED);
5288
5289
5290
5291
5292
5293
5294 if ((new_flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) &&
5295 !(pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE))
5296 return -EOPNOTSUPP;
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5307 if (!(pf->hw.flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) {
5308 dev_warn(&pf->pdev->dev,
5309 "Device does not support changing FW LLDP\n");
5310 return -EOPNOTSUPP;
5311 }
5312 }
5313
5314 if (changed_flags & I40E_FLAG_RS_FEC &&
5315 pf->hw.device_id != I40E_DEV_ID_25G_SFP28 &&
5316 pf->hw.device_id != I40E_DEV_ID_25G_B) {
5317 dev_warn(&pf->pdev->dev,
5318 "Device does not support changing FEC configuration\n");
5319 return -EOPNOTSUPP;
5320 }
5321
5322 if (changed_flags & I40E_FLAG_BASE_R_FEC &&
5323 pf->hw.device_id != I40E_DEV_ID_25G_SFP28 &&
5324 pf->hw.device_id != I40E_DEV_ID_25G_B &&
5325 pf->hw.device_id != I40E_DEV_ID_KX_X722) {
5326 dev_warn(&pf->pdev->dev,
5327 "Device does not support changing FEC configuration\n");
5328 return -EOPNOTSUPP;
5329 }
5330
5331
5332
5333
5334
5335
5336
5337 if ((changed_flags & I40E_FLAG_FD_ATR_ENABLED) &&
5338 !(new_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5339 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
5340 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
5341 }
5342
5343 if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {
5344 u16 sw_flags = 0, valid_flags = 0;
5345 int ret;
5346
5347 if (!(new_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
5348 sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
5349 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
5350 ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,
5351 0, NULL);
5352 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
5353 dev_info(&pf->pdev->dev,
5354 "couldn't set switch config bits, err %s aq_err %s\n",
5355 i40e_stat_str(&pf->hw, ret),
5356 i40e_aq_str(&pf->hw,
5357 pf->hw.aq.asq_last_status));
5358
5359 }
5360 }
5361
5362 if ((changed_flags & I40E_FLAG_RS_FEC) ||
5363 (changed_flags & I40E_FLAG_BASE_R_FEC)) {
5364 u8 fec_cfg = 0;
5365
5366 if (new_flags & I40E_FLAG_RS_FEC &&
5367 new_flags & I40E_FLAG_BASE_R_FEC) {
5368 fec_cfg = I40E_AQ_SET_FEC_AUTO;
5369 } else if (new_flags & I40E_FLAG_RS_FEC) {
5370 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
5371 I40E_AQ_SET_FEC_ABILITY_RS);
5372 } else if (new_flags & I40E_FLAG_BASE_R_FEC) {
5373 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
5374 I40E_AQ_SET_FEC_ABILITY_KR);
5375 }
5376 if (i40e_set_fec_cfg(dev, fec_cfg))
5377 dev_warn(&pf->pdev->dev, "Cannot change FEC config\n");
5378 }
5379
5380 if ((changed_flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &&
5381 (orig_flags & I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED)) {
5382 dev_err(&pf->pdev->dev,
5383 "Setting link-down-on-close not supported on this port (because total-port-shutdown is enabled)\n");
5384 return -EOPNOTSUPP;
5385 }
5386
5387 if ((changed_flags & I40E_FLAG_VF_VLAN_PRUNING) &&
5388 pf->num_alloc_vfs) {
5389 dev_warn(&pf->pdev->dev,
5390 "Changing vf-vlan-pruning flag while VF(s) are active is not supported\n");
5391 return -EOPNOTSUPP;
5392 }
5393
5394 if ((changed_flags & new_flags &
5395 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &&
5396 (new_flags & I40E_FLAG_MFP_ENABLED))
5397 dev_warn(&pf->pdev->dev,
5398 "Turning on link-down-on-close flag may affect other partitions\n");
5399
5400 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5401 if (new_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5402 #ifdef CONFIG_I40E_DCB
5403 i40e_dcb_sw_default_config(pf);
5404 #endif
5405 i40e_aq_cfg_lldp_mib_change_event(&pf->hw, false, NULL);
5406 i40e_aq_stop_lldp(&pf->hw, true, false, NULL);
5407 } else {
5408 status = i40e_aq_start_lldp(&pf->hw, false, NULL);
5409 if (status) {
5410 adq_err = pf->hw.aq.asq_last_status;
5411 switch (adq_err) {
5412 case I40E_AQ_RC_EEXIST:
5413 dev_warn(&pf->pdev->dev,
5414 "FW LLDP agent is already running\n");
5415 reset_needed = 0;
5416 break;
5417 case I40E_AQ_RC_EPERM:
5418 dev_warn(&pf->pdev->dev,
5419 "Device configuration forbids SW from starting the LLDP agent.\n");
5420 return -EINVAL;
5421 case I40E_AQ_RC_EAGAIN:
5422 dev_warn(&pf->pdev->dev,
5423 "Stop FW LLDP agent command is still being processed, please try again in a second.\n");
5424 return -EBUSY;
5425 default:
5426 dev_warn(&pf->pdev->dev,
5427 "Starting FW LLDP agent failed: error: %s, %s\n",
5428 i40e_stat_str(&pf->hw,
5429 status),
5430 i40e_aq_str(&pf->hw,
5431 adq_err));
5432 return -EINVAL;
5433 }
5434 }
5435 }
5436 }
5437
5438
5439
5440
5441
5442
5443 pf->flags = new_flags;
5444
5445
5446
5447
5448 if (reset_needed)
5449 i40e_do_reset(pf, reset_needed, true);
5450
5451 return 0;
5452 }
5453
5454
5455
5456
5457
5458
5459 static int i40e_get_module_info(struct net_device *netdev,
5460 struct ethtool_modinfo *modinfo)
5461 {
5462 struct i40e_netdev_priv *np = netdev_priv(netdev);
5463 struct i40e_vsi *vsi = np->vsi;
5464 struct i40e_pf *pf = vsi->back;
5465 struct i40e_hw *hw = &pf->hw;
5466 u32 sff8472_comp = 0;
5467 u32 sff8472_swap = 0;
5468 u32 sff8636_rev = 0;
5469 i40e_status status;
5470 u32 type = 0;
5471
5472
5473 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
5474 netdev_err(vsi->netdev, "Module EEPROM memory read not supported. Please update the NVM image.\n");
5475 return -EINVAL;
5476 }
5477
5478 status = i40e_update_link_info(hw);
5479 if (status)
5480 return -EIO;
5481
5482 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
5483 netdev_err(vsi->netdev, "Cannot read module EEPROM memory. No module connected.\n");
5484 return -EINVAL;
5485 }
5486
5487 type = hw->phy.link_info.module_type[0];
5488
5489 switch (type) {
5490 case I40E_MODULE_TYPE_SFP:
5491 status = i40e_aq_get_phy_register(hw,
5492 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5493 I40E_I2C_EEPROM_DEV_ADDR, true,
5494 I40E_MODULE_SFF_8472_COMP,
5495 &sff8472_comp, NULL);
5496 if (status)
5497 return -EIO;
5498
5499 status = i40e_aq_get_phy_register(hw,
5500 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5501 I40E_I2C_EEPROM_DEV_ADDR, true,
5502 I40E_MODULE_SFF_8472_SWAP,
5503 &sff8472_swap, NULL);
5504 if (status)
5505 return -EIO;
5506
5507
5508
5509
5510 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
5511 netdev_warn(vsi->netdev, "Module address swap to access page 0xA2 is not supported.\n");
5512 modinfo->type = ETH_MODULE_SFF_8079;
5513 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5514 } else if (sff8472_comp == 0x00) {
5515
5516 modinfo->type = ETH_MODULE_SFF_8079;
5517 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5518 } else if (!(sff8472_swap & I40E_MODULE_SFF_DDM_IMPLEMENTED)) {
5519
5520
5521
5522 modinfo->type = ETH_MODULE_SFF_8079;
5523 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5524 } else {
5525 modinfo->type = ETH_MODULE_SFF_8472;
5526 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
5527 }
5528 break;
5529 case I40E_MODULE_TYPE_QSFP_PLUS:
5530
5531 status = i40e_aq_get_phy_register(hw,
5532 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5533 0, true,
5534 I40E_MODULE_REVISION_ADDR,
5535 &sff8636_rev, NULL);
5536 if (status)
5537 return -EIO;
5538
5539 if (sff8636_rev > 0x02) {
5540
5541 modinfo->type = ETH_MODULE_SFF_8636;
5542 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5543 } else {
5544 modinfo->type = ETH_MODULE_SFF_8436;
5545 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5546 }
5547 break;
5548 case I40E_MODULE_TYPE_QSFP28:
5549 modinfo->type = ETH_MODULE_SFF_8636;
5550 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5551 break;
5552 default:
5553 netdev_err(vsi->netdev, "Module type unrecognized\n");
5554 return -EINVAL;
5555 }
5556 return 0;
5557 }
5558
5559
5560
5561
5562
5563
5564
5565 static int i40e_get_module_eeprom(struct net_device *netdev,
5566 struct ethtool_eeprom *ee,
5567 u8 *data)
5568 {
5569 struct i40e_netdev_priv *np = netdev_priv(netdev);
5570 struct i40e_vsi *vsi = np->vsi;
5571 struct i40e_pf *pf = vsi->back;
5572 struct i40e_hw *hw = &pf->hw;
5573 bool is_sfp = false;
5574 i40e_status status;
5575 u32 value = 0;
5576 int i;
5577
5578 if (!ee || !ee->len || !data)
5579 return -EINVAL;
5580
5581 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
5582 is_sfp = true;
5583
5584 for (i = 0; i < ee->len; i++) {
5585 u32 offset = i + ee->offset;
5586 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
5587
5588
5589 if (is_sfp) {
5590 if (offset >= ETH_MODULE_SFF_8079_LEN) {
5591 offset -= ETH_MODULE_SFF_8079_LEN;
5592 addr = I40E_I2C_EEPROM_DEV_ADDR2;
5593 }
5594 } else {
5595 while (offset >= ETH_MODULE_SFF_8436_LEN) {
5596
5597 offset -= ETH_MODULE_SFF_8436_LEN / 2;
5598 addr++;
5599 }
5600 }
5601
5602 status = i40e_aq_get_phy_register(hw,
5603 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5604 addr, true, offset, &value, NULL);
5605 if (status)
5606 return -EIO;
5607 data[i] = value;
5608 }
5609 return 0;
5610 }
5611
5612 static int i40e_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
5613 {
5614 struct i40e_netdev_priv *np = netdev_priv(netdev);
5615 struct i40e_aq_get_phy_abilities_resp phy_cfg;
5616 enum i40e_status_code status = 0;
5617 struct i40e_vsi *vsi = np->vsi;
5618 struct i40e_pf *pf = vsi->back;
5619 struct i40e_hw *hw = &pf->hw;
5620
5621
5622 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_cfg, NULL);
5623 if (status)
5624 return -EAGAIN;
5625
5626
5627
5628
5629 if (phy_cfg.eee_capability == 0)
5630 return -EOPNOTSUPP;
5631
5632 edata->supported = SUPPORTED_Autoneg;
5633 edata->lp_advertised = edata->supported;
5634
5635
5636 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_cfg, NULL);
5637 if (status)
5638 return -EAGAIN;
5639
5640 edata->advertised = phy_cfg.eee_capability ? SUPPORTED_Autoneg : 0U;
5641 edata->eee_enabled = !!edata->advertised;
5642 edata->tx_lpi_enabled = pf->stats.tx_lpi_status;
5643
5644 edata->eee_active = pf->stats.tx_lpi_status && pf->stats.rx_lpi_status;
5645
5646 return 0;
5647 }
5648
5649 static int i40e_is_eee_param_supported(struct net_device *netdev,
5650 struct ethtool_eee *edata)
5651 {
5652 struct i40e_netdev_priv *np = netdev_priv(netdev);
5653 struct i40e_vsi *vsi = np->vsi;
5654 struct i40e_pf *pf = vsi->back;
5655 struct i40e_ethtool_not_used {
5656 u32 value;
5657 const char *name;
5658 } param[] = {
5659 {edata->advertised & ~SUPPORTED_Autoneg, "advertise"},
5660 {edata->tx_lpi_timer, "tx-timer"},
5661 {edata->tx_lpi_enabled != pf->stats.tx_lpi_status, "tx-lpi"}
5662 };
5663 int i;
5664
5665 for (i = 0; i < ARRAY_SIZE(param); i++) {
5666 if (param[i].value) {
5667 netdev_info(netdev,
5668 "EEE setting %s not supported\n",
5669 param[i].name);
5670 return -EOPNOTSUPP;
5671 }
5672 }
5673
5674 return 0;
5675 }
5676
5677 static int i40e_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
5678 {
5679 struct i40e_netdev_priv *np = netdev_priv(netdev);
5680 struct i40e_aq_get_phy_abilities_resp abilities;
5681 enum i40e_status_code status = I40E_SUCCESS;
5682 struct i40e_aq_set_phy_config config;
5683 struct i40e_vsi *vsi = np->vsi;
5684 struct i40e_pf *pf = vsi->back;
5685 struct i40e_hw *hw = &pf->hw;
5686 __le16 eee_capability;
5687
5688
5689 if (i40e_is_eee_param_supported(netdev, edata))
5690 return -EOPNOTSUPP;
5691
5692
5693 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
5694 NULL);
5695 if (status)
5696 return -EAGAIN;
5697
5698
5699
5700
5701 if (abilities.eee_capability == 0)
5702 return -EOPNOTSUPP;
5703
5704
5705 eee_capability = abilities.eee_capability;
5706
5707
5708 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
5709 NULL);
5710 if (status)
5711 return -EAGAIN;
5712
5713
5714 config.phy_type = abilities.phy_type;
5715 config.phy_type_ext = abilities.phy_type_ext;
5716 config.link_speed = abilities.link_speed;
5717 config.abilities = abilities.abilities |
5718 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
5719 config.eeer = abilities.eeer_val;
5720 config.low_power_ctrl = abilities.d3_lpan;
5721 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
5722 I40E_AQ_PHY_FEC_CONFIG_MASK;
5723
5724
5725 if (edata->eee_enabled) {
5726 config.eee_capability = eee_capability;
5727 config.eeer |= cpu_to_le32(I40E_PRTPM_EEER_TX_LPI_EN_MASK);
5728 } else {
5729 config.eee_capability = 0;
5730 config.eeer &= cpu_to_le32(~I40E_PRTPM_EEER_TX_LPI_EN_MASK);
5731 }
5732
5733
5734 status = i40e_aq_set_phy_config(hw, &config, NULL);
5735 if (status)
5736 return -EAGAIN;
5737
5738 return 0;
5739 }
5740
5741 static const struct ethtool_ops i40e_ethtool_recovery_mode_ops = {
5742 .get_drvinfo = i40e_get_drvinfo,
5743 .set_eeprom = i40e_set_eeprom,
5744 .get_eeprom_len = i40e_get_eeprom_len,
5745 .get_eeprom = i40e_get_eeprom,
5746 };
5747
5748 static const struct ethtool_ops i40e_ethtool_ops = {
5749 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5750 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
5751 ETHTOOL_COALESCE_USE_ADAPTIVE |
5752 ETHTOOL_COALESCE_RX_USECS_HIGH |
5753 ETHTOOL_COALESCE_TX_USECS_HIGH,
5754 .get_drvinfo = i40e_get_drvinfo,
5755 .get_regs_len = i40e_get_regs_len,
5756 .get_regs = i40e_get_regs,
5757 .nway_reset = i40e_nway_reset,
5758 .get_link = ethtool_op_get_link,
5759 .get_wol = i40e_get_wol,
5760 .set_wol = i40e_set_wol,
5761 .set_eeprom = i40e_set_eeprom,
5762 .get_eeprom_len = i40e_get_eeprom_len,
5763 .get_eeprom = i40e_get_eeprom,
5764 .get_ringparam = i40e_get_ringparam,
5765 .set_ringparam = i40e_set_ringparam,
5766 .get_pauseparam = i40e_get_pauseparam,
5767 .set_pauseparam = i40e_set_pauseparam,
5768 .get_msglevel = i40e_get_msglevel,
5769 .set_msglevel = i40e_set_msglevel,
5770 .get_rxnfc = i40e_get_rxnfc,
5771 .set_rxnfc = i40e_set_rxnfc,
5772 .self_test = i40e_diag_test,
5773 .get_strings = i40e_get_strings,
5774 .get_eee = i40e_get_eee,
5775 .set_eee = i40e_set_eee,
5776 .set_phys_id = i40e_set_phys_id,
5777 .get_sset_count = i40e_get_sset_count,
5778 .get_ethtool_stats = i40e_get_ethtool_stats,
5779 .get_coalesce = i40e_get_coalesce,
5780 .set_coalesce = i40e_set_coalesce,
5781 .get_rxfh_key_size = i40e_get_rxfh_key_size,
5782 .get_rxfh_indir_size = i40e_get_rxfh_indir_size,
5783 .get_rxfh = i40e_get_rxfh,
5784 .set_rxfh = i40e_set_rxfh,
5785 .get_channels = i40e_get_channels,
5786 .set_channels = i40e_set_channels,
5787 .get_module_info = i40e_get_module_info,
5788 .get_module_eeprom = i40e_get_module_eeprom,
5789 .get_ts_info = i40e_get_ts_info,
5790 .get_priv_flags = i40e_get_priv_flags,
5791 .set_priv_flags = i40e_set_priv_flags,
5792 .get_per_queue_coalesce = i40e_get_per_queue_coalesce,
5793 .set_per_queue_coalesce = i40e_set_per_queue_coalesce,
5794 .get_link_ksettings = i40e_get_link_ksettings,
5795 .set_link_ksettings = i40e_set_link_ksettings,
5796 .get_fecparam = i40e_get_fec_param,
5797 .set_fecparam = i40e_set_fec_param,
5798 .flash_device = i40e_ddp_flash,
5799 };
5800
5801 void i40e_set_ethtool_ops(struct net_device *netdev)
5802 {
5803 struct i40e_netdev_priv *np = netdev_priv(netdev);
5804 struct i40e_pf *pf = np->vsi->back;
5805
5806 if (!test_bit(__I40E_RECOVERY_MODE, pf->state))
5807 netdev->ethtool_ops = &i40e_ethtool_ops;
5808 else
5809 netdev->ethtool_ops = &i40e_ethtool_recovery_mode_ops;
5810 }