intel/i40e/i40e_diag.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 2013 - 2018 Intel Corporation. */
0003
0004 #include "i40e_diag.h"
0005 #include "i40e_prototype.h"
0006
0007 /**
0008  * i40e_diag_reg_pattern_test
0009  * @hw: pointer to the hw struct
0010  * @reg: reg to be tested
0011  * @mask: bits to be touched
0012  **/
0013 static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
0014                             u32 reg, u32 mask)
0015 {
0016     static const u32 patterns[] = {
0017         0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
0018     };
0019     u32 pat, val, orig_val;
0020     int i;
0021
0022     orig_val = rd32(hw, reg);
0023     for (i = 0; i < ARRAY_SIZE(patterns); i++) {
0024         pat = patterns[i];
0025         wr32(hw, reg, (pat & mask));
0026         val = rd32(hw, reg);
0027         if ((val & mask) != (pat & mask)) {
0028             i40e_debug(hw, I40E_DEBUG_DIAG,
0029                    "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
0030                    __func__, reg, pat, val);
0031             return I40E_ERR_DIAG_TEST_FAILED;
0032         }
0033     }
0034
0035     wr32(hw, reg, orig_val);
0036     val = rd32(hw, reg);
0037     if (val != orig_val) {
0038         i40e_debug(hw, I40E_DEBUG_DIAG,
0039                "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
0040                __func__, reg, orig_val, val);
0041         return I40E_ERR_DIAG_TEST_FAILED;
0042     }
0043
0044     return 0;
0045 }
0046
0047 struct i40e_diag_reg_test_info i40e_reg_list[] = {
0048     /* offset               mask         elements   stride */
0049     {I40E_QTX_CTL(0),       0x0000FFBF, 1,
0050         I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
0051     {I40E_PFINT_ITR0(0),    0x00000FFF, 3,
0052         I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
0053     {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1,
0054         I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
0055     {I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1,
0056         I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
0057     {I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1,
0058         I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
0059     {I40E_PFINT_STAT_CTL0,  0x0000000C, 1, 0},
0060     {I40E_PFINT_LNKLST0,    0x00001FFF, 1, 0},
0061     {I40E_PFINT_LNKLSTN(0), 0x000007FF, 1,
0062         I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
0063     {I40E_QINT_TQCTL(0),    0x000000FF, 1,
0064         I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
0065     {I40E_QINT_RQCTL(0),    0x000000FF, 1,
0066         I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
0067     {I40E_PFINT_ICR0_ENA,   0xF7F20000, 1, 0},
0068     { 0 }
0069 };
0070
0071 /**
0072  * i40e_diag_reg_test
0073  * @hw: pointer to the hw struct
0074  *
0075  * Perform registers diagnostic test
0076  **/
0077 i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
0078 {
0079     i40e_status ret_code = 0;
0080     u32 reg, mask;
0081     u32 i, j;
0082
0083     for (i = 0; i40e_reg_list[i].offset != 0 &&
0084                          !ret_code; i++) {
0085
0086         /* set actual reg range for dynamically allocated resources */
0087         if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
0088             hw->func_caps.num_tx_qp != 0)
0089             i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
0090         if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
0091              i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
0092              i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
0093              i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
0094              i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
0095             hw->func_caps.num_msix_vectors != 0)
0096             i40e_reg_list[i].elements =
0097                 hw->func_caps.num_msix_vectors - 1;
0098
0099         /* test register access */
0100         mask = i40e_reg_list[i].mask;
0101         for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) {
0102             reg = i40e_reg_list[i].offset +
0103                   (j * i40e_reg_list[i].stride);
0104             ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
0105         }
0106     }
0107
0108     return ret_code;
0109 }
0110
0111 /**
0112  * i40e_diag_eeprom_test
0113  * @hw: pointer to the hw struct
0114  *
0115  * Perform EEPROM diagnostic test
0116  **/
0117 i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
0118 {
0119     i40e_status ret_code;
0120     u16 reg_val;
0121
0122     /* read NVM control word and if NVM valid, validate EEPROM checksum*/
0123     ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
0124     if (!ret_code &&
0125         ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
0126          BIT(I40E_SR_CONTROL_WORD_1_SHIFT)))
0127         return i40e_validate_nvm_checksum(hw, NULL);
0128     else
0129         return I40E_ERR_DIAG_TEST_FAILED;
0130 }