intel/i40e/i40e_dcb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2013 - 2021 Intel Corporation. */
0003
0004 #ifndef _I40E_DCB_H_
0005 #define _I40E_DCB_H_
0006
0007 #include "i40e_type.h"
0008
0009 #define I40E_DCBX_STATUS_NOT_STARTED    0
0010 #define I40E_DCBX_STATUS_IN_PROGRESS    1
0011 #define I40E_DCBX_STATUS_DONE       2
0012 #define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
0013 #define I40E_DCBX_STATUS_DISABLED   7
0014
0015 #define I40E_TLV_TYPE_END       0
0016 #define I40E_TLV_TYPE_ORG       127
0017
0018 #define I40E_IEEE_8021QAZ_OUI       0x0080C2
0019 #define I40E_IEEE_SUBTYPE_ETS_CFG   9
0020 #define I40E_IEEE_SUBTYPE_ETS_REC   10
0021 #define I40E_IEEE_SUBTYPE_PFC_CFG   11
0022 #define I40E_IEEE_SUBTYPE_APP_PRI   12
0023
0024 #define I40E_CEE_DCBX_OUI       0x001b21
0025 #define I40E_CEE_DCBX_TYPE      2
0026
0027 #define I40E_CEE_SUBTYPE_CTRL       1
0028 #define I40E_CEE_SUBTYPE_PG_CFG     2
0029 #define I40E_CEE_SUBTYPE_PFC_CFG    3
0030 #define I40E_CEE_SUBTYPE_APP_PRI    4
0031
0032 #define I40E_CEE_MAX_FEAT_TYPE      3
0033 #define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET   0x2B
0034 #define I40E_LLDP_CURRENT_STATUS_X722_OFFSET    0x31
0035 #define I40E_LLDP_CURRENT_STATUS_OFFSET     1
0036 #define I40E_LLDP_CURRENT_STATUS_SIZE       1
0037
0038 /* Defines for LLDP TLV header */
0039 #define I40E_LLDP_TLV_LEN_SHIFT     0
0040 #define I40E_LLDP_TLV_LEN_MASK      (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
0041 #define I40E_LLDP_TLV_TYPE_SHIFT    9
0042 #define I40E_LLDP_TLV_TYPE_MASK     (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
0043 #define I40E_LLDP_TLV_SUBTYPE_SHIFT 0
0044 #define I40E_LLDP_TLV_SUBTYPE_MASK  (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
0045 #define I40E_LLDP_TLV_OUI_SHIFT     8
0046 #define I40E_LLDP_TLV_OUI_MASK      (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
0047
0048 /* Defines for IEEE ETS TLV */
0049 #define I40E_IEEE_ETS_MAXTC_SHIFT   0
0050 #define I40E_IEEE_ETS_MAXTC_MASK    (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
0051 #define I40E_IEEE_ETS_CBS_SHIFT     6
0052 #define I40E_IEEE_ETS_CBS_MASK      BIT(I40E_IEEE_ETS_CBS_SHIFT)
0053 #define I40E_IEEE_ETS_WILLING_SHIFT 7
0054 #define I40E_IEEE_ETS_WILLING_MASK  BIT(I40E_IEEE_ETS_WILLING_SHIFT)
0055 #define I40E_IEEE_ETS_PRIO_0_SHIFT  0
0056 #define I40E_IEEE_ETS_PRIO_0_MASK   (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
0057 #define I40E_IEEE_ETS_PRIO_1_SHIFT  4
0058 #define I40E_IEEE_ETS_PRIO_1_MASK   (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
0059 #define I40E_CEE_PGID_PRIO_0_SHIFT  0
0060 #define I40E_CEE_PGID_PRIO_0_MASK   (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
0061 #define I40E_CEE_PGID_PRIO_1_SHIFT  4
0062 #define I40E_CEE_PGID_PRIO_1_MASK   (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
0063 #define I40E_CEE_PGID_STRICT        15
0064
0065 /* Defines for IEEE TSA types */
0066 #define I40E_IEEE_TSA_STRICT        0
0067 #define I40E_IEEE_TSA_ETS       2
0068
0069 /* Defines for IEEE PFC TLV */
0070 #define I40E_DCB_PFC_ENABLED        2
0071 #define I40E_DCB_PFC_FORCED_NUM_TC  2
0072 #define I40E_IEEE_PFC_CAP_SHIFT     0
0073 #define I40E_IEEE_PFC_CAP_MASK      (0xF << I40E_IEEE_PFC_CAP_SHIFT)
0074 #define I40E_IEEE_PFC_MBC_SHIFT     6
0075 #define I40E_IEEE_PFC_MBC_MASK      BIT(I40E_IEEE_PFC_MBC_SHIFT)
0076 #define I40E_IEEE_PFC_WILLING_SHIFT 7
0077 #define I40E_IEEE_PFC_WILLING_MASK  BIT(I40E_IEEE_PFC_WILLING_SHIFT)
0078
0079 /* Defines for IEEE APP TLV */
0080 #define I40E_IEEE_APP_SEL_SHIFT     0
0081 #define I40E_IEEE_APP_SEL_MASK      (0x7 << I40E_IEEE_APP_SEL_SHIFT)
0082 #define I40E_IEEE_APP_PRIO_SHIFT    5
0083 #define I40E_IEEE_APP_PRIO_MASK     (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
0084
0085 /* TLV definitions for preparing MIB */
0086 #define I40E_TLV_ID_CHASSIS_ID      0
0087 #define I40E_TLV_ID_PORT_ID     1
0088 #define I40E_TLV_ID_TIME_TO_LIVE    2
0089 #define I40E_IEEE_TLV_ID_ETS_CFG    3
0090 #define I40E_IEEE_TLV_ID_ETS_REC    4
0091 #define I40E_IEEE_TLV_ID_PFC_CFG    5
0092 #define I40E_IEEE_TLV_ID_APP_PRI    6
0093 #define I40E_TLV_ID_END_OF_LLDPPDU  7
0094 #define I40E_TLV_ID_START       I40E_IEEE_TLV_ID_ETS_CFG
0095
0096 #define I40E_IEEE_TLV_HEADER_LENGTH 2
0097 #define I40E_IEEE_ETS_TLV_LENGTH    25
0098 #define I40E_IEEE_PFC_TLV_LENGTH    6
0099 #define I40E_IEEE_APP_TLV_LENGTH    11
0100
0101 /* Defines for default SW DCB config */
0102 #define I40E_IEEE_DEFAULT_ETS_TCBW  100
0103 #define I40E_IEEE_DEFAULT_ETS_WILLING   1
0104 #define I40E_IEEE_DEFAULT_PFC_WILLING   1
0105 #define I40E_IEEE_DEFAULT_NUM_APPS  1
0106 #define I40E_IEEE_DEFAULT_APP_PRIO  3
0107
0108 #pragma pack(1)
0109 /* IEEE 802.1AB LLDP Organization specific TLV */
0110 struct i40e_lldp_org_tlv {
0111     __be16 typelength;
0112     __be32 ouisubtype;
0113     u8 tlvinfo[1];
0114 };
0115
0116 struct i40e_cee_tlv_hdr {
0117     __be16 typelen;
0118     u8 operver;
0119     u8 maxver;
0120 };
0121
0122 struct i40e_cee_ctrl_tlv {
0123     struct i40e_cee_tlv_hdr hdr;
0124     __be32 seqno;
0125     __be32 ackno;
0126 };
0127
0128 struct i40e_cee_feat_tlv {
0129     struct i40e_cee_tlv_hdr hdr;
0130     u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
0131 #define I40E_CEE_FEAT_TLV_ENABLE_MASK   0x80
0132 #define I40E_CEE_FEAT_TLV_WILLING_MASK  0x40
0133 #define I40E_CEE_FEAT_TLV_ERR_MASK  0x20
0134     u8 subtype;
0135     u8 tlvinfo[1];
0136 };
0137
0138 struct i40e_cee_app_prio {
0139     __be16 protocol;
0140     u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
0141 #define I40E_CEE_APP_SELECTOR_MASK  0x03
0142     __be16 lower_oui;
0143     u8 prio_map;
0144 };
0145 #pragma pack()
0146
0147 enum i40e_get_fw_lldp_status_resp {
0148     I40E_GET_FW_LLDP_STATUS_DISABLED = 0,
0149     I40E_GET_FW_LLDP_STATUS_ENABLED = 1
0150 };
0151
0152 /* Data structures to pass for SW DCBX */
0153 struct i40e_rx_pb_config {
0154     u32 shared_pool_size;
0155     u32 shared_pool_high_wm;
0156     u32 shared_pool_low_wm;
0157     u32 shared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS];
0158     u32 shared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS];
0159     u32 tc_pool_size[I40E_MAX_TRAFFIC_CLASS];
0160     u32 tc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS];
0161     u32 tc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS];
0162 };
0163
0164 enum i40e_dcb_arbiter_mode {
0165     I40E_DCB_ARB_MODE_STRICT_PRIORITY = 0,
0166     I40E_DCB_ARB_MODE_ROUND_ROBIN = 1
0167 };
0168
0169 #define I40E_DCB_DEFAULT_MAX_EXPONENT       0xB
0170 #define I40E_DEFAULT_PAUSE_TIME         0xffff
0171 #define I40E_MAX_FRAME_SIZE         4608 /* 4.5 KB */
0172
0173 #define I40E_DEVICE_RPB_SIZE            968000 /* 968 KB */
0174
0175 /* BitTimes (BT) conversion */
0176 #define I40E_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
0177 #define I40E_B2BT(BT) ((BT) * 8)
0178 #define I40E_BT2B(BT) (((BT) + (8 - 1)) / 8)
0179
0180 /* Max Frame(TC) = MFS(max) + MFS(TC) */
0181 #define I40E_MAX_FRAME_TC(mfs_max, mfs_tc)  I40E_B2BT((mfs_max) + (mfs_tc))
0182
0183 /* EEE Tx LPI Exit time in Bit Times */
0184 #define I40E_EEE_TX_LPI_EXIT_TIME       142500
0185
0186 /* PCI Round Trip Time in Bit Times */
0187 #define I40E_PCIRTT_LINK_SPEED_10G      20000
0188 #define I40E_PCIRTT_BYTE_LINK_SPEED_20G     40000
0189 #define I40E_PCIRTT_BYTE_LINK_SPEED_40G     80000
0190
0191 /* PFC Frame Delay Bit Times */
0192 #define I40E_PFC_FRAME_DELAY            672
0193
0194 /* Worst case Cable (10GBase-T) Delay Bit Times */
0195 #define I40E_CABLE_DELAY            5556
0196
0197 /* Higher Layer Delay @10G Bit Times */
0198 #define I40E_HIGHER_LAYER_DELAY_10G     6144
0199
0200 /* Interface Delays in Bit Times */
0201 /* TODO: Add for other link speeds 20G/40G/etc. */
0202 #define I40E_INTERFACE_DELAY_10G_MAC_CONTROL    8192
0203 #define I40E_INTERFACE_DELAY_10G_MAC        8192
0204 #define I40E_INTERFACE_DELAY_10G_RS     8192
0205
0206 #define I40E_INTERFACE_DELAY_XGXS       2048
0207 #define I40E_INTERFACE_DELAY_XAUI       2048
0208
0209 #define I40E_INTERFACE_DELAY_10G_BASEX_PCS  2048
0210 #define I40E_INTERFACE_DELAY_10G_BASER_PCS  3584
0211 #define I40E_INTERFACE_DELAY_LX4_PMD        512
0212 #define I40E_INTERFACE_DELAY_CX4_PMD        512
0213 #define I40E_INTERFACE_DELAY_SERIAL_PMA     512
0214 #define I40E_INTERFACE_DELAY_PMD        512
0215
0216 #define I40E_INTERFACE_DELAY_10G_BASET      25600
0217
0218 /* Hardware RX DCB config related defines */
0219 #define I40E_DCB_1_PORT_THRESHOLD       0xF
0220 #define I40E_DCB_1_PORT_FIFO_SIZE       0x10
0221 #define I40E_DCB_2_PORT_THRESHOLD_LOW_NUM_TC    0xF
0222 #define I40E_DCB_2_PORT_FIFO_SIZE_LOW_NUM_TC    0x10
0223 #define I40E_DCB_2_PORT_THRESHOLD_HIGH_NUM_TC   0xC
0224 #define I40E_DCB_2_PORT_FIFO_SIZE_HIGH_NUM_TC   0x8
0225 #define I40E_DCB_4_PORT_THRESHOLD_LOW_NUM_TC    0x9
0226 #define I40E_DCB_4_PORT_FIFO_SIZE_LOW_NUM_TC    0x8
0227 #define I40E_DCB_4_PORT_THRESHOLD_HIGH_NUM_TC   0x6
0228 #define I40E_DCB_4_PORT_FIFO_SIZE_HIGH_NUM_TC   0x4
0229 #define I40E_DCB_WATERMARK_START_FACTOR     0x2
0230
0231 /* delay values for with 10G BaseT in Bit Times */
0232 #define I40E_INTERFACE_DELAY_10G_COPPER \
0233     (I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \
0234      + I40E_INTERFACE_DELAY_10G_BASET)
0235 #define I40E_DV_TC(mfs_max, mfs_tc) \
0236         ((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \
0237          + I40E_PFC_FRAME_DELAY \
0238          + (2 * I40E_CABLE_DELAY) \
0239          + (2 * I40E_INTERFACE_DELAY_10G_COPPER) \
0240          + I40E_HIGHER_LAYER_DELAY_10G)
0241 static inline u32 I40E_STD_DV_TC(u32 mfs_max, u32 mfs_tc)
0242 {
0243     return I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max);
0244 }
0245
0246 /* APIs for SW DCBX */
0247 void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,
0248                 enum i40e_dcb_arbiter_mode ets_mode,
0249                 enum i40e_dcb_arbiter_mode non_ets_mode,
0250                 u32 max_exponent, u8 lltc_map);
0251 void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,
0252                        u8 num_tc, u8 num_ports);
0253 void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,
0254                 u8 pfc_en, u8 *prio_tc);
0255 void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc);
0256 u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw);
0257 void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,
0258                   u8 *mode, u8 *prio_type);
0259 void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc);
0260 void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,
0261                       u8 num_ports, bool eee_enabled,
0262                       u8 pfc_en, u32 *mfs_tc,
0263                       struct i40e_rx_pb_config *pb_cfg);
0264 void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,
0265                   struct i40e_rx_pb_config *old_pb_cfg,
0266                   struct i40e_rx_pb_config *new_pb_cfg);
0267 i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,
0268                  u16 *status);
0269 i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
0270                     struct i40e_dcbx_config *dcbcfg);
0271 i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
0272                    u8 bridgetype,
0273                    struct i40e_dcbx_config *dcbcfg);
0274 i40e_status i40e_get_dcb_config(struct i40e_hw *hw);
0275 i40e_status i40e_init_dcb(struct i40e_hw *hw,
0276               bool enable_mib_change);
0277 enum i40e_status_code
0278 i40e_get_fw_lldp_status(struct i40e_hw *hw,
0279             enum i40e_get_fw_lldp_status_resp *lldp_status);
0280 i40e_status i40e_set_dcb_config(struct i40e_hw *hw);
0281 i40e_status i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
0282                     struct i40e_dcbx_config *dcbcfg);
0283 #endif /* _I40E_DCB_H_ */