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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2013 - 2021 Intel Corporation. */
0003 
0004 #ifndef _I40E_H_
0005 #define _I40E_H_
0006 
0007 #include <net/tcp.h>
0008 #include <net/udp.h>
0009 #include <linux/types.h>
0010 #include <linux/errno.h>
0011 #include <linux/module.h>
0012 #include <linux/pci.h>
0013 #include <linux/aer.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/ioport.h>
0016 #include <linux/iommu.h>
0017 #include <linux/slab.h>
0018 #include <linux/list.h>
0019 #include <linux/hashtable.h>
0020 #include <linux/string.h>
0021 #include <linux/in.h>
0022 #include <linux/ip.h>
0023 #include <linux/sctp.h>
0024 #include <linux/pkt_sched.h>
0025 #include <linux/ipv6.h>
0026 #include <net/checksum.h>
0027 #include <net/ip6_checksum.h>
0028 #include <linux/ethtool.h>
0029 #include <linux/if_vlan.h>
0030 #include <linux/if_macvlan.h>
0031 #include <linux/if_bridge.h>
0032 #include <linux/clocksource.h>
0033 #include <linux/net_tstamp.h>
0034 #include <linux/ptp_clock_kernel.h>
0035 #include <net/pkt_cls.h>
0036 #include <net/tc_act/tc_gact.h>
0037 #include <net/tc_act/tc_mirred.h>
0038 #include <net/udp_tunnel.h>
0039 #include <net/xdp_sock.h>
0040 #include <linux/bitfield.h>
0041 #include "i40e_type.h"
0042 #include "i40e_prototype.h"
0043 #include <linux/net/intel/i40e_client.h>
0044 #include <linux/avf/virtchnl.h>
0045 #include "i40e_virtchnl_pf.h"
0046 #include "i40e_txrx.h"
0047 #include "i40e_dcb.h"
0048 
0049 /* Useful i40e defaults */
0050 #define I40E_MAX_VEB            16
0051 
0052 #define I40E_MAX_NUM_DESCRIPTORS    4096
0053 #define I40E_MAX_CSR_SPACE      (4 * 1024 * 1024 - 64 * 1024)
0054 #define I40E_DEFAULT_NUM_DESCRIPTORS    512
0055 #define I40E_REQ_DESCRIPTOR_MULTIPLE    32
0056 #define I40E_MIN_NUM_DESCRIPTORS    64
0057 #define I40E_MIN_MSIX           2
0058 #define I40E_DEFAULT_NUM_VMDQ_VSI   8 /* max 256 VSIs */
0059 #define I40E_MIN_VSI_ALLOC      83 /* LAN, ATR, FCOE, 64 VF */
0060 /* max 16 qps */
0061 #define i40e_default_queues_per_vmdq(pf) \
0062         (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
0063 #define I40E_DEFAULT_QUEUES_PER_VF  4
0064 #define I40E_MAX_VF_QUEUES      16
0065 #define i40e_pf_get_max_q_per_tc(pf) \
0066         (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
0067 #define I40E_FDIR_RING_COUNT        32
0068 #define I40E_MAX_AQ_BUF_SIZE        4096
0069 #define I40E_AQ_LEN         256
0070 #define I40E_MIN_ARQ_LEN        1
0071 #define I40E_MIN_ASQ_LEN        2
0072 #define I40E_AQ_WORK_LIMIT      66 /* max number of VFs + a little */
0073 #define I40E_MAX_USER_PRIORITY      8
0074 #define I40E_DEFAULT_TRAFFIC_CLASS  BIT(0)
0075 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
0076 #define I40E_INT_NAME_STR_LEN       (IFNAMSIZ + 16)
0077 
0078 #define I40E_NVM_VERSION_LO_SHIFT   0
0079 #define I40E_NVM_VERSION_LO_MASK    (0xff << I40E_NVM_VERSION_LO_SHIFT)
0080 #define I40E_NVM_VERSION_HI_SHIFT   12
0081 #define I40E_NVM_VERSION_HI_MASK    (0xf << I40E_NVM_VERSION_HI_SHIFT)
0082 #define I40E_OEM_VER_BUILD_MASK     0xffff
0083 #define I40E_OEM_VER_PATCH_MASK     0xff
0084 #define I40E_OEM_VER_BUILD_SHIFT    8
0085 #define I40E_OEM_VER_SHIFT      24
0086 #define I40E_PHY_DEBUG_ALL \
0087     (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
0088     I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
0089 
0090 #define I40E_OEM_EETRACK_ID     0xffffffff
0091 #define I40E_OEM_GEN_SHIFT      24
0092 #define I40E_OEM_SNAP_MASK      0x00ff0000
0093 #define I40E_OEM_SNAP_SHIFT     16
0094 #define I40E_OEM_RELEASE_MASK       0x0000ffff
0095 
0096 #define I40E_RX_DESC(R, i)  \
0097     (&(((union i40e_rx_desc *)((R)->desc))[i]))
0098 #define I40E_TX_DESC(R, i)  \
0099     (&(((struct i40e_tx_desc *)((R)->desc))[i]))
0100 #define I40E_TX_CTXTDESC(R, i)  \
0101     (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
0102 #define I40E_TX_FDIRDESC(R, i)  \
0103     (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
0104 
0105 /* BW rate limiting */
0106 #define I40E_BW_CREDIT_DIVISOR      50 /* 50Mbps per BW credit */
0107 #define I40E_BW_MBPS_DIVISOR        125000 /* rate / (1000000 / 8) Mbps */
0108 #define I40E_MAX_BW_INACTIVE_ACCUM  4 /* accumulate 4 credits max */
0109 
0110 /* driver state flags */
0111 enum i40e_state_t {
0112     __I40E_TESTING,
0113     __I40E_CONFIG_BUSY,
0114     __I40E_CONFIG_DONE,
0115     __I40E_DOWN,
0116     __I40E_SERVICE_SCHED,
0117     __I40E_ADMINQ_EVENT_PENDING,
0118     __I40E_MDD_EVENT_PENDING,
0119     __I40E_VFLR_EVENT_PENDING,
0120     __I40E_RESET_RECOVERY_PENDING,
0121     __I40E_TIMEOUT_RECOVERY_PENDING,
0122     __I40E_MISC_IRQ_REQUESTED,
0123     __I40E_RESET_INTR_RECEIVED,
0124     __I40E_REINIT_REQUESTED,
0125     __I40E_PF_RESET_REQUESTED,
0126     __I40E_PF_RESET_AND_REBUILD_REQUESTED,
0127     __I40E_CORE_RESET_REQUESTED,
0128     __I40E_GLOBAL_RESET_REQUESTED,
0129     __I40E_EMP_RESET_INTR_RECEIVED,
0130     __I40E_SUSPENDED,
0131     __I40E_PTP_TX_IN_PROGRESS,
0132     __I40E_BAD_EEPROM,
0133     __I40E_DOWN_REQUESTED,
0134     __I40E_FD_FLUSH_REQUESTED,
0135     __I40E_FD_ATR_AUTO_DISABLED,
0136     __I40E_FD_SB_AUTO_DISABLED,
0137     __I40E_RESET_FAILED,
0138     __I40E_PORT_SUSPENDED,
0139     __I40E_VF_DISABLE,
0140     __I40E_MACVLAN_SYNC_PENDING,
0141     __I40E_TEMP_LINK_POLLING,
0142     __I40E_CLIENT_SERVICE_REQUESTED,
0143     __I40E_CLIENT_L2_CHANGE,
0144     __I40E_CLIENT_RESET,
0145     __I40E_VIRTCHNL_OP_PENDING,
0146     __I40E_RECOVERY_MODE,
0147     __I40E_VF_RESETS_DISABLED,  /* disable resets during i40e_remove */
0148     __I40E_IN_REMOVE,
0149     __I40E_VFS_RELEASING,
0150     /* This must be last as it determines the size of the BITMAP */
0151     __I40E_STATE_SIZE__,
0152 };
0153 
0154 #define I40E_PF_RESET_FLAG  BIT_ULL(__I40E_PF_RESET_REQUESTED)
0155 #define I40E_PF_RESET_AND_REBUILD_FLAG  \
0156     BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
0157 
0158 /* VSI state flags */
0159 enum i40e_vsi_state_t {
0160     __I40E_VSI_DOWN,
0161     __I40E_VSI_NEEDS_RESTART,
0162     __I40E_VSI_SYNCING_FILTERS,
0163     __I40E_VSI_OVERFLOW_PROMISC,
0164     __I40E_VSI_REINIT_REQUESTED,
0165     __I40E_VSI_DOWN_REQUESTED,
0166     __I40E_VSI_RELEASING,
0167     /* This must be last as it determines the size of the BITMAP */
0168     __I40E_VSI_STATE_SIZE__,
0169 };
0170 
0171 enum i40e_interrupt_policy {
0172     I40E_INTERRUPT_BEST_CASE,
0173     I40E_INTERRUPT_MEDIUM,
0174     I40E_INTERRUPT_LOWEST
0175 };
0176 
0177 struct i40e_lump_tracking {
0178     u16 num_entries;
0179     u16 list[0];
0180 #define I40E_PILE_VALID_BIT  0x8000
0181 #define I40E_IWARP_IRQ_PILE_ID  (I40E_PILE_VALID_BIT - 2)
0182 };
0183 
0184 #define I40E_DEFAULT_ATR_SAMPLE_RATE    20
0185 #define I40E_FDIR_MAX_RAW_PACKET_SIZE   512
0186 #define I40E_FDIR_BUFFER_FULL_MARGIN    10
0187 #define I40E_FDIR_BUFFER_HEAD_ROOM  32
0188 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
0189 
0190 #define I40E_HKEY_ARRAY_SIZE    ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
0191 #define I40E_HLUT_ARRAY_SIZE    ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
0192 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
0193 
0194 enum i40e_fd_stat_idx {
0195     I40E_FD_STAT_ATR,
0196     I40E_FD_STAT_SB,
0197     I40E_FD_STAT_ATR_TUNNEL,
0198     I40E_FD_STAT_PF_COUNT
0199 };
0200 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
0201 #define I40E_FD_ATR_STAT_IDX(pf_id) \
0202             (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
0203 #define I40E_FD_SB_STAT_IDX(pf_id)  \
0204             (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
0205 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
0206             (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
0207 
0208 /* The following structure contains the data parsed from the user-defined
0209  * field of the ethtool_rx_flow_spec structure.
0210  */
0211 struct i40e_rx_flow_userdef {
0212     bool flex_filter;
0213     u16 flex_word;
0214     u16 flex_offset;
0215 };
0216 
0217 struct i40e_fdir_filter {
0218     struct hlist_node fdir_node;
0219     /* filter ipnut set */
0220     u8 flow_type;
0221     u8 ipl4_proto;
0222     /* TX packet view of src and dst */
0223     __be32 dst_ip;
0224     __be32 src_ip;
0225     __be32 dst_ip6[4];
0226     __be32 src_ip6[4];
0227     __be16 src_port;
0228     __be16 dst_port;
0229     __be32 sctp_v_tag;
0230 
0231     __be16 vlan_etype;
0232     __be16 vlan_tag;
0233     /* Flexible data to match within the packet payload */
0234     __be16 flex_word;
0235     u16 flex_offset;
0236     bool flex_filter;
0237 
0238     /* filter control */
0239     u16 q_index;
0240     u8  flex_off;
0241     u8  pctype;
0242     u16 dest_vsi;
0243     u8  dest_ctl;
0244     u8  fd_status;
0245     u16 cnt_index;
0246     u32 fd_id;
0247 };
0248 
0249 #define I40E_CLOUD_FIELD_OMAC       BIT(0)
0250 #define I40E_CLOUD_FIELD_IMAC       BIT(1)
0251 #define I40E_CLOUD_FIELD_IVLAN      BIT(2)
0252 #define I40E_CLOUD_FIELD_TEN_ID     BIT(3)
0253 #define I40E_CLOUD_FIELD_IIP        BIT(4)
0254 
0255 #define I40E_CLOUD_FILTER_FLAGS_OMAC    I40E_CLOUD_FIELD_OMAC
0256 #define I40E_CLOUD_FILTER_FLAGS_IMAC    I40E_CLOUD_FIELD_IMAC
0257 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN  (I40E_CLOUD_FIELD_IMAC | \
0258                          I40E_CLOUD_FIELD_IVLAN)
0259 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
0260                          I40E_CLOUD_FIELD_TEN_ID)
0261 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
0262                           I40E_CLOUD_FIELD_IMAC | \
0263                           I40E_CLOUD_FIELD_TEN_ID)
0264 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
0265                            I40E_CLOUD_FIELD_IVLAN | \
0266                            I40E_CLOUD_FIELD_TEN_ID)
0267 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
0268 
0269 struct i40e_cloud_filter {
0270     struct hlist_node cloud_node;
0271     unsigned long cookie;
0272     /* cloud filter input set follows */
0273     u8 dst_mac[ETH_ALEN];
0274     u8 src_mac[ETH_ALEN];
0275     __be16 vlan_id;
0276     u16 seid;       /* filter control */
0277     __be16 dst_port;
0278     __be16 src_port;
0279     u32 tenant_id;
0280     union {
0281         struct {
0282             struct in_addr dst_ip;
0283             struct in_addr src_ip;
0284         } v4;
0285         struct {
0286             struct in6_addr dst_ip6;
0287             struct in6_addr src_ip6;
0288         } v6;
0289     } ip;
0290 #define dst_ipv6    ip.v6.dst_ip6.s6_addr32
0291 #define src_ipv6    ip.v6.src_ip6.s6_addr32
0292 #define dst_ipv4    ip.v4.dst_ip.s_addr
0293 #define src_ipv4    ip.v4.src_ip.s_addr
0294     u16 n_proto;    /* Ethernet Protocol */
0295     u8 ip_proto;    /* IPPROTO value */
0296     u8 flags;
0297 #define I40E_CLOUD_TNL_TYPE_NONE        0xff
0298     u8 tunnel_type;
0299 };
0300 
0301 #define I40E_DCB_PRIO_TYPE_STRICT   0
0302 #define I40E_DCB_PRIO_TYPE_ETS      1
0303 #define I40E_DCB_STRICT_PRIO_CREDITS    127
0304 /* DCB per TC information data structure */
0305 struct i40e_tc_info {
0306     u16 qoffset;    /* Queue offset from base queue */
0307     u16 qcount;     /* Total Queues */
0308     u8  netdev_tc;  /* Netdev TC index if netdev associated */
0309 };
0310 
0311 /* TC configuration data structure */
0312 struct i40e_tc_configuration {
0313     u8  numtc;      /* Total number of enabled TCs */
0314     u8  enabled_tc; /* TC map */
0315     struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
0316 };
0317 
0318 #define I40E_UDP_PORT_INDEX_UNUSED  255
0319 struct i40e_udp_port_config {
0320     /* AdminQ command interface expects port number in Host byte order */
0321     u16 port;
0322     u8 type;
0323     u8 filter_index;
0324 };
0325 
0326 #define I40_DDP_FLASH_REGION 100
0327 #define I40E_PROFILE_INFO_SIZE 48
0328 #define I40E_MAX_PROFILE_NUM 16
0329 #define I40E_PROFILE_LIST_SIZE \
0330     (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
0331 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
0332 #define I40E_DDP_PROFILE_NAME_MAX 64
0333 
0334 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
0335           bool is_add);
0336 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
0337 
0338 struct i40e_ddp_profile_list {
0339     u32 p_count;
0340     struct i40e_profile_info p_info[];
0341 };
0342 
0343 struct i40e_ddp_old_profile_list {
0344     struct list_head list;
0345     size_t old_ddp_size;
0346     u8 old_ddp_buf[];
0347 };
0348 
0349 /* macros related to FLX_PIT */
0350 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
0351                     I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
0352                     I40E_PRTQF_FLX_PIT_FSIZE_MASK)
0353 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
0354                      I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
0355                      I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
0356 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
0357                      I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
0358                      I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
0359 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
0360                          I40E_FLEX_SET_FSIZE(fsize) | \
0361                          I40E_FLEX_SET_SRC_WORD(src))
0362 
0363 
0364 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
0365 
0366 /* macros related to GLQF_ORT */
0367 #define I40E_ORT_SET_IDX(idx)       (((idx) << \
0368                       I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
0369                      I40E_GLQF_ORT_PIT_INDX_MASK)
0370 
0371 #define I40E_ORT_SET_COUNT(count)   (((count) << \
0372                       I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
0373                      I40E_GLQF_ORT_FIELD_CNT_MASK)
0374 
0375 #define I40E_ORT_SET_PAYLOAD(payload)   (((payload) << \
0376                       I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
0377                      I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
0378 
0379 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
0380                         I40E_ORT_SET_COUNT(count) | \
0381                         I40E_ORT_SET_PAYLOAD(payload))
0382 
0383 #define I40E_L3_GLQF_ORT_IDX        34
0384 #define I40E_L4_GLQF_ORT_IDX        35
0385 
0386 /* Flex PIT register index */
0387 #define I40E_FLEX_PIT_IDX_START_L3  3
0388 #define I40E_FLEX_PIT_IDX_START_L4  6
0389 
0390 #define I40E_FLEX_PIT_TABLE_SIZE    3
0391 
0392 #define I40E_FLEX_DEST_UNUSED       63
0393 
0394 #define I40E_FLEX_INDEX_ENTRIES     8
0395 
0396 /* Flex MASK to disable all flexible entries */
0397 #define I40E_FLEX_INPUT_MASK    (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
0398                  I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
0399                  I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
0400                  I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
0401 
0402 struct i40e_flex_pit {
0403     struct list_head list;
0404     u16 src_offset;
0405     u8 pit_index;
0406 };
0407 
0408 struct i40e_fwd_adapter {
0409     struct net_device *netdev;
0410     int bit_no;
0411 };
0412 
0413 struct i40e_channel {
0414     struct list_head list;
0415     bool initialized;
0416     u8 type;
0417     u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
0418     u16 stat_counter_idx;
0419     u16 base_queue;
0420     u16 num_queue_pairs; /* Requested by user */
0421     u16 seid;
0422 
0423     u8 enabled_tc;
0424     struct i40e_aqc_vsi_properties_data info;
0425 
0426     u64 max_tx_rate;
0427     struct i40e_fwd_adapter *fwd;
0428 
0429     /* track this channel belongs to which VSI */
0430     struct i40e_vsi *parent_vsi;
0431 };
0432 
0433 struct i40e_ptp_pins_settings;
0434 
0435 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
0436 {
0437     return !!ch->fwd;
0438 }
0439 
0440 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
0441 {
0442     if (i40e_is_channel_macvlan(ch))
0443         return ch->fwd->netdev->dev_addr;
0444     else
0445         return NULL;
0446 }
0447 
0448 /* struct that defines the Ethernet device */
0449 struct i40e_pf {
0450     struct pci_dev *pdev;
0451     struct i40e_hw hw;
0452     DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
0453     struct msix_entry *msix_entries;
0454     bool fc_autoneg_status;
0455 
0456     u16 eeprom_version;
0457     u16 num_vmdq_vsis;         /* num vmdq vsis this PF has set up */
0458     u16 num_vmdq_qps;          /* num queue pairs per vmdq pool */
0459     u16 num_vmdq_msix;         /* num queue vectors per vmdq pool */
0460     u16 num_req_vfs;           /* num VFs requested for this PF */
0461     u16 num_vf_qps;            /* num queue pairs per VF */
0462     u16 num_lan_qps;           /* num lan queues this PF has set up */
0463     u16 num_lan_msix;          /* num queue vectors for the base PF vsi */
0464     u16 num_fdsb_msix;         /* num queue vectors for sideband Fdir */
0465     u16 num_iwarp_msix;        /* num of iwarp vectors for this PF */
0466     int iwarp_base_vector;
0467     int queues_left;           /* queues left unclaimed */
0468     u16 alloc_rss_size;        /* allocated RSS queues */
0469     u16 rss_size_max;          /* HW defined max RSS queues */
0470     u16 fdir_pf_filter_count;  /* num of guaranteed filters for this PF */
0471     u16 num_alloc_vsi;         /* num VSIs this driver supports */
0472     u8 atr_sample_rate;
0473     bool wol_en;
0474 
0475     struct hlist_head fdir_filter_list;
0476     u16 fdir_pf_active_filters;
0477     unsigned long fd_flush_timestamp;
0478     u32 fd_flush_cnt;
0479     u32 fd_add_err;
0480     u32 fd_atr_cnt;
0481 
0482     /* Book-keeping of side-band filter count per flow-type.
0483      * This is used to detect and handle input set changes for
0484      * respective flow-type.
0485      */
0486     u16 fd_tcp4_filter_cnt;
0487     u16 fd_udp4_filter_cnt;
0488     u16 fd_sctp4_filter_cnt;
0489     u16 fd_ip4_filter_cnt;
0490 
0491     u16 fd_tcp6_filter_cnt;
0492     u16 fd_udp6_filter_cnt;
0493     u16 fd_sctp6_filter_cnt;
0494     u16 fd_ip6_filter_cnt;
0495 
0496     /* Flexible filter table values that need to be programmed into
0497      * hardware, which expects L3 and L4 to be programmed separately. We
0498      * need to ensure that the values are in ascended order and don't have
0499      * duplicates, so we track each L3 and L4 values in separate lists.
0500      */
0501     struct list_head l3_flex_pit_list;
0502     struct list_head l4_flex_pit_list;
0503 
0504     struct udp_tunnel_nic_shared udp_tunnel_shared;
0505     struct udp_tunnel_nic_info udp_tunnel_nic;
0506 
0507     struct hlist_head cloud_filter_list;
0508     u16 num_cloud_filters;
0509 
0510     enum i40e_interrupt_policy int_policy;
0511     u16 rx_itr_default;
0512     u16 tx_itr_default;
0513     u32 msg_enable;
0514     char int_name[I40E_INT_NAME_STR_LEN];
0515     u16 adminq_work_limit; /* num of admin receive queue desc to process */
0516     unsigned long service_timer_period;
0517     unsigned long service_timer_previous;
0518     struct timer_list service_timer;
0519     struct work_struct service_task;
0520 
0521     u32 hw_features;
0522 #define I40E_HW_RSS_AQ_CAPABLE          BIT(0)
0523 #define I40E_HW_128_QP_RSS_CAPABLE      BIT(1)
0524 #define I40E_HW_ATR_EVICT_CAPABLE       BIT(2)
0525 #define I40E_HW_WB_ON_ITR_CAPABLE       BIT(3)
0526 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
0527 #define I40E_HW_NO_PCI_LINK_CHECK       BIT(5)
0528 #define I40E_HW_100M_SGMII_CAPABLE      BIT(6)
0529 #define I40E_HW_NO_DCB_SUPPORT          BIT(7)
0530 #define I40E_HW_USE_SET_LLDP_MIB        BIT(8)
0531 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE      BIT(9)
0532 #define I40E_HW_PTP_L4_CAPABLE          BIT(10)
0533 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE       BIT(11)
0534 #define I40E_HW_HAVE_CRT_RETIMER        BIT(13)
0535 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE      BIT(14)
0536 #define I40E_HW_PHY_CONTROLS_LEDS       BIT(15)
0537 #define I40E_HW_STOP_FW_LLDP            BIT(16)
0538 #define I40E_HW_PORT_ID_VALID           BIT(17)
0539 #define I40E_HW_RESTART_AUTONEG         BIT(18)
0540 
0541     u32 flags;
0542 #define I40E_FLAG_RX_CSUM_ENABLED       BIT(0)
0543 #define I40E_FLAG_MSI_ENABLED           BIT(1)
0544 #define I40E_FLAG_MSIX_ENABLED          BIT(2)
0545 #define I40E_FLAG_RSS_ENABLED           BIT(3)
0546 #define I40E_FLAG_VMDQ_ENABLED          BIT(4)
0547 #define I40E_FLAG_SRIOV_ENABLED         BIT(5)
0548 #define I40E_FLAG_DCB_CAPABLE           BIT(6)
0549 #define I40E_FLAG_DCB_ENABLED           BIT(7)
0550 #define I40E_FLAG_FD_SB_ENABLED         BIT(8)
0551 #define I40E_FLAG_FD_ATR_ENABLED        BIT(9)
0552 #define I40E_FLAG_MFP_ENABLED           BIT(10)
0553 #define I40E_FLAG_HW_ATR_EVICT_ENABLED      BIT(11)
0554 #define I40E_FLAG_VEB_MODE_ENABLED      BIT(12)
0555 #define I40E_FLAG_VEB_STATS_ENABLED     BIT(13)
0556 #define I40E_FLAG_LINK_POLLING_ENABLED      BIT(14)
0557 #define I40E_FLAG_TRUE_PROMISC_SUPPORT      BIT(15)
0558 #define I40E_FLAG_LEGACY_RX         BIT(16)
0559 #define I40E_FLAG_PTP               BIT(17)
0560 #define I40E_FLAG_IWARP_ENABLED         BIT(18)
0561 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED    BIT(19)
0562 #define I40E_FLAG_SOURCE_PRUNING_DISABLED       BIT(20)
0563 #define I40E_FLAG_TC_MQPRIO         BIT(21)
0564 #define I40E_FLAG_FD_SB_INACTIVE        BIT(22)
0565 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER     BIT(23)
0566 #define I40E_FLAG_DISABLE_FW_LLDP       BIT(24)
0567 #define I40E_FLAG_RS_FEC            BIT(25)
0568 #define I40E_FLAG_BASE_R_FEC            BIT(26)
0569 #define I40E_FLAG_VF_VLAN_PRUNING       BIT(27)
0570 /* TOTAL_PORT_SHUTDOWN
0571  * Allows to physically disable the link on the NIC's port.
0572  * If enabled, (after link down request from the OS)
0573  * no link, traffic or led activity is possible on that port.
0574  *
0575  * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
0576  * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
0577  * and cannot be disabled by system admin at that time.
0578  * The functionalities are exclusive in terms of configuration, but they also
0579  * have similar behavior (allowing to disable physical link of the port),
0580  * with following differences:
0581  * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
0582  *   supported by whole family of 7xx Intel Ethernet Controllers
0583  * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
0584  *   only if motherboard's BIOS and NIC's FW has support of it
0585  * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
0586  *   by sending phy_type=0 to NIC's FW
0587  * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
0588  *   the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
0589  *   in abilities field of i40e_aq_set_phy_config structure
0590  */
0591 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED   BIT(27)
0592 
0593     struct i40e_client_instance *cinst;
0594     bool stat_offsets_loaded;
0595     struct i40e_hw_port_stats stats;
0596     struct i40e_hw_port_stats stats_offsets;
0597     u32 tx_timeout_count;
0598     u32 tx_timeout_recovery_level;
0599     unsigned long tx_timeout_last_recovery;
0600     u32 tx_sluggish_count;
0601     u32 hw_csum_rx_error;
0602     u32 led_status;
0603     u16 corer_count; /* Core reset count */
0604     u16 globr_count; /* Global reset count */
0605     u16 empr_count; /* EMP reset count */
0606     u16 pfr_count; /* PF reset count */
0607     u16 sw_int_count; /* SW interrupt count */
0608 
0609     struct mutex switch_mutex;
0610     u16 lan_vsi;       /* our default LAN VSI */
0611     u16 lan_veb;       /* initial relay, if exists */
0612 #define I40E_NO_VEB 0xffff
0613 #define I40E_NO_VSI 0xffff
0614     u16 next_vsi;      /* Next unallocated VSI - 0-based! */
0615     struct i40e_vsi **vsi;
0616     struct i40e_veb *veb[I40E_MAX_VEB];
0617 
0618     struct i40e_lump_tracking *qp_pile;
0619     struct i40e_lump_tracking *irq_pile;
0620 
0621     /* switch config info */
0622     u16 pf_seid;
0623     u16 main_vsi_seid;
0624     u16 mac_seid;
0625     struct kobject *switch_kobj;
0626 #ifdef CONFIG_DEBUG_FS
0627     struct dentry *i40e_dbg_pf;
0628 #endif /* CONFIG_DEBUG_FS */
0629     bool cur_promisc;
0630 
0631     u16 instance; /* A unique number per i40e_pf instance in the system */
0632 
0633     /* sr-iov config info */
0634     struct i40e_vf *vf;
0635     int num_alloc_vfs;  /* actual number of VFs allocated */
0636     u32 vf_aq_requests;
0637     u32 arq_overflows;  /* Not fatal, possibly indicative of problems */
0638 
0639     /* DCBx/DCBNL capability for PF that indicates
0640      * whether DCBx is managed by firmware or host
0641      * based agent (LLDPAD). Also, indicates what
0642      * flavor of DCBx protocol (IEEE/CEE) is supported
0643      * by the device. For now we're supporting IEEE
0644      * mode only.
0645      */
0646     u16 dcbx_cap;
0647 
0648     struct i40e_filter_control_settings filter_settings;
0649     struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
0650     struct i40e_dcbx_config tmp_cfg;
0651 
0652 /* GPIO defines used by PTP */
0653 #define I40E_SDP3_2         18
0654 #define I40E_SDP3_3         19
0655 #define I40E_GPIO_4         20
0656 #define I40E_LED2_0         26
0657 #define I40E_LED2_1         27
0658 #define I40E_LED3_0         28
0659 #define I40E_LED3_1         29
0660 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
0661     (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
0662 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
0663     (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
0664 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
0665     (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
0666 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
0667     (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
0668 #define I40E_GLGEN_GPIO_CTL_RESERVED    BIT(2)
0669 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
0670     (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
0671 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \
0672     (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
0673 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
0674     (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
0675 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
0676     (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
0677 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
0678     (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
0679 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
0680     (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
0681 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
0682     (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
0683 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
0684     (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
0685 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
0686     (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
0687      I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
0688      I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
0689 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
0690     (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
0691      I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
0692      I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
0693 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
0694     (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
0695      I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
0696      I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
0697      I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
0698 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
0699     (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
0700      I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
0701      I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
0702      I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
0703 #define I40E_GLGEN_GPIO_CTL_LED_INIT \
0704     (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
0705      I40E_GLGEN_GPIO_CTL_DIR_OUT | \
0706      I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
0707      I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
0708      I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
0709      I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
0710 #define I40E_PRTTSYN_AUX_1_INSTNT \
0711     (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
0712 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
0713     (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
0714 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD  (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
0715 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
0716     (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
0717 #define I40E_PTP_HALF_SECOND        500000000LL /* nano seconds */
0718 #define I40E_PTP_2_SEC_DELAY        2
0719 
0720     struct ptp_clock *ptp_clock;
0721     struct ptp_clock_info ptp_caps;
0722     struct sk_buff *ptp_tx_skb;
0723     unsigned long ptp_tx_start;
0724     struct hwtstamp_config tstamp_config;
0725     struct timespec64 ptp_prev_hw_time;
0726     struct work_struct ptp_pps_work;
0727     struct work_struct ptp_extts0_work;
0728     struct work_struct ptp_extts1_work;
0729     ktime_t ptp_reset_start;
0730     struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
0731     u32 ptp_adj_mult;
0732     u32 tx_hwtstamp_timeouts;
0733     u32 tx_hwtstamp_skipped;
0734     u32 rx_hwtstamp_cleared;
0735     u32 latch_event_flags;
0736     u64 ptp_pps_start;
0737     u32 pps_delay;
0738     spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
0739     struct ptp_pin_desc ptp_pin[3];
0740     unsigned long latch_events[4];
0741     bool ptp_tx;
0742     bool ptp_rx;
0743     struct i40e_ptp_pins_settings *ptp_pins;
0744     u16 rss_table_size; /* HW RSS table size */
0745     u32 max_bw;
0746     u32 min_bw;
0747 
0748     u32 ioremap_len;
0749     u32 fd_inv;
0750     u16 phy_led_val;
0751 
0752     u16 override_q_count;
0753     u16 last_sw_conf_flags;
0754     u16 last_sw_conf_valid_flags;
0755     /* List to keep previous DDP profiles to be rolled back in the future */
0756     struct list_head ddp_old_prof;
0757 };
0758 
0759 /**
0760  * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
0761  * @macaddr: the MAC Address as the base key
0762  *
0763  * Simply copies the address and returns it as a u64 for hashing
0764  **/
0765 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
0766 {
0767     u64 key = 0;
0768 
0769     ether_addr_copy((u8 *)&key, macaddr);
0770     return key;
0771 }
0772 
0773 enum i40e_filter_state {
0774     I40E_FILTER_INVALID = 0,    /* Invalid state */
0775     I40E_FILTER_NEW,        /* New, not sent to FW yet */
0776     I40E_FILTER_ACTIVE,     /* Added to switch by FW */
0777     I40E_FILTER_FAILED,     /* Rejected by FW */
0778     I40E_FILTER_REMOVE,     /* To be removed */
0779 /* There is no 'removed' state; the filter struct is freed */
0780 };
0781 struct i40e_mac_filter {
0782     struct hlist_node hlist;
0783     u8 macaddr[ETH_ALEN];
0784 #define I40E_VLAN_ANY -1
0785     s16 vlan;
0786     enum i40e_filter_state state;
0787 };
0788 
0789 /* Wrapper structure to keep track of filters while we are preparing to send
0790  * firmware commands. We cannot send firmware commands while holding a
0791  * spinlock, since it might sleep. To avoid this, we wrap the added filters in
0792  * a separate structure, which will track the state change and update the real
0793  * filter while under lock. We can't simply hold the filters in a separate
0794  * list, as this opens a window for a race condition when adding new MAC
0795  * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
0796  */
0797 struct i40e_new_mac_filter {
0798     struct hlist_node hlist;
0799     struct i40e_mac_filter *f;
0800 
0801     /* Track future changes to state separately */
0802     enum i40e_filter_state state;
0803 };
0804 
0805 struct i40e_veb {
0806     struct i40e_pf *pf;
0807     u16 idx;
0808     u16 veb_idx;        /* index of VEB parent */
0809     u16 seid;
0810     u16 uplink_seid;
0811     u16 stats_idx;      /* index of VEB parent */
0812     u8  enabled_tc;
0813     u16 bridge_mode;    /* Bridge Mode (VEB/VEPA) */
0814     u16 flags;
0815     u16 bw_limit;
0816     u8  bw_max_quanta;
0817     bool is_abs_credits;
0818     u8  bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
0819     u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
0820     u8  bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
0821     struct kobject *kobj;
0822     bool stat_offsets_loaded;
0823     struct i40e_eth_stats stats;
0824     struct i40e_eth_stats stats_offsets;
0825     struct i40e_veb_tc_stats tc_stats;
0826     struct i40e_veb_tc_stats tc_stats_offsets;
0827 };
0828 
0829 /* struct that defines a VSI, associated with a dev */
0830 struct i40e_vsi {
0831     struct net_device *netdev;
0832     unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0833     bool netdev_registered;
0834     bool stat_offsets_loaded;
0835 
0836     u32 current_netdev_flags;
0837     DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
0838 #define I40E_VSI_FLAG_FILTER_CHANGED    BIT(0)
0839 #define I40E_VSI_FLAG_VEB_OWNER     BIT(1)
0840     unsigned long flags;
0841 
0842     /* Per VSI lock to protect elements/hash (MAC filter) */
0843     spinlock_t mac_filter_hash_lock;
0844     /* Fixed size hash table with 2^8 buckets for MAC filters */
0845     DECLARE_HASHTABLE(mac_filter_hash, 8);
0846     bool has_vlan_filter;
0847 
0848     /* VSI stats */
0849     struct rtnl_link_stats64 net_stats;
0850     struct rtnl_link_stats64 net_stats_offsets;
0851     struct i40e_eth_stats eth_stats;
0852     struct i40e_eth_stats eth_stats_offsets;
0853     u64 tx_restart;
0854     u64 tx_busy;
0855     u64 tx_linearize;
0856     u64 tx_force_wb;
0857     u64 tx_stopped;
0858     u64 rx_buf_failed;
0859     u64 rx_page_failed;
0860     u64 rx_page_reuse;
0861     u64 rx_page_alloc;
0862     u64 rx_page_waive;
0863     u64 rx_page_busy;
0864 
0865     /* These are containers of ring pointers, allocated at run-time */
0866     struct i40e_ring **rx_rings;
0867     struct i40e_ring **tx_rings;
0868     struct i40e_ring **xdp_rings; /* XDP Tx rings */
0869 
0870     u32  active_filters;
0871     u32  promisc_threshold;
0872 
0873     u16 work_limit;
0874     u16 int_rate_limit; /* value in usecs */
0875 
0876     u16 rss_table_size; /* HW RSS table size */
0877     u16 rss_size;       /* Allocated RSS queues */
0878     u8  *rss_hkey_user; /* User configured hash keys */
0879     u8  *rss_lut_user;  /* User configured lookup table entries */
0880 
0881 
0882     u16 max_frame;
0883     u16 rx_buf_len;
0884 
0885     struct bpf_prog *xdp_prog;
0886 
0887     /* List of q_vectors allocated to this VSI */
0888     struct i40e_q_vector **q_vectors;
0889     int num_q_vectors;
0890     int base_vector;
0891     bool irqs_ready;
0892 
0893     u16 seid;       /* HW index of this VSI (absolute index) */
0894     u16 id;         /* VSI number */
0895     u16 uplink_seid;
0896 
0897     u16 base_queue;     /* vsi's first queue in hw array */
0898     u16 alloc_queue_pairs;  /* Allocated Tx/Rx queues */
0899     u16 req_queue_pairs;    /* User requested queue pairs */
0900     u16 num_queue_pairs;    /* Used tx and rx pairs */
0901     u16 num_tx_desc;
0902     u16 num_rx_desc;
0903     enum i40e_vsi_type type;  /* VSI type, e.g., LAN, FCoE, etc */
0904     s16 vf_id;      /* Virtual function ID for SRIOV VSIs */
0905 
0906     struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
0907     struct i40e_tc_configuration tc_config;
0908     struct i40e_aqc_vsi_properties_data info;
0909 
0910     /* VSI BW limit (absolute across all TCs) */
0911     u16 bw_limit;       /* VSI BW Limit (0 = disabled) */
0912     u8  bw_max_quanta;  /* Max Quanta when BW limit is enabled */
0913 
0914     /* Relative TC credits across VSIs */
0915     u8  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
0916     /* TC BW limit credits within VSI */
0917     u16  bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
0918     /* TC BW limit max quanta within VSI */
0919     u8  bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
0920 
0921     struct i40e_pf *back;   /* Backreference to associated PF */
0922     u16 idx;        /* index in pf->vsi[] */
0923     u16 veb_idx;        /* index of VEB parent */
0924     struct kobject *kobj;   /* sysfs object */
0925     bool current_isup;  /* Sync 'link up' logging */
0926     enum i40e_aq_link_speed current_speed;  /* Sync link speed logging */
0927 
0928     /* channel specific fields */
0929     u16 cnt_q_avail;    /* num of queues available for channel usage */
0930     u16 orig_rss_size;
0931     u16 current_rss_size;
0932     bool reconfig_rss;
0933 
0934     u16 next_base_queue;    /* next queue to be used for channel setup */
0935 
0936     struct list_head ch_list;
0937     u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
0938 
0939     /* macvlan fields */
0940 #define I40E_MAX_MACVLANS       128 /* Max HW vectors - 1 on FVL */
0941 #define I40E_MIN_MACVLAN_VECTORS    2   /* Min vectors to enable macvlans */
0942     DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
0943     struct list_head macvlan_list;
0944     int macvlan_cnt;
0945 
0946     void *priv; /* client driver data reference. */
0947 
0948     /* VSI specific handlers */
0949     irqreturn_t (*irq_handler)(int irq, void *data);
0950 
0951     unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
0952 } ____cacheline_internodealigned_in_smp;
0953 
0954 struct i40e_netdev_priv {
0955     struct i40e_vsi *vsi;
0956 };
0957 
0958 extern struct ida i40e_client_ida;
0959 
0960 /* struct that defines an interrupt vector */
0961 struct i40e_q_vector {
0962     struct i40e_vsi *vsi;
0963 
0964     u16 v_idx;      /* index in the vsi->q_vector array. */
0965     u16 reg_idx;        /* register index of the interrupt */
0966 
0967     struct napi_struct napi;
0968 
0969     struct i40e_ring_container rx;
0970     struct i40e_ring_container tx;
0971 
0972     u8 itr_countdown;   /* when 0 should adjust adaptive ITR */
0973     u8 num_ringpairs;   /* total number of ring pairs in vector */
0974 
0975     cpumask_t affinity_mask;
0976     struct irq_affinity_notify affinity_notify;
0977 
0978     struct rcu_head rcu;    /* to avoid race with update stats on free */
0979     char name[I40E_INT_NAME_STR_LEN];
0980     bool arm_wb_state;
0981 } ____cacheline_internodealigned_in_smp;
0982 
0983 /* lan device */
0984 struct i40e_device {
0985     struct list_head list;
0986     struct i40e_pf *pf;
0987 };
0988 
0989 /**
0990  * i40e_nvm_version_str - format the NVM version strings
0991  * @hw: ptr to the hardware info
0992  **/
0993 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
0994 {
0995     static char buf[32];
0996     u32 full_ver;
0997 
0998     full_ver = hw->nvm.oem_ver;
0999 
1000     if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
1001         u8 gen, snap;
1002         u16 release;
1003 
1004         gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
1005         snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
1006             I40E_OEM_SNAP_SHIFT);
1007         release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
1008 
1009         snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
1010     } else {
1011         u8 ver, patch;
1012         u16 build;
1013 
1014         ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
1015         build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
1016              I40E_OEM_VER_BUILD_MASK);
1017         patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
1018 
1019         snprintf(buf, sizeof(buf),
1020              "%x.%02x 0x%x %d.%d.%d",
1021              (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
1022                 I40E_NVM_VERSION_HI_SHIFT,
1023              (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
1024                 I40E_NVM_VERSION_LO_SHIFT,
1025              hw->nvm.eetrack, ver, build, patch);
1026     }
1027 
1028     return buf;
1029 }
1030 
1031 /**
1032  * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1033  * @netdev: the corresponding netdev
1034  *
1035  * Return the PF struct for the given netdev
1036  **/
1037 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1038 {
1039     struct i40e_netdev_priv *np = netdev_priv(netdev);
1040     struct i40e_vsi *vsi = np->vsi;
1041 
1042     return vsi->back;
1043 }
1044 
1045 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1046                 irqreturn_t (*irq_handler)(int, void *))
1047 {
1048     vsi->irq_handler = irq_handler;
1049 }
1050 
1051 /**
1052  * i40e_get_fd_cnt_all - get the total FD filter space available
1053  * @pf: pointer to the PF struct
1054  **/
1055 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1056 {
1057     return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1058 }
1059 
1060 /**
1061  * i40e_read_fd_input_set - reads value of flow director input set register
1062  * @pf: pointer to the PF struct
1063  * @addr: register addr
1064  *
1065  * This function reads value of flow director input set register
1066  * specified by 'addr' (which is specific to flow-type)
1067  **/
1068 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1069 {
1070     u64 val;
1071 
1072     val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1073     val <<= 32;
1074     val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1075 
1076     return val;
1077 }
1078 
1079 /**
1080  * i40e_write_fd_input_set - writes value into flow director input set register
1081  * @pf: pointer to the PF struct
1082  * @addr: register addr
1083  * @val: value to be written
1084  *
1085  * This function writes specified value to the register specified by 'addr'.
1086  * This register is input set register based on flow-type.
1087  **/
1088 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1089                        u16 addr, u64 val)
1090 {
1091     i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1092               (u32)(val >> 32));
1093     i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1094               (u32)(val & 0xFFFFFFFFULL));
1095 }
1096 
1097 /**
1098  * i40e_get_pf_count - get PCI PF count.
1099  * @hw: pointer to a hw.
1100  *
1101  * Reports the function number of the highest PCI physical
1102  * function plus 1 as it is loaded from the NVM.
1103  *
1104  * Return: PCI PF count.
1105  **/
1106 static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1107 {
1108     return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1109              rd32(hw, I40E_GLGEN_PCIFCNCNT));
1110 }
1111 
1112 /* needed by i40e_ethtool.c */
1113 int i40e_up(struct i40e_vsi *vsi);
1114 void i40e_down(struct i40e_vsi *vsi);
1115 extern const char i40e_driver_name[];
1116 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1117 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1118 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1119 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1120 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1121                u16 rss_table_size, u16 rss_size);
1122 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1123 /**
1124  * i40e_find_vsi_by_type - Find and return Flow Director VSI
1125  * @pf: PF to search for VSI
1126  * @type: Value indicating type of VSI we are looking for
1127  **/
1128 static inline struct i40e_vsi *
1129 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1130 {
1131     int i;
1132 
1133     for (i = 0; i < pf->num_alloc_vsi; i++) {
1134         struct i40e_vsi *vsi = pf->vsi[i];
1135 
1136         if (vsi && vsi->type == type)
1137             return vsi;
1138     }
1139 
1140     return NULL;
1141 }
1142 void i40e_update_stats(struct i40e_vsi *vsi);
1143 void i40e_update_veb_stats(struct i40e_veb *veb);
1144 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1145 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1146 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1147                     bool printconfig);
1148 
1149 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1150               struct i40e_fdir_filter *input, bool add);
1151 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1152 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1153 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1154 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1155 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1156 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1157 void i40e_set_ethtool_ops(struct net_device *netdev);
1158 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1159                     const u8 *macaddr, s16 vlan);
1160 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1161 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1162 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1163 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1164                 u16 uplink, u32 param1);
1165 int i40e_vsi_release(struct i40e_vsi *vsi);
1166 void i40e_service_event_schedule(struct i40e_pf *pf);
1167 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1168                   u8 *msg, u16 len);
1169 
1170 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1171                bool enable);
1172 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1173 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1174 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1175 void i40e_vsi_stop_rings_no_wait(struct  i40e_vsi *vsi);
1176 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1177 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1178 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1179                 u16 downlink_seid, u8 enabled_tc);
1180 void i40e_veb_release(struct i40e_veb *veb);
1181 
1182 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1183 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1184 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1185 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1186 void i40e_pf_reset_stats(struct i40e_pf *pf);
1187 #ifdef CONFIG_DEBUG_FS
1188 void i40e_dbg_pf_init(struct i40e_pf *pf);
1189 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1190 void i40e_dbg_init(void);
1191 void i40e_dbg_exit(void);
1192 #else
1193 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1194 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1195 static inline void i40e_dbg_init(void) {}
1196 static inline void i40e_dbg_exit(void) {}
1197 #endif /* CONFIG_DEBUG_FS*/
1198 /* needed by client drivers */
1199 int i40e_lan_add_device(struct i40e_pf *pf);
1200 int i40e_lan_del_device(struct i40e_pf *pf);
1201 void i40e_client_subtask(struct i40e_pf *pf);
1202 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1203 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1204 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1205 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1206 void i40e_client_update_msix_info(struct i40e_pf *pf);
1207 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1208 /**
1209  * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1210  * @vsi: pointer to a vsi
1211  * @vector: enable a particular Hw Interrupt vector, without base_vector
1212  **/
1213 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1214 {
1215     struct i40e_pf *pf = vsi->back;
1216     struct i40e_hw *hw = &pf->hw;
1217     u32 val;
1218 
1219     val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1220           I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1221           (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1222     wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1223     /* skip the flush */
1224 }
1225 
1226 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1227 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1228 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1229 int i40e_open(struct net_device *netdev);
1230 int i40e_close(struct net_device *netdev);
1231 int i40e_vsi_open(struct i40e_vsi *vsi);
1232 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1233 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1234 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1235 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1236 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1237 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1238                         const u8 *macaddr);
1239 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1240 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1241 int i40e_count_filters(struct i40e_vsi *vsi);
1242 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1243 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1244 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1245 {
1246     return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP);
1247 }
1248 
1249 #ifdef CONFIG_I40E_DCB
1250 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1251                struct i40e_dcbx_config *old_cfg,
1252                struct i40e_dcbx_config *new_cfg);
1253 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1254 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1255 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1256                 struct i40e_dcbx_config *old_cfg,
1257                 struct i40e_dcbx_config *new_cfg);
1258 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1259 int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1260 #endif /* CONFIG_I40E_DCB */
1261 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1262 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1263 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1264 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1265 void i40e_ptp_set_increment(struct i40e_pf *pf);
1266 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1267 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1268 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1269 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1270 void i40e_ptp_init(struct i40e_pf *pf);
1271 void i40e_ptp_stop(struct i40e_pf *pf);
1272 int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1273 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1274 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1275 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1276 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1277 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1278 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1279 
1280 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1281 
1282 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1283 {
1284     return !!READ_ONCE(vsi->xdp_prog);
1285 }
1286 
1287 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1288 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1289 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1290                   struct i40e_cloud_filter *filter,
1291                   bool add);
1292 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1293                       struct i40e_cloud_filter *filter,
1294                       bool add);
1295 
1296 /**
1297  * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1298  * @pf: pointer to a pf.
1299  *
1300  * Check and return value of flag I40E_FLAG_TC_MQPRIO.
1301  *
1302  * Return: I40E_FLAG_TC_MQPRIO set state.
1303  **/
1304 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1305 {
1306     return pf->flags & I40E_FLAG_TC_MQPRIO;
1307 }
1308 
1309 #endif /* _I40E_H_ */
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