intel/e1000e/phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000E_PHY_H_
0005 #define _E1000E_PHY_H_
0006
0007 s32 e1000e_check_downshift(struct e1000_hw *hw);
0008 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
0009 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
0010 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
0011 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
0012 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
0013 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
0014 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
0015 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
0016 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
0017 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
0018 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
0019 s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
0020 s32 e1000e_get_phy_id(struct e1000_hw *hw);
0021 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
0022 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
0023 s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
0024 s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
0025 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
0026 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
0027 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
0028 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
0029 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
0030 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
0031 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
0032 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
0033 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
0034 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
0035 s32 e1000e_setup_copper_link(struct e1000_hw *hw);
0036 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
0037 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
0038 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
0039 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
0040 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
0041 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
0042                 u32 usec_interval, bool *success);
0043 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
0044 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
0045 s32 e1000e_determine_phy_address(struct e1000_hw *hw);
0046 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
0047 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
0048 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
0049 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
0050 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
0051 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
0052 void e1000_power_up_phy_copper(struct e1000_hw *hw);
0053 void e1000_power_down_phy_copper(struct e1000_hw *hw);
0054 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
0055 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
0056 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
0057 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
0058 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
0059 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
0060 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
0061 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
0062 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
0063 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
0064 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
0065 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
0066 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
0067 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
0068
0069 #define E1000_MAX_PHY_ADDR      8
0070
0071 /* IGP01E1000 Specific Registers */
0072 #define IGP01E1000_PHY_PORT_CONFIG  0x10    /* Port Config */
0073 #define IGP01E1000_PHY_PORT_STATUS  0x11    /* Status */
0074 #define IGP01E1000_PHY_PORT_CTRL    0x12    /* Control */
0075 #define IGP01E1000_PHY_LINK_HEALTH  0x13    /* PHY Link Health */
0076 #define IGP02E1000_PHY_POWER_MGMT   0x19    /* Power Management */
0077 #define IGP01E1000_PHY_PAGE_SELECT  0x1F    /* Page Select */
0078 #define BM_PHY_PAGE_SELECT      22  /* Page Select for BM */
0079 #define IGP_PAGE_SHIFT          5
0080 #define PHY_REG_MASK            0x1F
0081
0082 /* BM/HV Specific Registers */
0083 #define BM_PORT_CTRL_PAGE       769
0084 #define BM_WUC_PAGE         800
0085 #define BM_WUC_ADDRESS_OPCODE       0x11
0086 #define BM_WUC_DATA_OPCODE      0x12
0087 #define BM_WUC_ENABLE_PAGE      BM_PORT_CTRL_PAGE
0088 #define BM_WUC_ENABLE_REG       17
0089 #define BM_WUC_ENABLE_BIT       BIT(2)
0090 #define BM_WUC_HOST_WU_BIT      BIT(4)
0091 #define BM_WUC_ME_WU_BIT        BIT(5)
0092
0093 #define PHY_UPPER_SHIFT         21
0094 #define BM_PHY_REG(page, reg) \
0095     (((reg) & MAX_PHY_REG_ADDRESS) |\
0096      (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
0097      (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
0098 #define BM_PHY_REG_PAGE(offset) \
0099     ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
0100 #define BM_PHY_REG_NUM(offset) \
0101     ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
0102      (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
0103         ~MAX_PHY_REG_ADDRESS)))
0104
0105 #define HV_INTC_FC_PAGE_START       768
0106 #define I82578_ADDR_REG         29
0107 #define I82577_ADDR_REG         16
0108 #define I82577_CFG_REG          22
0109 #define I82577_CFG_ASSERT_CRS_ON_TX BIT(15)
0110 #define I82577_CFG_ENABLE_DOWNSHIFT (3u << 10)  /* auto downshift */
0111 #define I82577_CTRL_REG         23
0112
0113 /* 82577 specific PHY registers */
0114 #define I82577_PHY_CTRL_2       18
0115 #define I82577_PHY_LBK_CTRL     19
0116 #define I82577_PHY_STATUS_2     26
0117 #define I82577_PHY_DIAG_STATUS      31
0118
0119 /* I82577 PHY Status 2 */
0120 #define I82577_PHY_STATUS2_REV_POLARITY     0x0400
0121 #define I82577_PHY_STATUS2_MDIX         0x0800
0122 #define I82577_PHY_STATUS2_SPEED_MASK       0x0300
0123 #define I82577_PHY_STATUS2_SPEED_1000MBPS   0x0200
0124
0125 /* I82577 PHY Control 2 */
0126 #define I82577_PHY_CTRL2_MANUAL_MDIX        0x0200
0127 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX      0x0400
0128 #define I82577_PHY_CTRL2_MDIX_CFG_MASK      0x0600
0129
0130 /* I82577 PHY Diagnostics Status */
0131 #define I82577_DSTATUS_CABLE_LENGTH     0x03FC
0132 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT   2
0133
0134 /* BM PHY Copper Specific Control 1 */
0135 #define BM_CS_CTRL1         16
0136
0137 /* BM PHY Copper Specific Status */
0138 #define BM_CS_STATUS            17
0139 #define BM_CS_STATUS_LINK_UP        0x0400
0140 #define BM_CS_STATUS_RESOLVED       0x0800
0141 #define BM_CS_STATUS_SPEED_MASK     0xC000
0142 #define BM_CS_STATUS_SPEED_1000     0x8000
0143
0144 /* 82577 Mobile Phy Status Register */
0145 #define HV_M_STATUS         26
0146 #define HV_M_STATUS_AUTONEG_COMPLETE    0x1000
0147 #define HV_M_STATUS_SPEED_MASK      0x0300
0148 #define HV_M_STATUS_SPEED_1000      0x0200
0149 #define HV_M_STATUS_SPEED_100       0x0100
0150 #define HV_M_STATUS_LINK_UP     0x0040
0151
0152 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
0153 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
0154
0155 #define IGP01E1000_PSCR_AUTO_MDIX   0x1000
0156 #define IGP01E1000_PSCR_FORCE_MDI_MDIX  0x2000  /* 0=MDI, 1=MDIX */
0157
0158 #define IGP01E1000_PSCFR_SMART_SPEED    0x0080
0159
0160 #define IGP02E1000_PM_SPD       0x0001  /* Smart Power Down */
0161 #define IGP02E1000_PM_D0_LPLU       0x0002  /* For D0a states */
0162 #define IGP02E1000_PM_D3_LPLU       0x0004  /* For all other states */
0163
0164 #define IGP01E1000_PLHR_SS_DOWNGRADE    0x8000
0165
0166 #define IGP01E1000_PSSR_POLARITY_REVERSED   0x0002
0167 #define IGP01E1000_PSSR_MDIX        0x0800
0168 #define IGP01E1000_PSSR_SPEED_MASK  0xC000
0169 #define IGP01E1000_PSSR_SPEED_1000MBPS  0xC000
0170
0171 #define IGP02E1000_PHY_CHANNEL_NUM  4
0172 #define IGP02E1000_PHY_AGC_A        0x11B1
0173 #define IGP02E1000_PHY_AGC_B        0x12B1
0174 #define IGP02E1000_PHY_AGC_C        0x14B1
0175 #define IGP02E1000_PHY_AGC_D        0x18B1
0176
0177 #define IGP02E1000_AGC_LENGTH_SHIFT 9   /* Course=15:13, Fine=12:9 */
0178 #define IGP02E1000_AGC_LENGTH_MASK  0x7F
0179 #define IGP02E1000_AGC_RANGE        15
0180
0181 #define E1000_CABLE_LENGTH_UNDEFINED    0xFF
0182
0183 #define E1000_KMRNCTRLSTA_OFFSET    0x001F0000
0184 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT  16
0185 #define E1000_KMRNCTRLSTA_REN       0x00200000
0186 #define E1000_KMRNCTRLSTA_CTRL_OFFSET   0x1 /* Kumeran Control */
0187 #define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3 /* Kumeran Diagnostic */
0188 #define E1000_KMRNCTRLSTA_TIMEOUTS  0x4 /* Kumeran Timeouts */
0189 #define E1000_KMRNCTRLSTA_INBAND_PARAM  0x9 /* Kumeran InBand Parameters */
0190 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200  /* Kumeran IBIST Disable */
0191 #define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000  /* Nearend Loopback mode */
0192 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
0193 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002  /* enable K1 */
0194 #define E1000_KMRNCTRLSTA_HD_CTRL   0x10    /* Kumeran HD Control */
0195
0196 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
0197 #define IFE_PHY_SPECIAL_CONTROL     0x11    /* 100BaseTx PHY Special Ctrl */
0198 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B    /* PHY Special and LED Ctrl */
0199 #define IFE_PHY_MDIX_CONTROL        0x1C    /* MDI/MDI-X Control */
0200
0201 /* IFE PHY Extended Status Control */
0202 #define IFE_PESC_POLARITY_REVERSED  0x0100
0203
0204 /* IFE PHY Special Control */
0205 #define IFE_PSC_AUTO_POLARITY_DISABLE   0x0010
0206 #define IFE_PSC_FORCE_POLARITY      0x0020
0207
0208 /* IFE PHY Special Control and LED Control */
0209 #define IFE_PSCL_PROBE_MODE     0x0020
0210 #define IFE_PSCL_PROBE_LEDS_OFF     0x0006  /* Force LEDs 0 and 2 off */
0211 #define IFE_PSCL_PROBE_LEDS_ON      0x0007  /* Force LEDs 0 and 2 on */
0212
0213 /* IFE PHY MDIX Control */
0214 #define IFE_PMC_MDIX_STATUS     0x0020  /* 1=MDI-X, 0=MDI */
0215 #define IFE_PMC_FORCE_MDIX      0x0040  /* 1=force MDI-X, 0=force MDI */
0216 #define IFE_PMC_AUTO_MDIX       0x0080  /* 1=enable auto, 0=disable */
0217
0218 #endif