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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003 
0004 #ifndef _E1000E_HW_H_
0005 #define _E1000E_HW_H_
0006 
0007 #include "regs.h"
0008 #include "defines.h"
0009 
0010 struct e1000_hw;
0011 
0012 #define E1000_DEV_ID_82571EB_COPPER     0x105E
0013 #define E1000_DEV_ID_82571EB_FIBER      0x105F
0014 #define E1000_DEV_ID_82571EB_SERDES     0x1060
0015 #define E1000_DEV_ID_82571EB_QUAD_COPPER    0x10A4
0016 #define E1000_DEV_ID_82571PT_QUAD_COPPER    0x10D5
0017 #define E1000_DEV_ID_82571EB_QUAD_FIBER     0x10A5
0018 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
0019 #define E1000_DEV_ID_82571EB_SERDES_DUAL    0x10D9
0020 #define E1000_DEV_ID_82571EB_SERDES_QUAD    0x10DA
0021 #define E1000_DEV_ID_82572EI_COPPER     0x107D
0022 #define E1000_DEV_ID_82572EI_FIBER      0x107E
0023 #define E1000_DEV_ID_82572EI_SERDES     0x107F
0024 #define E1000_DEV_ID_82572EI            0x10B9
0025 #define E1000_DEV_ID_82573E         0x108B
0026 #define E1000_DEV_ID_82573E_IAMT        0x108C
0027 #define E1000_DEV_ID_82573L         0x109A
0028 #define E1000_DEV_ID_82574L         0x10D3
0029 #define E1000_DEV_ID_82574LA            0x10F6
0030 #define E1000_DEV_ID_82583V         0x150C
0031 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
0032 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
0033 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
0034 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
0035 #define E1000_DEV_ID_ICH8_82567V_3      0x1501
0036 #define E1000_DEV_ID_ICH8_IGP_M_AMT     0x1049
0037 #define E1000_DEV_ID_ICH8_IGP_AMT       0x104A
0038 #define E1000_DEV_ID_ICH8_IGP_C         0x104B
0039 #define E1000_DEV_ID_ICH8_IFE           0x104C
0040 #define E1000_DEV_ID_ICH8_IFE_GT        0x10C4
0041 #define E1000_DEV_ID_ICH8_IFE_G         0x10C5
0042 #define E1000_DEV_ID_ICH8_IGP_M         0x104D
0043 #define E1000_DEV_ID_ICH9_IGP_AMT       0x10BD
0044 #define E1000_DEV_ID_ICH9_BM            0x10E5
0045 #define E1000_DEV_ID_ICH9_IGP_M_AMT     0x10F5
0046 #define E1000_DEV_ID_ICH9_IGP_M         0x10BF
0047 #define E1000_DEV_ID_ICH9_IGP_M_V       0x10CB
0048 #define E1000_DEV_ID_ICH9_IGP_C         0x294C
0049 #define E1000_DEV_ID_ICH9_IFE           0x10C0
0050 #define E1000_DEV_ID_ICH9_IFE_GT        0x10C3
0051 #define E1000_DEV_ID_ICH9_IFE_G         0x10C2
0052 #define E1000_DEV_ID_ICH10_R_BM_LM      0x10CC
0053 #define E1000_DEV_ID_ICH10_R_BM_LF      0x10CD
0054 #define E1000_DEV_ID_ICH10_R_BM_V       0x10CE
0055 #define E1000_DEV_ID_ICH10_D_BM_LM      0x10DE
0056 #define E1000_DEV_ID_ICH10_D_BM_LF      0x10DF
0057 #define E1000_DEV_ID_ICH10_D_BM_V       0x1525
0058 #define E1000_DEV_ID_PCH_M_HV_LM        0x10EA
0059 #define E1000_DEV_ID_PCH_M_HV_LC        0x10EB
0060 #define E1000_DEV_ID_PCH_D_HV_DM        0x10EF
0061 #define E1000_DEV_ID_PCH_D_HV_DC        0x10F0
0062 #define E1000_DEV_ID_PCH2_LV_LM         0x1502
0063 #define E1000_DEV_ID_PCH2_LV_V          0x1503
0064 #define E1000_DEV_ID_PCH_LPT_I217_LM        0x153A
0065 #define E1000_DEV_ID_PCH_LPT_I217_V     0x153B
0066 #define E1000_DEV_ID_PCH_LPTLP_I218_LM      0x155A
0067 #define E1000_DEV_ID_PCH_LPTLP_I218_V       0x1559
0068 #define E1000_DEV_ID_PCH_I218_LM2       0x15A0
0069 #define E1000_DEV_ID_PCH_I218_V2        0x15A1
0070 #define E1000_DEV_ID_PCH_I218_LM3       0x15A2  /* Wildcat Point PCH */
0071 #define E1000_DEV_ID_PCH_I218_V3        0x15A3  /* Wildcat Point PCH */
0072 #define E1000_DEV_ID_PCH_SPT_I219_LM        0x156F  /* SPT PCH */
0073 #define E1000_DEV_ID_PCH_SPT_I219_V     0x1570  /* SPT PCH */
0074 #define E1000_DEV_ID_PCH_SPT_I219_LM2       0x15B7  /* SPT-H PCH */
0075 #define E1000_DEV_ID_PCH_SPT_I219_V2        0x15B8  /* SPT-H PCH */
0076 #define E1000_DEV_ID_PCH_LBG_I219_LM3       0x15B9  /* LBG PCH */
0077 #define E1000_DEV_ID_PCH_SPT_I219_LM4       0x15D7
0078 #define E1000_DEV_ID_PCH_SPT_I219_V4        0x15D8
0079 #define E1000_DEV_ID_PCH_SPT_I219_LM5       0x15E3
0080 #define E1000_DEV_ID_PCH_SPT_I219_V5        0x15D6
0081 #define E1000_DEV_ID_PCH_CNP_I219_LM6       0x15BD
0082 #define E1000_DEV_ID_PCH_CNP_I219_V6        0x15BE
0083 #define E1000_DEV_ID_PCH_CNP_I219_LM7       0x15BB
0084 #define E1000_DEV_ID_PCH_CNP_I219_V7        0x15BC
0085 #define E1000_DEV_ID_PCH_ICP_I219_LM8       0x15DF
0086 #define E1000_DEV_ID_PCH_ICP_I219_V8        0x15E0
0087 #define E1000_DEV_ID_PCH_ICP_I219_LM9       0x15E1
0088 #define E1000_DEV_ID_PCH_ICP_I219_V9        0x15E2
0089 #define E1000_DEV_ID_PCH_CMP_I219_LM10      0x0D4E
0090 #define E1000_DEV_ID_PCH_CMP_I219_V10       0x0D4F
0091 #define E1000_DEV_ID_PCH_CMP_I219_LM11      0x0D4C
0092 #define E1000_DEV_ID_PCH_CMP_I219_V11       0x0D4D
0093 #define E1000_DEV_ID_PCH_CMP_I219_LM12      0x0D53
0094 #define E1000_DEV_ID_PCH_CMP_I219_V12       0x0D55
0095 #define E1000_DEV_ID_PCH_TGP_I219_LM13      0x15FB
0096 #define E1000_DEV_ID_PCH_TGP_I219_V13       0x15FC
0097 #define E1000_DEV_ID_PCH_TGP_I219_LM14      0x15F9
0098 #define E1000_DEV_ID_PCH_TGP_I219_V14       0x15FA
0099 #define E1000_DEV_ID_PCH_TGP_I219_LM15      0x15F4
0100 #define E1000_DEV_ID_PCH_TGP_I219_V15       0x15F5
0101 #define E1000_DEV_ID_PCH_RPL_I219_LM23      0x0DC5
0102 #define E1000_DEV_ID_PCH_RPL_I219_V23       0x0DC6
0103 #define E1000_DEV_ID_PCH_ADP_I219_LM16      0x1A1E
0104 #define E1000_DEV_ID_PCH_ADP_I219_V16       0x1A1F
0105 #define E1000_DEV_ID_PCH_ADP_I219_LM17      0x1A1C
0106 #define E1000_DEV_ID_PCH_ADP_I219_V17       0x1A1D
0107 #define E1000_DEV_ID_PCH_RPL_I219_LM22      0x0DC7
0108 #define E1000_DEV_ID_PCH_RPL_I219_V22       0x0DC8
0109 #define E1000_DEV_ID_PCH_MTP_I219_LM18      0x550A
0110 #define E1000_DEV_ID_PCH_MTP_I219_V18       0x550B
0111 #define E1000_DEV_ID_PCH_MTP_I219_LM19      0x550C
0112 #define E1000_DEV_ID_PCH_MTP_I219_V19       0x550D
0113 #define E1000_DEV_ID_PCH_LNP_I219_LM20      0x550E
0114 #define E1000_DEV_ID_PCH_LNP_I219_V20       0x550F
0115 #define E1000_DEV_ID_PCH_LNP_I219_LM21      0x5510
0116 #define E1000_DEV_ID_PCH_LNP_I219_V21       0x5511
0117 
0118 #define E1000_REVISION_4    4
0119 
0120 #define E1000_FUNC_1        1
0121 
0122 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
0123 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
0124 
0125 enum e1000_mac_type {
0126     e1000_82571,
0127     e1000_82572,
0128     e1000_82573,
0129     e1000_82574,
0130     e1000_82583,
0131     e1000_80003es2lan,
0132     e1000_ich8lan,
0133     e1000_ich9lan,
0134     e1000_ich10lan,
0135     e1000_pchlan,
0136     e1000_pch2lan,
0137     e1000_pch_lpt,
0138     e1000_pch_spt,
0139     e1000_pch_cnp,
0140     e1000_pch_tgp,
0141     e1000_pch_adp,
0142     e1000_pch_mtp,
0143     e1000_pch_lnp,
0144 };
0145 
0146 enum e1000_media_type {
0147     e1000_media_type_unknown = 0,
0148     e1000_media_type_copper = 1,
0149     e1000_media_type_fiber = 2,
0150     e1000_media_type_internal_serdes = 3,
0151     e1000_num_media_types
0152 };
0153 
0154 enum e1000_nvm_type {
0155     e1000_nvm_unknown = 0,
0156     e1000_nvm_none,
0157     e1000_nvm_eeprom_spi,
0158     e1000_nvm_flash_hw,
0159     e1000_nvm_flash_sw
0160 };
0161 
0162 enum e1000_nvm_override {
0163     e1000_nvm_override_none = 0,
0164     e1000_nvm_override_spi_small,
0165     e1000_nvm_override_spi_large
0166 };
0167 
0168 enum e1000_phy_type {
0169     e1000_phy_unknown = 0,
0170     e1000_phy_none,
0171     e1000_phy_m88,
0172     e1000_phy_igp,
0173     e1000_phy_igp_2,
0174     e1000_phy_gg82563,
0175     e1000_phy_igp_3,
0176     e1000_phy_ife,
0177     e1000_phy_bm,
0178     e1000_phy_82578,
0179     e1000_phy_82577,
0180     e1000_phy_82579,
0181     e1000_phy_i217,
0182 };
0183 
0184 enum e1000_bus_width {
0185     e1000_bus_width_unknown = 0,
0186     e1000_bus_width_pcie_x1,
0187     e1000_bus_width_pcie_x2,
0188     e1000_bus_width_pcie_x4 = 4,
0189     e1000_bus_width_pcie_x8 = 8,
0190     e1000_bus_width_32,
0191     e1000_bus_width_64,
0192     e1000_bus_width_reserved
0193 };
0194 
0195 enum e1000_1000t_rx_status {
0196     e1000_1000t_rx_status_not_ok = 0,
0197     e1000_1000t_rx_status_ok,
0198     e1000_1000t_rx_status_undefined = 0xFF
0199 };
0200 
0201 enum e1000_rev_polarity {
0202     e1000_rev_polarity_normal = 0,
0203     e1000_rev_polarity_reversed,
0204     e1000_rev_polarity_undefined = 0xFF
0205 };
0206 
0207 enum e1000_fc_mode {
0208     e1000_fc_none = 0,
0209     e1000_fc_rx_pause,
0210     e1000_fc_tx_pause,
0211     e1000_fc_full,
0212     e1000_fc_default = 0xFF
0213 };
0214 
0215 enum e1000_ms_type {
0216     e1000_ms_hw_default = 0,
0217     e1000_ms_force_master,
0218     e1000_ms_force_slave,
0219     e1000_ms_auto
0220 };
0221 
0222 enum e1000_smart_speed {
0223     e1000_smart_speed_default = 0,
0224     e1000_smart_speed_on,
0225     e1000_smart_speed_off
0226 };
0227 
0228 enum e1000_serdes_link_state {
0229     e1000_serdes_link_down = 0,
0230     e1000_serdes_link_autoneg_progress,
0231     e1000_serdes_link_autoneg_complete,
0232     e1000_serdes_link_forced_up
0233 };
0234 
0235 /* Receive Descriptor - Extended */
0236 union e1000_rx_desc_extended {
0237     struct {
0238         __le64 buffer_addr;
0239         __le64 reserved;
0240     } read;
0241     struct {
0242         struct {
0243             __le32 mrq;       /* Multiple Rx Queues */
0244             union {
0245                 __le32 rss;     /* RSS Hash */
0246                 struct {
0247                     __le16 ip_id;  /* IP id */
0248                     __le16 csum;   /* Packet Checksum */
0249                 } csum_ip;
0250             } hi_dword;
0251         } lower;
0252         struct {
0253             __le32 status_error;     /* ext status/error */
0254             __le16 length;
0255             __le16 vlan;         /* VLAN tag */
0256         } upper;
0257     } wb;  /* writeback */
0258 };
0259 
0260 #define MAX_PS_BUFFERS 4
0261 
0262 /* Number of packet split data buffers (not including the header buffer) */
0263 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
0264 
0265 /* Receive Descriptor - Packet Split */
0266 union e1000_rx_desc_packet_split {
0267     struct {
0268         /* one buffer for protocol header(s), three data buffers */
0269         __le64 buffer_addr[MAX_PS_BUFFERS];
0270     } read;
0271     struct {
0272         struct {
0273             __le32 mrq;       /* Multiple Rx Queues */
0274             union {
0275                 __le32 rss;       /* RSS Hash */
0276                 struct {
0277                     __le16 ip_id;    /* IP id */
0278                     __le16 csum;     /* Packet Checksum */
0279                 } csum_ip;
0280             } hi_dword;
0281         } lower;
0282         struct {
0283             __le32 status_error;     /* ext status/error */
0284             __le16 length0;   /* length of buffer 0 */
0285             __le16 vlan;         /* VLAN tag */
0286         } middle;
0287         struct {
0288             __le16 header_status;
0289             /* length of buffers 1-3 */
0290             __le16 length[PS_PAGE_BUFFERS];
0291         } upper;
0292         __le64 reserved;
0293     } wb; /* writeback */
0294 };
0295 
0296 /* Transmit Descriptor */
0297 struct e1000_tx_desc {
0298     __le64 buffer_addr;      /* Address of the descriptor's data buffer */
0299     union {
0300         __le32 data;
0301         struct {
0302             __le16 length;    /* Data buffer length */
0303             u8 cso; /* Checksum offset */
0304             u8 cmd; /* Descriptor control */
0305         } flags;
0306     } lower;
0307     union {
0308         __le32 data;
0309         struct {
0310             u8 status;     /* Descriptor status */
0311             u8 css; /* Checksum start */
0312             __le16 special;
0313         } fields;
0314     } upper;
0315 };
0316 
0317 /* Offload Context Descriptor */
0318 struct e1000_context_desc {
0319     union {
0320         __le32 ip_config;
0321         struct {
0322             u8 ipcss;      /* IP checksum start */
0323             u8 ipcso;      /* IP checksum offset */
0324             __le16 ipcse;     /* IP checksum end */
0325         } ip_fields;
0326     } lower_setup;
0327     union {
0328         __le32 tcp_config;
0329         struct {
0330             u8 tucss;      /* TCP checksum start */
0331             u8 tucso;      /* TCP checksum offset */
0332             __le16 tucse;     /* TCP checksum end */
0333         } tcp_fields;
0334     } upper_setup;
0335     __le32 cmd_and_length;
0336     union {
0337         __le32 data;
0338         struct {
0339             u8 status;     /* Descriptor status */
0340             u8 hdr_len;    /* Header length */
0341             __le16 mss;       /* Maximum segment size */
0342         } fields;
0343     } tcp_seg_setup;
0344 };
0345 
0346 /* Offload data descriptor */
0347 struct e1000_data_desc {
0348     __le64 buffer_addr;   /* Address of the descriptor's buffer address */
0349     union {
0350         __le32 data;
0351         struct {
0352             __le16 length;    /* Data buffer length */
0353             u8 typ_len_ext;
0354             u8 cmd;
0355         } flags;
0356     } lower;
0357     union {
0358         __le32 data;
0359         struct {
0360             u8 status;     /* Descriptor status */
0361             u8 popts;      /* Packet Options */
0362             __le16 special;
0363         } fields;
0364     } upper;
0365 };
0366 
0367 /* Statistics counters collected by the MAC */
0368 struct e1000_hw_stats {
0369     u64 crcerrs;
0370     u64 algnerrc;
0371     u64 symerrs;
0372     u64 rxerrc;
0373     u64 mpc;
0374     u64 scc;
0375     u64 ecol;
0376     u64 mcc;
0377     u64 latecol;
0378     u64 colc;
0379     u64 dc;
0380     u64 tncrs;
0381     u64 sec;
0382     u64 cexterr;
0383     u64 rlec;
0384     u64 xonrxc;
0385     u64 xontxc;
0386     u64 xoffrxc;
0387     u64 xofftxc;
0388     u64 fcruc;
0389     u64 prc64;
0390     u64 prc127;
0391     u64 prc255;
0392     u64 prc511;
0393     u64 prc1023;
0394     u64 prc1522;
0395     u64 gprc;
0396     u64 bprc;
0397     u64 mprc;
0398     u64 gptc;
0399     u64 gorc;
0400     u64 gotc;
0401     u64 rnbc;
0402     u64 ruc;
0403     u64 rfc;
0404     u64 roc;
0405     u64 rjc;
0406     u64 mgprc;
0407     u64 mgpdc;
0408     u64 mgptc;
0409     u64 tor;
0410     u64 tot;
0411     u64 tpr;
0412     u64 tpt;
0413     u64 ptc64;
0414     u64 ptc127;
0415     u64 ptc255;
0416     u64 ptc511;
0417     u64 ptc1023;
0418     u64 ptc1522;
0419     u64 mptc;
0420     u64 bptc;
0421     u64 tsctc;
0422     u64 tsctfc;
0423     u64 iac;
0424     u64 icrxptc;
0425     u64 icrxatc;
0426     u64 ictxptc;
0427     u64 ictxatc;
0428     u64 ictxqec;
0429     u64 ictxqmtc;
0430     u64 icrxdmtc;
0431     u64 icrxoc;
0432 };
0433 
0434 struct e1000_phy_stats {
0435     u32 idle_errors;
0436     u32 receive_errors;
0437 };
0438 
0439 struct e1000_host_mng_dhcp_cookie {
0440     u32 signature;
0441     u8 status;
0442     u8 reserved0;
0443     u16 vlan_id;
0444     u32 reserved1;
0445     u16 reserved2;
0446     u8 reserved3;
0447     u8 checksum;
0448 };
0449 
0450 /* Host Interface "Rev 1" */
0451 struct e1000_host_command_header {
0452     u8 command_id;
0453     u8 command_length;
0454     u8 command_options;
0455     u8 checksum;
0456 };
0457 
0458 #define E1000_HI_MAX_DATA_LENGTH    252
0459 struct e1000_host_command_info {
0460     struct e1000_host_command_header command_header;
0461     u8 command_data[E1000_HI_MAX_DATA_LENGTH];
0462 };
0463 
0464 /* Host Interface "Rev 2" */
0465 struct e1000_host_mng_command_header {
0466     u8 command_id;
0467     u8 checksum;
0468     u16 reserved1;
0469     u16 reserved2;
0470     u16 command_length;
0471 };
0472 
0473 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
0474 struct e1000_host_mng_command_info {
0475     struct e1000_host_mng_command_header command_header;
0476     u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
0477 };
0478 
0479 #include "mac.h"
0480 #include "phy.h"
0481 #include "nvm.h"
0482 #include "manage.h"
0483 
0484 /* Function pointers for the MAC. */
0485 struct e1000_mac_operations {
0486     s32  (*id_led_init)(struct e1000_hw *);
0487     s32  (*blink_led)(struct e1000_hw *);
0488     bool (*check_mng_mode)(struct e1000_hw *);
0489     s32  (*check_for_link)(struct e1000_hw *);
0490     s32  (*cleanup_led)(struct e1000_hw *);
0491     void (*clear_hw_cntrs)(struct e1000_hw *);
0492     void (*clear_vfta)(struct e1000_hw *);
0493     s32  (*get_bus_info)(struct e1000_hw *);
0494     void (*set_lan_id)(struct e1000_hw *);
0495     s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
0496     s32  (*led_on)(struct e1000_hw *);
0497     s32  (*led_off)(struct e1000_hw *);
0498     void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
0499     s32  (*reset_hw)(struct e1000_hw *);
0500     s32  (*init_hw)(struct e1000_hw *);
0501     s32  (*setup_link)(struct e1000_hw *);
0502     s32  (*setup_physical_interface)(struct e1000_hw *);
0503     s32  (*setup_led)(struct e1000_hw *);
0504     void (*write_vfta)(struct e1000_hw *, u32, u32);
0505     void (*config_collision_dist)(struct e1000_hw *);
0506     int  (*rar_set)(struct e1000_hw *, u8 *, u32);
0507     s32  (*read_mac_addr)(struct e1000_hw *);
0508     u32  (*rar_get_count)(struct e1000_hw *);
0509 };
0510 
0511 /* When to use various PHY register access functions:
0512  *
0513  *                 Func   Caller
0514  *   Function      Does   Does    When to use
0515  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0516  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
0517  *   X_reg_locked  P,A    L       for multiple accesses of different regs
0518  *                                on different pages
0519  *   X_reg_page    A      L,P     for multiple accesses of different regs
0520  *                                on the same page
0521  *
0522  * Where X=[read|write], L=locking, P=sets page, A=register access
0523  *
0524  */
0525 struct e1000_phy_operations {
0526     s32  (*acquire)(struct e1000_hw *);
0527     s32  (*cfg_on_link_up)(struct e1000_hw *);
0528     s32  (*check_polarity)(struct e1000_hw *);
0529     s32  (*check_reset_block)(struct e1000_hw *);
0530     s32  (*commit)(struct e1000_hw *);
0531     s32  (*force_speed_duplex)(struct e1000_hw *);
0532     s32  (*get_cfg_done)(struct e1000_hw *hw);
0533     s32  (*get_cable_length)(struct e1000_hw *);
0534     s32  (*get_info)(struct e1000_hw *);
0535     s32  (*set_page)(struct e1000_hw *, u16);
0536     s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
0537     s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
0538     s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
0539     void (*release)(struct e1000_hw *);
0540     s32  (*reset)(struct e1000_hw *);
0541     s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
0542     s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
0543     s32  (*write_reg)(struct e1000_hw *, u32, u16);
0544     s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
0545     s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
0546     void (*power_up)(struct e1000_hw *);
0547     void (*power_down)(struct e1000_hw *);
0548 };
0549 
0550 /* Function pointers for the NVM. */
0551 struct e1000_nvm_operations {
0552     s32  (*acquire)(struct e1000_hw *);
0553     s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
0554     void (*release)(struct e1000_hw *);
0555     void (*reload)(struct e1000_hw *);
0556     s32  (*update)(struct e1000_hw *);
0557     s32  (*valid_led_default)(struct e1000_hw *, u16 *);
0558     s32  (*validate)(struct e1000_hw *);
0559     s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
0560 };
0561 
0562 struct e1000_mac_info {
0563     struct e1000_mac_operations ops;
0564     u8 addr[ETH_ALEN];
0565     u8 perm_addr[ETH_ALEN];
0566 
0567     enum e1000_mac_type type;
0568 
0569     u32 collision_delta;
0570     u32 ledctl_default;
0571     u32 ledctl_mode1;
0572     u32 ledctl_mode2;
0573     u32 mc_filter_type;
0574     u32 tx_packet_delta;
0575     u32 txcw;
0576 
0577     u16 current_ifs_val;
0578     u16 ifs_max_val;
0579     u16 ifs_min_val;
0580     u16 ifs_ratio;
0581     u16 ifs_step_size;
0582     u16 mta_reg_count;
0583 
0584     /* Maximum size of the MTA register table in all supported adapters */
0585 #define MAX_MTA_REG 128
0586     u32 mta_shadow[MAX_MTA_REG];
0587     u16 rar_entry_count;
0588 
0589     u8 forced_speed_duplex;
0590 
0591     bool adaptive_ifs;
0592     bool has_fwsm;
0593     bool arc_subsystem_valid;
0594     bool autoneg;
0595     bool autoneg_failed;
0596     bool get_link_status;
0597     bool in_ifs_mode;
0598     bool serdes_has_link;
0599     bool tx_pkt_filtering;
0600     enum e1000_serdes_link_state serdes_link_state;
0601 };
0602 
0603 struct e1000_phy_info {
0604     struct e1000_phy_operations ops;
0605 
0606     enum e1000_phy_type type;
0607 
0608     enum e1000_1000t_rx_status local_rx;
0609     enum e1000_1000t_rx_status remote_rx;
0610     enum e1000_ms_type ms_type;
0611     enum e1000_ms_type original_ms_type;
0612     enum e1000_rev_polarity cable_polarity;
0613     enum e1000_smart_speed smart_speed;
0614 
0615     u32 addr;
0616     u32 id;
0617     u32 reset_delay_us; /* in usec */
0618     u32 revision;
0619 
0620     enum e1000_media_type media_type;
0621 
0622     u16 autoneg_advertised;
0623     u16 autoneg_mask;
0624     u16 cable_length;
0625     u16 max_cable_length;
0626     u16 min_cable_length;
0627 
0628     u8 mdix;
0629 
0630     bool disable_polarity_correction;
0631     bool is_mdix;
0632     bool polarity_correction;
0633     bool speed_downgraded;
0634     bool autoneg_wait_to_complete;
0635 };
0636 
0637 struct e1000_nvm_info {
0638     struct e1000_nvm_operations ops;
0639 
0640     enum e1000_nvm_type type;
0641     enum e1000_nvm_override override;
0642 
0643     u32 flash_bank_size;
0644     u32 flash_base_addr;
0645 
0646     u16 word_size;
0647     u16 delay_usec;
0648     u16 address_bits;
0649     u16 opcode_bits;
0650     u16 page_size;
0651 };
0652 
0653 struct e1000_bus_info {
0654     enum e1000_bus_width width;
0655 
0656     u16 func;
0657 };
0658 
0659 struct e1000_fc_info {
0660     u32 high_water;          /* Flow control high-water mark */
0661     u32 low_water;           /* Flow control low-water mark */
0662     u16 pause_time;          /* Flow control pause timer */
0663     u16 refresh_time;        /* Flow control refresh timer */
0664     bool send_xon;           /* Flow control send XON */
0665     bool strict_ieee;        /* Strict IEEE mode */
0666     enum e1000_fc_mode current_mode; /* FC mode in effect */
0667     enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
0668 };
0669 
0670 struct e1000_dev_spec_82571 {
0671     bool laa_is_present;
0672     u32 smb_counter;
0673 };
0674 
0675 struct e1000_dev_spec_80003es2lan {
0676     bool mdic_wa_enable;
0677 };
0678 
0679 struct e1000_shadow_ram {
0680     u16 value;
0681     bool modified;
0682 };
0683 
0684 #define E1000_ICH8_SHADOW_RAM_WORDS     2048
0685 
0686 /* I218 PHY Ultra Low Power (ULP) states */
0687 enum e1000_ulp_state {
0688     e1000_ulp_state_unknown,
0689     e1000_ulp_state_off,
0690     e1000_ulp_state_on,
0691 };
0692 
0693 struct e1000_dev_spec_ich8lan {
0694     bool kmrn_lock_loss_workaround_enabled;
0695     struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
0696     bool nvm_k1_enabled;
0697     bool eee_disable;
0698     u16 eee_lp_ability;
0699     enum e1000_ulp_state ulp_state;
0700 };
0701 
0702 struct e1000_hw {
0703     struct e1000_adapter *adapter;
0704 
0705     void __iomem *hw_addr;
0706     void __iomem *flash_address;
0707 
0708     struct e1000_mac_info mac;
0709     struct e1000_fc_info fc;
0710     struct e1000_phy_info phy;
0711     struct e1000_nvm_info nvm;
0712     struct e1000_bus_info bus;
0713     struct e1000_host_mng_dhcp_cookie mng_cookie;
0714 
0715     union {
0716         struct e1000_dev_spec_82571 e82571;
0717         struct e1000_dev_spec_80003es2lan e80003es2lan;
0718         struct e1000_dev_spec_ich8lan ich8lan;
0719     } dev_spec;
0720 };
0721 
0722 #include "82571.h"
0723 #include "80003es2lan.h"
0724 #include "ich8lan.h"
0725 
0726 #endif /* _E1000E_HW_H_ */
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