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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003 
0004 /* Linux PRO/1000 Ethernet Driver main header file */
0005 
0006 #ifndef _E1000_H_
0007 #define _E1000_H_
0008 
0009 #include <linux/bitops.h>
0010 #include <linux/types.h>
0011 #include <linux/timer.h>
0012 #include <linux/workqueue.h>
0013 #include <linux/io.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/pci.h>
0016 #include <linux/crc32.h>
0017 #include <linux/if_vlan.h>
0018 #include <linux/timecounter.h>
0019 #include <linux/net_tstamp.h>
0020 #include <linux/ptp_clock_kernel.h>
0021 #include <linux/ptp_classify.h>
0022 #include <linux/mii.h>
0023 #include <linux/mdio.h>
0024 #include <linux/mutex.h>
0025 #include <linux/pm_qos.h>
0026 #include "hw.h"
0027 
0028 struct e1000_info;
0029 
0030 #define e_dbg(format, arg...) \
0031     netdev_dbg(hw->adapter->netdev, format, ## arg)
0032 #define e_err(format, arg...) \
0033     netdev_err(adapter->netdev, format, ## arg)
0034 #define e_info(format, arg...) \
0035     netdev_info(adapter->netdev, format, ## arg)
0036 #define e_warn(format, arg...) \
0037     netdev_warn(adapter->netdev, format, ## arg)
0038 #define e_notice(format, arg...) \
0039     netdev_notice(adapter->netdev, format, ## arg)
0040 
0041 /* Interrupt modes, as used by the IntMode parameter */
0042 #define E1000E_INT_MODE_LEGACY      0
0043 #define E1000E_INT_MODE_MSI     1
0044 #define E1000E_INT_MODE_MSIX        2
0045 
0046 /* Tx/Rx descriptor defines */
0047 #define E1000_DEFAULT_TXD       256
0048 #define E1000_MAX_TXD           4096
0049 #define E1000_MIN_TXD           64
0050 
0051 #define E1000_DEFAULT_RXD       256
0052 #define E1000_MAX_RXD           4096
0053 #define E1000_MIN_RXD           64
0054 
0055 #define E1000_MIN_ITR_USECS     10 /* 100000 irq/sec */
0056 #define E1000_MAX_ITR_USECS     10000 /* 100    irq/sec */
0057 
0058 #define E1000_FC_PAUSE_TIME     0x0680 /* 858 usec */
0059 
0060 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
0061 /* How many Rx Buffers do we bundle into one write to the hardware ? */
0062 #define E1000_RX_BUFFER_WRITE       16 /* Must be power of 2 */
0063 
0064 #define AUTO_ALL_MODES          0
0065 #define E1000_EEPROM_APME       0x0400
0066 
0067 #define E1000_MNG_VLAN_NONE     (-1)
0068 
0069 #define DEFAULT_JUMBO           9234
0070 
0071 /* Time to wait before putting the device into D3 if there's no link (in ms). */
0072 #define LINK_TIMEOUT        100
0073 
0074 /* Count for polling __E1000_RESET condition every 10-20msec.
0075  * Experimentation has shown the reset can take approximately 210msec.
0076  */
0077 #define E1000_CHECK_RESET_COUNT     25
0078 
0079 #define PCICFG_DESC_RING_STATUS     0xe4
0080 #define FLUSH_DESC_REQUIRED     0x100
0081 
0082 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
0083  * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
0084  * WTHRESH=4, so a setting of 5 gives the most efficient bus
0085  * utilization but to avoid possible Tx stalls, set it to 1
0086  */
0087 #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
0088     (E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
0089      E1000_TXDCTL_COUNT_DESC |                             \
0090      (1u << 16) | /* wthresh must be +1 more than desired */\
0091      (1u << 8)  | /* hthresh */                             \
0092      0x1f)        /* pthresh */
0093 
0094 #define E1000_RXDCTL_DMA_BURST_ENABLE                          \
0095     (0x01000000 | /* set descriptor granularity */         \
0096      (4u << 16) | /* set writeback threshold    */         \
0097      (4u << 8)  | /* set prefetch threshold     */         \
0098      0x20)        /* set hthresh                */
0099 
0100 #define E1000_TIDV_FPD BIT(31)
0101 #define E1000_RDTR_FPD BIT(31)
0102 
0103 enum e1000_boards {
0104     board_82571,
0105     board_82572,
0106     board_82573,
0107     board_82574,
0108     board_82583,
0109     board_80003es2lan,
0110     board_ich8lan,
0111     board_ich9lan,
0112     board_ich10lan,
0113     board_pchlan,
0114     board_pch2lan,
0115     board_pch_lpt,
0116     board_pch_spt,
0117     board_pch_cnp,
0118     board_pch_tgp,
0119     board_pch_adp
0120 };
0121 
0122 struct e1000_ps_page {
0123     struct page *page;
0124     u64 dma; /* must be u64 - written to hw */
0125 };
0126 
0127 /* wrappers around a pointer to a socket buffer,
0128  * so a DMA handle can be stored along with the buffer
0129  */
0130 struct e1000_buffer {
0131     dma_addr_t dma;
0132     struct sk_buff *skb;
0133     union {
0134         /* Tx */
0135         struct {
0136             unsigned long time_stamp;
0137             u16 length;
0138             u16 next_to_watch;
0139             unsigned int segs;
0140             unsigned int bytecount;
0141             u16 mapped_as_page;
0142         };
0143         /* Rx */
0144         struct {
0145             /* arrays of page information for packet split */
0146             struct e1000_ps_page *ps_pages;
0147             struct page *page;
0148         };
0149     };
0150 };
0151 
0152 struct e1000_ring {
0153     struct e1000_adapter *adapter;  /* back pointer to adapter */
0154     void *desc;         /* pointer to ring memory  */
0155     dma_addr_t dma;         /* phys address of ring    */
0156     unsigned int size;      /* length of ring in bytes */
0157     unsigned int count;     /* number of desc. in ring */
0158 
0159     u16 next_to_use;
0160     u16 next_to_clean;
0161 
0162     void __iomem *head;
0163     void __iomem *tail;
0164 
0165     /* array of buffer information structs */
0166     struct e1000_buffer *buffer_info;
0167 
0168     char name[IFNAMSIZ + 5];
0169     u32 ims_val;
0170     u32 itr_val;
0171     void __iomem *itr_register;
0172     int set_itr;
0173 
0174     struct sk_buff *rx_skb_top;
0175 };
0176 
0177 /* PHY register snapshot values */
0178 struct e1000_phy_regs {
0179     u16 bmcr;       /* basic mode control register    */
0180     u16 bmsr;       /* basic mode status register     */
0181     u16 advertise;      /* auto-negotiation advertisement */
0182     u16 lpa;        /* link partner ability register  */
0183     u16 expansion;      /* auto-negotiation expansion reg */
0184     u16 ctrl1000;       /* 1000BASE-T control register    */
0185     u16 stat1000;       /* 1000BASE-T status register     */
0186     u16 estatus;        /* extended status register       */
0187 };
0188 
0189 /* board specific private data structure */
0190 struct e1000_adapter {
0191     struct timer_list watchdog_timer;
0192     struct timer_list phy_info_timer;
0193     struct timer_list blink_timer;
0194 
0195     struct work_struct reset_task;
0196     struct work_struct watchdog_task;
0197 
0198     const struct e1000_info *ei;
0199 
0200     unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0201     u32 bd_number;
0202     u32 rx_buffer_len;
0203     u16 mng_vlan_id;
0204     u16 link_speed;
0205     u16 link_duplex;
0206     u16 eeprom_vers;
0207 
0208     /* track device up/down/testing state */
0209     unsigned long state;
0210 
0211     /* Interrupt Throttle Rate */
0212     u32 itr;
0213     u32 itr_setting;
0214     u16 tx_itr;
0215     u16 rx_itr;
0216 
0217     /* Tx - one ring per active queue */
0218     struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
0219     u32 tx_fifo_limit;
0220 
0221     struct napi_struct napi;
0222 
0223     unsigned int uncorr_errors; /* uncorrectable ECC errors */
0224     unsigned int corr_errors;   /* correctable ECC errors */
0225     unsigned int restart_queue;
0226     u32 txd_cmd;
0227 
0228     bool detect_tx_hung;
0229     bool tx_hang_recheck;
0230     u8 tx_timeout_factor;
0231 
0232     u32 tx_int_delay;
0233     u32 tx_abs_int_delay;
0234 
0235     unsigned int total_tx_bytes;
0236     unsigned int total_tx_packets;
0237     unsigned int total_rx_bytes;
0238     unsigned int total_rx_packets;
0239 
0240     /* Tx stats */
0241     u64 tpt_old;
0242     u64 colc_old;
0243     u32 gotc;
0244     u64 gotc_old;
0245     u32 tx_timeout_count;
0246     u32 tx_fifo_head;
0247     u32 tx_head_addr;
0248     u32 tx_fifo_size;
0249     u32 tx_dma_failed;
0250     u32 tx_hwtstamp_timeouts;
0251     u32 tx_hwtstamp_skipped;
0252 
0253     /* Rx */
0254     bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
0255              int work_to_do) ____cacheline_aligned_in_smp;
0256     void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
0257                  gfp_t gfp);
0258     struct e1000_ring *rx_ring;
0259 
0260     u32 rx_int_delay;
0261     u32 rx_abs_int_delay;
0262 
0263     /* Rx stats */
0264     u64 hw_csum_err;
0265     u64 hw_csum_good;
0266     u64 rx_hdr_split;
0267     u32 gorc;
0268     u64 gorc_old;
0269     u32 alloc_rx_buff_failed;
0270     u32 rx_dma_failed;
0271     u32 rx_hwtstamp_cleared;
0272 
0273     unsigned int rx_ps_pages;
0274     u16 rx_ps_bsize0;
0275     u32 max_frame_size;
0276     u32 min_frame_size;
0277 
0278     /* OS defined structs */
0279     struct net_device *netdev;
0280     struct pci_dev *pdev;
0281 
0282     /* structs defined in e1000_hw.h */
0283     struct e1000_hw hw;
0284 
0285     spinlock_t stats64_lock;    /* protects statistics counters */
0286     struct e1000_hw_stats stats;
0287     struct e1000_phy_info phy_info;
0288     struct e1000_phy_stats phy_stats;
0289 
0290     /* Snapshot of PHY registers */
0291     struct e1000_phy_regs phy_regs;
0292 
0293     struct e1000_ring test_tx_ring;
0294     struct e1000_ring test_rx_ring;
0295     u32 test_icr;
0296 
0297     u32 msg_enable;
0298     unsigned int num_vectors;
0299     struct msix_entry *msix_entries;
0300     int int_mode;
0301     u32 eiac_mask;
0302 
0303     u32 eeprom_wol;
0304     u32 wol;
0305     u32 pba;
0306     u32 max_hw_frame_size;
0307 
0308     bool fc_autoneg;
0309 
0310     unsigned int flags;
0311     unsigned int flags2;
0312     struct work_struct downshift_task;
0313     struct work_struct update_phy_task;
0314     struct work_struct print_hang_task;
0315 
0316     int phy_hang_count;
0317 
0318     u16 tx_ring_count;
0319     u16 rx_ring_count;
0320 
0321     struct hwtstamp_config hwtstamp_config;
0322     struct delayed_work systim_overflow_work;
0323     struct sk_buff *tx_hwtstamp_skb;
0324     unsigned long tx_hwtstamp_start;
0325     struct work_struct tx_hwtstamp_work;
0326     spinlock_t systim_lock; /* protects SYSTIML/H regsters */
0327     struct cyclecounter cc;
0328     struct timecounter tc;
0329     struct ptp_clock *ptp_clock;
0330     struct ptp_clock_info ptp_clock_info;
0331     struct pm_qos_request pm_qos_req;
0332     long ptp_delta;
0333 
0334     u16 eee_advert;
0335 };
0336 
0337 struct e1000_info {
0338     enum e1000_mac_type mac;
0339     unsigned int        flags;
0340     unsigned int        flags2;
0341     u32         pba;
0342     u32         max_hw_frame_size;
0343     s32         (*get_variants)(struct e1000_adapter *);
0344     const struct e1000_mac_operations *mac_ops;
0345     const struct e1000_phy_operations *phy_ops;
0346     const struct e1000_nvm_operations *nvm_ops;
0347 };
0348 
0349 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
0350 
0351 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
0352  * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore
0353  * its resolution) is based on the contents of the TIMINCA register - it
0354  * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
0355  * For the best accuracy, the incperiod should be as small as possible.  The
0356  * incvalue is scaled by a factor as large as possible (while still fitting
0357  * in bits 23:0) so that relatively small clock corrections can be made.
0358  *
0359  * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
0360  * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
0361  * bits to count nanoseconds leaving the rest for fractional nonseconds.
0362  */
0363 #define INCVALUE_96MHZ      125
0364 #define INCVALUE_SHIFT_96MHZ    17
0365 #define INCPERIOD_SHIFT_96MHZ   2
0366 #define INCPERIOD_96MHZ     (12 >> INCPERIOD_SHIFT_96MHZ)
0367 
0368 #define INCVALUE_25MHZ      40
0369 #define INCVALUE_SHIFT_25MHZ    18
0370 #define INCPERIOD_25MHZ     1
0371 
0372 #define INCVALUE_24MHZ      125
0373 #define INCVALUE_SHIFT_24MHZ    14
0374 #define INCPERIOD_24MHZ     3
0375 
0376 #define INCVALUE_38400KHZ   26
0377 #define INCVALUE_SHIFT_38400KHZ 19
0378 #define INCPERIOD_38400KHZ  1
0379 
0380 /* Another drawback of scaling the incvalue by a large factor is the
0381  * 64-bit SYSTIM register overflows more quickly.  This is dealt with
0382  * by simply reading the clock before it overflows.
0383  *
0384  * Clock    ns bits Overflows after
0385  * ~~~~~~   ~~~~~~~ ~~~~~~~~~~~~~~~
0386  * 96MHz    47-bit  2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
0387  * 25MHz    46-bit  2^46 / 10^9 / 3600 = 19.55 hours
0388  */
0389 #define E1000_SYSTIM_OVERFLOW_PERIOD    (HZ * 60 * 60 * 4)
0390 #define E1000_MAX_82574_SYSTIM_REREADS  50
0391 #define E1000_82574_SYSTIM_EPSILON  (1ULL << 35ULL)
0392 
0393 /* hardware capability, feature, and workaround flags */
0394 #define FLAG_HAS_AMT                      BIT(0)
0395 #define FLAG_HAS_FLASH                    BIT(1)
0396 #define FLAG_HAS_HW_VLAN_FILTER           BIT(2)
0397 #define FLAG_HAS_WOL                      BIT(3)
0398 /* reserved BIT(4) */
0399 #define FLAG_HAS_CTRLEXT_ON_LOAD          BIT(5)
0400 #define FLAG_HAS_SWSM_ON_LOAD             BIT(6)
0401 #define FLAG_HAS_JUMBO_FRAMES             BIT(7)
0402 #define FLAG_READ_ONLY_NVM                BIT(8)
0403 #define FLAG_IS_ICH                       BIT(9)
0404 #define FLAG_HAS_MSIX                     BIT(10)
0405 #define FLAG_HAS_SMART_POWER_DOWN         BIT(11)
0406 #define FLAG_IS_QUAD_PORT_A               BIT(12)
0407 #define FLAG_IS_QUAD_PORT                 BIT(13)
0408 #define FLAG_HAS_HW_TIMESTAMP             BIT(14)
0409 #define FLAG_APME_IN_WUC                  BIT(15)
0410 #define FLAG_APME_IN_CTRL3                BIT(16)
0411 #define FLAG_APME_CHECK_PORT_B            BIT(17)
0412 #define FLAG_DISABLE_FC_PAUSE_TIME        BIT(18)
0413 #define FLAG_NO_WAKE_UCAST                BIT(19)
0414 #define FLAG_MNG_PT_ENABLED               BIT(20)
0415 #define FLAG_RESET_OVERWRITES_LAA         BIT(21)
0416 #define FLAG_TARC_SPEED_MODE_BIT          BIT(22)
0417 #define FLAG_TARC_SET_BIT_ZERO            BIT(23)
0418 #define FLAG_RX_NEEDS_RESTART             BIT(24)
0419 #define FLAG_LSC_GIG_SPEED_DROP           BIT(25)
0420 #define FLAG_SMART_POWER_DOWN             BIT(26)
0421 #define FLAG_MSI_ENABLED                  BIT(27)
0422 /* reserved BIT(28) */
0423 #define FLAG_TSO_FORCE                    BIT(29)
0424 #define FLAG_RESTART_NOW                  BIT(30)
0425 #define FLAG_MSI_TEST_FAILED              BIT(31)
0426 
0427 #define FLAG2_CRC_STRIPPING               BIT(0)
0428 #define FLAG2_HAS_PHY_WAKEUP              BIT(1)
0429 #define FLAG2_IS_DISCARDING               BIT(2)
0430 #define FLAG2_DISABLE_ASPM_L1             BIT(3)
0431 #define FLAG2_HAS_PHY_STATS               BIT(4)
0432 #define FLAG2_HAS_EEE                     BIT(5)
0433 #define FLAG2_DMA_BURST                   BIT(6)
0434 #define FLAG2_DISABLE_ASPM_L0S            BIT(7)
0435 #define FLAG2_DISABLE_AIM                 BIT(8)
0436 #define FLAG2_CHECK_PHY_HANG              BIT(9)
0437 #define FLAG2_NO_DISABLE_RX               BIT(10)
0438 #define FLAG2_PCIM2PCI_ARBITER_WA         BIT(11)
0439 #define FLAG2_DFLT_CRC_STRIPPING          BIT(12)
0440 #define FLAG2_CHECK_RX_HWTSTAMP           BIT(13)
0441 #define FLAG2_CHECK_SYSTIM_OVERFLOW       BIT(14)
0442 #define FLAG2_ENABLE_S0IX_FLOWS           BIT(15)
0443 
0444 #define E1000_RX_DESC_PS(R, i)      \
0445     (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
0446 #define E1000_RX_DESC_EXT(R, i)     \
0447     (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
0448 #define E1000_GET_DESC(R, i, type)  (&(((struct type *)((R).desc))[i]))
0449 #define E1000_TX_DESC(R, i)     E1000_GET_DESC(R, i, e1000_tx_desc)
0450 #define E1000_CONTEXT_DESC(R, i)    E1000_GET_DESC(R, i, e1000_context_desc)
0451 
0452 enum e1000_state_t {
0453     __E1000_TESTING,
0454     __E1000_RESETTING,
0455     __E1000_ACCESS_SHARED_RESOURCE,
0456     __E1000_DOWN
0457 };
0458 
0459 enum latency_range {
0460     lowest_latency = 0,
0461     low_latency = 1,
0462     bulk_latency = 2,
0463     latency_invalid = 255
0464 };
0465 
0466 extern char e1000e_driver_name[];
0467 
0468 void e1000e_check_options(struct e1000_adapter *adapter);
0469 void e1000e_set_ethtool_ops(struct net_device *netdev);
0470 
0471 int e1000e_open(struct net_device *netdev);
0472 int e1000e_close(struct net_device *netdev);
0473 void e1000e_up(struct e1000_adapter *adapter);
0474 void e1000e_down(struct e1000_adapter *adapter, bool reset);
0475 void e1000e_reinit_locked(struct e1000_adapter *adapter);
0476 void e1000e_reset(struct e1000_adapter *adapter);
0477 void e1000e_power_up_phy(struct e1000_adapter *adapter);
0478 int e1000e_setup_rx_resources(struct e1000_ring *ring);
0479 int e1000e_setup_tx_resources(struct e1000_ring *ring);
0480 void e1000e_free_rx_resources(struct e1000_ring *ring);
0481 void e1000e_free_tx_resources(struct e1000_ring *ring);
0482 void e1000e_get_stats64(struct net_device *netdev,
0483             struct rtnl_link_stats64 *stats);
0484 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
0485 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
0486 void e1000e_get_hw_control(struct e1000_adapter *adapter);
0487 void e1000e_release_hw_control(struct e1000_adapter *adapter);
0488 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
0489 
0490 extern unsigned int copybreak;
0491 
0492 extern const struct e1000_info e1000_82571_info;
0493 extern const struct e1000_info e1000_82572_info;
0494 extern const struct e1000_info e1000_82573_info;
0495 extern const struct e1000_info e1000_82574_info;
0496 extern const struct e1000_info e1000_82583_info;
0497 extern const struct e1000_info e1000_ich8_info;
0498 extern const struct e1000_info e1000_ich9_info;
0499 extern const struct e1000_info e1000_ich10_info;
0500 extern const struct e1000_info e1000_pch_info;
0501 extern const struct e1000_info e1000_pch2_info;
0502 extern const struct e1000_info e1000_pch_lpt_info;
0503 extern const struct e1000_info e1000_pch_spt_info;
0504 extern const struct e1000_info e1000_pch_cnp_info;
0505 extern const struct e1000_info e1000_pch_tgp_info;
0506 extern const struct e1000_info e1000_pch_adp_info;
0507 extern const struct e1000_info e1000_es2_info;
0508 
0509 void e1000e_ptp_init(struct e1000_adapter *adapter);
0510 void e1000e_ptp_remove(struct e1000_adapter *adapter);
0511 
0512 u64 e1000e_read_systim(struct e1000_adapter *adapter,
0513                struct ptp_system_timestamp *sts);
0514 
0515 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
0516 {
0517     return hw->phy.ops.reset(hw);
0518 }
0519 
0520 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
0521 {
0522     return hw->phy.ops.read_reg(hw, offset, data);
0523 }
0524 
0525 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
0526 {
0527     return hw->phy.ops.read_reg_locked(hw, offset, data);
0528 }
0529 
0530 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
0531 {
0532     return hw->phy.ops.write_reg(hw, offset, data);
0533 }
0534 
0535 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
0536 {
0537     return hw->phy.ops.write_reg_locked(hw, offset, data);
0538 }
0539 
0540 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
0541 
0542 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
0543 {
0544     if (hw->mac.ops.read_mac_addr)
0545         return hw->mac.ops.read_mac_addr(hw);
0546 
0547     return e1000_read_mac_addr_generic(hw);
0548 }
0549 
0550 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
0551 {
0552     return hw->nvm.ops.validate(hw);
0553 }
0554 
0555 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
0556 {
0557     return hw->nvm.ops.update(hw);
0558 }
0559 
0560 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
0561                  u16 *data)
0562 {
0563     return hw->nvm.ops.read(hw, offset, words, data);
0564 }
0565 
0566 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
0567                   u16 *data)
0568 {
0569     return hw->nvm.ops.write(hw, offset, words, data);
0570 }
0571 
0572 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
0573 {
0574     return hw->phy.ops.get_info(hw);
0575 }
0576 
0577 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
0578 {
0579     return readl(hw->hw_addr + reg);
0580 }
0581 
0582 #define er32(reg)   __er32(hw, E1000_##reg)
0583 
0584 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
0585 
0586 #define ew32(reg, val)  __ew32(hw, E1000_##reg, (val))
0587 
0588 #define e1e_flush() er32(STATUS)
0589 
0590 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
0591     (__ew32((a), (reg + ((offset) << 2)), (value)))
0592 
0593 #define E1000_READ_REG_ARRAY(a, reg, offset) \
0594     (readl((a)->hw_addr + reg + ((offset) << 2)))
0595 
0596 #endif /* _E1000_H_ */
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