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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003 
0004 /* 82571EB Gigabit Ethernet Controller
0005  * 82571EB Gigabit Ethernet Controller (Copper)
0006  * 82571EB Gigabit Ethernet Controller (Fiber)
0007  * 82571EB Dual Port Gigabit Mezzanine Adapter
0008  * 82571EB Quad Port Gigabit Mezzanine Adapter
0009  * 82571PT Gigabit PT Quad Port Server ExpressModule
0010  * 82572EI Gigabit Ethernet Controller (Copper)
0011  * 82572EI Gigabit Ethernet Controller (Fiber)
0012  * 82572EI Gigabit Ethernet Controller
0013  * 82573V Gigabit Ethernet Controller (Copper)
0014  * 82573E Gigabit Ethernet Controller (Copper)
0015  * 82573L Gigabit Ethernet Controller
0016  * 82574L Gigabit Network Connection
0017  * 82583V Gigabit Network Connection
0018  */
0019 
0020 #include "e1000.h"
0021 
0022 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
0023 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
0024 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
0025 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
0026 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
0027                       u16 words, u16 *data);
0028 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
0029 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
0030 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
0031 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
0032 static s32 e1000_led_on_82574(struct e1000_hw *hw);
0033 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
0034 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
0035 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
0036 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
0037 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
0038 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
0039 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
0040 
0041 /**
0042  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
0043  *  @hw: pointer to the HW structure
0044  **/
0045 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
0046 {
0047     struct e1000_phy_info *phy = &hw->phy;
0048     s32 ret_val;
0049 
0050     if (hw->phy.media_type != e1000_media_type_copper) {
0051         phy->type = e1000_phy_none;
0052         return 0;
0053     }
0054 
0055     phy->addr = 1;
0056     phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
0057     phy->reset_delay_us = 100;
0058 
0059     phy->ops.power_up = e1000_power_up_phy_copper;
0060     phy->ops.power_down = e1000_power_down_phy_copper_82571;
0061 
0062     switch (hw->mac.type) {
0063     case e1000_82571:
0064     case e1000_82572:
0065         phy->type = e1000_phy_igp_2;
0066         break;
0067     case e1000_82573:
0068         phy->type = e1000_phy_m88;
0069         break;
0070     case e1000_82574:
0071     case e1000_82583:
0072         phy->type = e1000_phy_bm;
0073         phy->ops.acquire = e1000_get_hw_semaphore_82574;
0074         phy->ops.release = e1000_put_hw_semaphore_82574;
0075         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
0076         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
0077         break;
0078     default:
0079         return -E1000_ERR_PHY;
0080     }
0081 
0082     /* This can only be done after all function pointers are setup. */
0083     ret_val = e1000_get_phy_id_82571(hw);
0084     if (ret_val) {
0085         e_dbg("Error getting PHY ID\n");
0086         return ret_val;
0087     }
0088 
0089     /* Verify phy id */
0090     switch (hw->mac.type) {
0091     case e1000_82571:
0092     case e1000_82572:
0093         if (phy->id != IGP01E1000_I_PHY_ID)
0094             ret_val = -E1000_ERR_PHY;
0095         break;
0096     case e1000_82573:
0097         if (phy->id != M88E1111_I_PHY_ID)
0098             ret_val = -E1000_ERR_PHY;
0099         break;
0100     case e1000_82574:
0101     case e1000_82583:
0102         if (phy->id != BME1000_E_PHY_ID_R2)
0103             ret_val = -E1000_ERR_PHY;
0104         break;
0105     default:
0106         ret_val = -E1000_ERR_PHY;
0107         break;
0108     }
0109 
0110     if (ret_val)
0111         e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
0112 
0113     return ret_val;
0114 }
0115 
0116 /**
0117  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
0118  *  @hw: pointer to the HW structure
0119  **/
0120 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
0121 {
0122     struct e1000_nvm_info *nvm = &hw->nvm;
0123     u32 eecd = er32(EECD);
0124     u16 size;
0125 
0126     nvm->opcode_bits = 8;
0127     nvm->delay_usec = 1;
0128     switch (nvm->override) {
0129     case e1000_nvm_override_spi_large:
0130         nvm->page_size = 32;
0131         nvm->address_bits = 16;
0132         break;
0133     case e1000_nvm_override_spi_small:
0134         nvm->page_size = 8;
0135         nvm->address_bits = 8;
0136         break;
0137     default:
0138         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
0139         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
0140         break;
0141     }
0142 
0143     switch (hw->mac.type) {
0144     case e1000_82573:
0145     case e1000_82574:
0146     case e1000_82583:
0147         if (((eecd >> 15) & 0x3) == 0x3) {
0148             nvm->type = e1000_nvm_flash_hw;
0149             nvm->word_size = 2048;
0150             /* Autonomous Flash update bit must be cleared due
0151              * to Flash update issue.
0152              */
0153             eecd &= ~E1000_EECD_AUPDEN;
0154             ew32(EECD, eecd);
0155             break;
0156         }
0157         fallthrough;
0158     default:
0159         nvm->type = e1000_nvm_eeprom_spi;
0160         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
0161                  E1000_EECD_SIZE_EX_SHIFT);
0162         /* Added to a constant, "size" becomes the left-shift value
0163          * for setting word_size.
0164          */
0165         size += NVM_WORD_SIZE_BASE_SHIFT;
0166 
0167         /* EEPROM access above 16k is unsupported */
0168         if (size > 14)
0169             size = 14;
0170         nvm->word_size = BIT(size);
0171         break;
0172     }
0173 
0174     /* Function Pointers */
0175     switch (hw->mac.type) {
0176     case e1000_82574:
0177     case e1000_82583:
0178         nvm->ops.acquire = e1000_get_hw_semaphore_82574;
0179         nvm->ops.release = e1000_put_hw_semaphore_82574;
0180         break;
0181     default:
0182         break;
0183     }
0184 
0185     return 0;
0186 }
0187 
0188 /**
0189  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
0190  *  @hw: pointer to the HW structure
0191  **/
0192 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
0193 {
0194     struct e1000_mac_info *mac = &hw->mac;
0195     u32 swsm = 0;
0196     u32 swsm2 = 0;
0197     bool force_clear_smbi = false;
0198 
0199     /* Set media type and media-dependent function pointers */
0200     switch (hw->adapter->pdev->device) {
0201     case E1000_DEV_ID_82571EB_FIBER:
0202     case E1000_DEV_ID_82572EI_FIBER:
0203     case E1000_DEV_ID_82571EB_QUAD_FIBER:
0204         hw->phy.media_type = e1000_media_type_fiber;
0205         mac->ops.setup_physical_interface =
0206             e1000_setup_fiber_serdes_link_82571;
0207         mac->ops.check_for_link = e1000e_check_for_fiber_link;
0208         mac->ops.get_link_up_info =
0209             e1000e_get_speed_and_duplex_fiber_serdes;
0210         break;
0211     case E1000_DEV_ID_82571EB_SERDES:
0212     case E1000_DEV_ID_82571EB_SERDES_DUAL:
0213     case E1000_DEV_ID_82571EB_SERDES_QUAD:
0214     case E1000_DEV_ID_82572EI_SERDES:
0215         hw->phy.media_type = e1000_media_type_internal_serdes;
0216         mac->ops.setup_physical_interface =
0217             e1000_setup_fiber_serdes_link_82571;
0218         mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
0219         mac->ops.get_link_up_info =
0220             e1000e_get_speed_and_duplex_fiber_serdes;
0221         break;
0222     default:
0223         hw->phy.media_type = e1000_media_type_copper;
0224         mac->ops.setup_physical_interface =
0225             e1000_setup_copper_link_82571;
0226         mac->ops.check_for_link = e1000e_check_for_copper_link;
0227         mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
0228         break;
0229     }
0230 
0231     /* Set mta register count */
0232     mac->mta_reg_count = 128;
0233     /* Set rar entry count */
0234     mac->rar_entry_count = E1000_RAR_ENTRIES;
0235     /* Adaptive IFS supported */
0236     mac->adaptive_ifs = true;
0237 
0238     /* MAC-specific function pointers */
0239     switch (hw->mac.type) {
0240     case e1000_82573:
0241         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
0242         mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
0243         mac->ops.led_on = e1000e_led_on_generic;
0244         mac->ops.blink_led = e1000e_blink_led_generic;
0245 
0246         /* FWSM register */
0247         mac->has_fwsm = true;
0248         /* ARC supported; valid only if manageability features are
0249          * enabled.
0250          */
0251         mac->arc_subsystem_valid = !!(er32(FWSM) &
0252                           E1000_FWSM_MODE_MASK);
0253         break;
0254     case e1000_82574:
0255     case e1000_82583:
0256         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
0257         mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
0258         mac->ops.led_on = e1000_led_on_82574;
0259         break;
0260     default:
0261         mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
0262         mac->ops.led_on = e1000e_led_on_generic;
0263         mac->ops.blink_led = e1000e_blink_led_generic;
0264 
0265         /* FWSM register */
0266         mac->has_fwsm = true;
0267         break;
0268     }
0269 
0270     /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
0271      * first NVM or PHY access. This should be done for single-port
0272      * devices, and for one port only on dual-port devices so that
0273      * for those devices we can still use the SMBI lock to synchronize
0274      * inter-port accesses to the PHY & NVM.
0275      */
0276     switch (hw->mac.type) {
0277     case e1000_82571:
0278     case e1000_82572:
0279         swsm2 = er32(SWSM2);
0280 
0281         if (!(swsm2 & E1000_SWSM2_LOCK)) {
0282             /* Only do this for the first interface on this card */
0283             ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
0284             force_clear_smbi = true;
0285         } else {
0286             force_clear_smbi = false;
0287         }
0288         break;
0289     default:
0290         force_clear_smbi = true;
0291         break;
0292     }
0293 
0294     if (force_clear_smbi) {
0295         /* Make sure SWSM.SMBI is clear */
0296         swsm = er32(SWSM);
0297         if (swsm & E1000_SWSM_SMBI) {
0298             /* This bit should not be set on a first interface, and
0299              * indicates that the bootagent or EFI code has
0300              * improperly left this bit enabled
0301              */
0302             e_dbg("Please update your 82571 Bootagent\n");
0303         }
0304         ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
0305     }
0306 
0307     /* Initialize device specific counter of SMBI acquisition timeouts. */
0308     hw->dev_spec.e82571.smb_counter = 0;
0309 
0310     return 0;
0311 }
0312 
0313 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
0314 {
0315     struct e1000_hw *hw = &adapter->hw;
0316     static int global_quad_port_a;  /* global port a indication */
0317     struct pci_dev *pdev = adapter->pdev;
0318     int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
0319     s32 rc;
0320 
0321     rc = e1000_init_mac_params_82571(hw);
0322     if (rc)
0323         return rc;
0324 
0325     rc = e1000_init_nvm_params_82571(hw);
0326     if (rc)
0327         return rc;
0328 
0329     rc = e1000_init_phy_params_82571(hw);
0330     if (rc)
0331         return rc;
0332 
0333     /* tag quad port adapters first, it's used below */
0334     switch (pdev->device) {
0335     case E1000_DEV_ID_82571EB_QUAD_COPPER:
0336     case E1000_DEV_ID_82571EB_QUAD_FIBER:
0337     case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
0338     case E1000_DEV_ID_82571PT_QUAD_COPPER:
0339         adapter->flags |= FLAG_IS_QUAD_PORT;
0340         /* mark the first port */
0341         if (global_quad_port_a == 0)
0342             adapter->flags |= FLAG_IS_QUAD_PORT_A;
0343         /* Reset for multiple quad port adapters */
0344         global_quad_port_a++;
0345         if (global_quad_port_a == 4)
0346             global_quad_port_a = 0;
0347         break;
0348     default:
0349         break;
0350     }
0351 
0352     switch (adapter->hw.mac.type) {
0353     case e1000_82571:
0354         /* these dual ports don't have WoL on port B at all */
0355         if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
0356              (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
0357              (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
0358             (is_port_b))
0359             adapter->flags &= ~FLAG_HAS_WOL;
0360         /* quad ports only support WoL on port A */
0361         if (adapter->flags & FLAG_IS_QUAD_PORT &&
0362             (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
0363             adapter->flags &= ~FLAG_HAS_WOL;
0364         /* Does not support WoL on any port */
0365         if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
0366             adapter->flags &= ~FLAG_HAS_WOL;
0367         break;
0368     case e1000_82573:
0369         if (pdev->device == E1000_DEV_ID_82573L) {
0370             adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
0371             adapter->max_hw_frame_size = DEFAULT_JUMBO;
0372         }
0373         break;
0374     default:
0375         break;
0376     }
0377 
0378     return 0;
0379 }
0380 
0381 /**
0382  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
0383  *  @hw: pointer to the HW structure
0384  *
0385  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
0386  *  revision in the hardware structure.
0387  **/
0388 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
0389 {
0390     struct e1000_phy_info *phy = &hw->phy;
0391     s32 ret_val;
0392     u16 phy_id = 0;
0393 
0394     switch (hw->mac.type) {
0395     case e1000_82571:
0396     case e1000_82572:
0397         /* The 82571 firmware may still be configuring the PHY.
0398          * In this case, we cannot access the PHY until the
0399          * configuration is done.  So we explicitly set the
0400          * PHY ID.
0401          */
0402         phy->id = IGP01E1000_I_PHY_ID;
0403         break;
0404     case e1000_82573:
0405         return e1000e_get_phy_id(hw);
0406     case e1000_82574:
0407     case e1000_82583:
0408         ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
0409         if (ret_val)
0410             return ret_val;
0411 
0412         phy->id = (u32)(phy_id << 16);
0413         usleep_range(20, 40);
0414         ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
0415         if (ret_val)
0416             return ret_val;
0417 
0418         phy->id |= (u32)(phy_id);
0419         phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
0420         break;
0421     default:
0422         return -E1000_ERR_PHY;
0423     }
0424 
0425     return 0;
0426 }
0427 
0428 /**
0429  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
0430  *  @hw: pointer to the HW structure
0431  *
0432  *  Acquire the HW semaphore to access the PHY or NVM
0433  **/
0434 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
0435 {
0436     u32 swsm;
0437     s32 sw_timeout = hw->nvm.word_size + 1;
0438     s32 fw_timeout = hw->nvm.word_size + 1;
0439     s32 i = 0;
0440 
0441     /* If we have timedout 3 times on trying to acquire
0442      * the inter-port SMBI semaphore, there is old code
0443      * operating on the other port, and it is not
0444      * releasing SMBI. Modify the number of times that
0445      * we try for the semaphore to interwork with this
0446      * older code.
0447      */
0448     if (hw->dev_spec.e82571.smb_counter > 2)
0449         sw_timeout = 1;
0450 
0451     /* Get the SW semaphore */
0452     while (i < sw_timeout) {
0453         swsm = er32(SWSM);
0454         if (!(swsm & E1000_SWSM_SMBI))
0455             break;
0456 
0457         usleep_range(50, 100);
0458         i++;
0459     }
0460 
0461     if (i == sw_timeout) {
0462         e_dbg("Driver can't access device - SMBI bit is set.\n");
0463         hw->dev_spec.e82571.smb_counter++;
0464     }
0465     /* Get the FW semaphore. */
0466     for (i = 0; i < fw_timeout; i++) {
0467         swsm = er32(SWSM);
0468         ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
0469 
0470         /* Semaphore acquired if bit latched */
0471         if (er32(SWSM) & E1000_SWSM_SWESMBI)
0472             break;
0473 
0474         usleep_range(50, 100);
0475     }
0476 
0477     if (i == fw_timeout) {
0478         /* Release semaphores */
0479         e1000_put_hw_semaphore_82571(hw);
0480         e_dbg("Driver can't access the NVM\n");
0481         return -E1000_ERR_NVM;
0482     }
0483 
0484     return 0;
0485 }
0486 
0487 /**
0488  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
0489  *  @hw: pointer to the HW structure
0490  *
0491  *  Release hardware semaphore used to access the PHY or NVM
0492  **/
0493 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
0494 {
0495     u32 swsm;
0496 
0497     swsm = er32(SWSM);
0498     swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
0499     ew32(SWSM, swsm);
0500 }
0501 
0502 /**
0503  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
0504  *  @hw: pointer to the HW structure
0505  *
0506  *  Acquire the HW semaphore during reset.
0507  *
0508  **/
0509 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
0510 {
0511     u32 extcnf_ctrl;
0512     s32 i = 0;
0513 
0514     extcnf_ctrl = er32(EXTCNF_CTRL);
0515     do {
0516         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
0517         ew32(EXTCNF_CTRL, extcnf_ctrl);
0518         extcnf_ctrl = er32(EXTCNF_CTRL);
0519 
0520         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
0521             break;
0522 
0523         usleep_range(2000, 4000);
0524         i++;
0525     } while (i < MDIO_OWNERSHIP_TIMEOUT);
0526 
0527     if (i == MDIO_OWNERSHIP_TIMEOUT) {
0528         /* Release semaphores */
0529         e1000_put_hw_semaphore_82573(hw);
0530         e_dbg("Driver can't access the PHY\n");
0531         return -E1000_ERR_PHY;
0532     }
0533 
0534     return 0;
0535 }
0536 
0537 /**
0538  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
0539  *  @hw: pointer to the HW structure
0540  *
0541  *  Release hardware semaphore used during reset.
0542  *
0543  **/
0544 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
0545 {
0546     u32 extcnf_ctrl;
0547 
0548     extcnf_ctrl = er32(EXTCNF_CTRL);
0549     extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
0550     ew32(EXTCNF_CTRL, extcnf_ctrl);
0551 }
0552 
0553 static DEFINE_MUTEX(swflag_mutex);
0554 
0555 /**
0556  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
0557  *  @hw: pointer to the HW structure
0558  *
0559  *  Acquire the HW semaphore to access the PHY or NVM.
0560  *
0561  **/
0562 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
0563 {
0564     s32 ret_val;
0565 
0566     mutex_lock(&swflag_mutex);
0567     ret_val = e1000_get_hw_semaphore_82573(hw);
0568     if (ret_val)
0569         mutex_unlock(&swflag_mutex);
0570     return ret_val;
0571 }
0572 
0573 /**
0574  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
0575  *  @hw: pointer to the HW structure
0576  *
0577  *  Release hardware semaphore used to access the PHY or NVM
0578  *
0579  **/
0580 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
0581 {
0582     e1000_put_hw_semaphore_82573(hw);
0583     mutex_unlock(&swflag_mutex);
0584 }
0585 
0586 /**
0587  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
0588  *  @hw: pointer to the HW structure
0589  *  @active: true to enable LPLU, false to disable
0590  *
0591  *  Sets the LPLU D0 state according to the active flag.
0592  *  LPLU will not be activated unless the
0593  *  device autonegotiation advertisement meets standards of
0594  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
0595  *  This is a function pointer entry point only called by
0596  *  PHY setup routines.
0597  **/
0598 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
0599 {
0600     u32 data = er32(POEMB);
0601 
0602     if (active)
0603         data |= E1000_PHY_CTRL_D0A_LPLU;
0604     else
0605         data &= ~E1000_PHY_CTRL_D0A_LPLU;
0606 
0607     ew32(POEMB, data);
0608     return 0;
0609 }
0610 
0611 /**
0612  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
0613  *  @hw: pointer to the HW structure
0614  *  @active: boolean used to enable/disable lplu
0615  *
0616  *  The low power link up (lplu) state is set to the power management level D3
0617  *  when active is true, else clear lplu for D3. LPLU
0618  *  is used during Dx states where the power conservation is most important.
0619  *  During driver activity, SmartSpeed should be enabled so performance is
0620  *  maintained.
0621  **/
0622 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
0623 {
0624     u32 data = er32(POEMB);
0625 
0626     if (!active) {
0627         data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
0628     } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
0629            (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
0630            (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
0631         data |= E1000_PHY_CTRL_NOND0A_LPLU;
0632     }
0633 
0634     ew32(POEMB, data);
0635     return 0;
0636 }
0637 
0638 /**
0639  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
0640  *  @hw: pointer to the HW structure
0641  *
0642  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
0643  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
0644  *  for EEPROM access grant bit.  If the access grant bit is not set, release
0645  *  hardware semaphore.
0646  **/
0647 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
0648 {
0649     s32 ret_val;
0650 
0651     ret_val = e1000_get_hw_semaphore_82571(hw);
0652     if (ret_val)
0653         return ret_val;
0654 
0655     switch (hw->mac.type) {
0656     case e1000_82573:
0657         break;
0658     default:
0659         ret_val = e1000e_acquire_nvm(hw);
0660         break;
0661     }
0662 
0663     if (ret_val)
0664         e1000_put_hw_semaphore_82571(hw);
0665 
0666     return ret_val;
0667 }
0668 
0669 /**
0670  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
0671  *  @hw: pointer to the HW structure
0672  *
0673  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
0674  **/
0675 static void e1000_release_nvm_82571(struct e1000_hw *hw)
0676 {
0677     e1000e_release_nvm(hw);
0678     e1000_put_hw_semaphore_82571(hw);
0679 }
0680 
0681 /**
0682  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
0683  *  @hw: pointer to the HW structure
0684  *  @offset: offset within the EEPROM to be written to
0685  *  @words: number of words to write
0686  *  @data: 16 bit word(s) to be written to the EEPROM
0687  *
0688  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
0689  *
0690  *  If e1000e_update_nvm_checksum is not called after this function, the
0691  *  EEPROM will most likely contain an invalid checksum.
0692  **/
0693 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
0694                  u16 *data)
0695 {
0696     s32 ret_val;
0697 
0698     switch (hw->mac.type) {
0699     case e1000_82573:
0700     case e1000_82574:
0701     case e1000_82583:
0702         ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
0703         break;
0704     case e1000_82571:
0705     case e1000_82572:
0706         ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
0707         break;
0708     default:
0709         ret_val = -E1000_ERR_NVM;
0710         break;
0711     }
0712 
0713     return ret_val;
0714 }
0715 
0716 /**
0717  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
0718  *  @hw: pointer to the HW structure
0719  *
0720  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
0721  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
0722  *  value to the EEPROM.
0723  **/
0724 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
0725 {
0726     u32 eecd;
0727     s32 ret_val;
0728     u16 i;
0729 
0730     ret_val = e1000e_update_nvm_checksum_generic(hw);
0731     if (ret_val)
0732         return ret_val;
0733 
0734     /* If our nvm is an EEPROM, then we're done
0735      * otherwise, commit the checksum to the flash NVM.
0736      */
0737     if (hw->nvm.type != e1000_nvm_flash_hw)
0738         return 0;
0739 
0740     /* Check for pending operations. */
0741     for (i = 0; i < E1000_FLASH_UPDATES; i++) {
0742         usleep_range(1000, 2000);
0743         if (!(er32(EECD) & E1000_EECD_FLUPD))
0744             break;
0745     }
0746 
0747     if (i == E1000_FLASH_UPDATES)
0748         return -E1000_ERR_NVM;
0749 
0750     /* Reset the firmware if using STM opcode. */
0751     if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
0752         /* The enabling of and the actual reset must be done
0753          * in two write cycles.
0754          */
0755         ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
0756         e1e_flush();
0757         ew32(HICR, E1000_HICR_FW_RESET);
0758     }
0759 
0760     /* Commit the write to flash */
0761     eecd = er32(EECD) | E1000_EECD_FLUPD;
0762     ew32(EECD, eecd);
0763 
0764     for (i = 0; i < E1000_FLASH_UPDATES; i++) {
0765         usleep_range(1000, 2000);
0766         if (!(er32(EECD) & E1000_EECD_FLUPD))
0767             break;
0768     }
0769 
0770     if (i == E1000_FLASH_UPDATES)
0771         return -E1000_ERR_NVM;
0772 
0773     return 0;
0774 }
0775 
0776 /**
0777  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
0778  *  @hw: pointer to the HW structure
0779  *
0780  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
0781  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
0782  **/
0783 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
0784 {
0785     if (hw->nvm.type == e1000_nvm_flash_hw)
0786         e1000_fix_nvm_checksum_82571(hw);
0787 
0788     return e1000e_validate_nvm_checksum_generic(hw);
0789 }
0790 
0791 /**
0792  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
0793  *  @hw: pointer to the HW structure
0794  *  @offset: offset within the EEPROM to be written to
0795  *  @words: number of words to write
0796  *  @data: 16 bit word(s) to be written to the EEPROM
0797  *
0798  *  After checking for invalid values, poll the EEPROM to ensure the previous
0799  *  command has completed before trying to write the next word.  After write
0800  *  poll for completion.
0801  *
0802  *  If e1000e_update_nvm_checksum is not called after this function, the
0803  *  EEPROM will most likely contain an invalid checksum.
0804  **/
0805 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
0806                       u16 words, u16 *data)
0807 {
0808     struct e1000_nvm_info *nvm = &hw->nvm;
0809     u32 i, eewr = 0;
0810     s32 ret_val = 0;
0811 
0812     /* A check for invalid values:  offset too large, too many words,
0813      * and not enough words.
0814      */
0815     if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
0816         (words == 0)) {
0817         e_dbg("nvm parameter(s) out of bounds\n");
0818         return -E1000_ERR_NVM;
0819     }
0820 
0821     for (i = 0; i < words; i++) {
0822         eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
0823             ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
0824             E1000_NVM_RW_REG_START);
0825 
0826         ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
0827         if (ret_val)
0828             break;
0829 
0830         ew32(EEWR, eewr);
0831 
0832         ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
0833         if (ret_val)
0834             break;
0835     }
0836 
0837     return ret_val;
0838 }
0839 
0840 /**
0841  *  e1000_get_cfg_done_82571 - Poll for configuration done
0842  *  @hw: pointer to the HW structure
0843  *
0844  *  Reads the management control register for the config done bit to be set.
0845  **/
0846 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
0847 {
0848     s32 timeout = PHY_CFG_TIMEOUT;
0849 
0850     while (timeout) {
0851         if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
0852             break;
0853         usleep_range(1000, 2000);
0854         timeout--;
0855     }
0856     if (!timeout) {
0857         e_dbg("MNG configuration cycle has not completed.\n");
0858         return -E1000_ERR_RESET;
0859     }
0860 
0861     return 0;
0862 }
0863 
0864 /**
0865  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
0866  *  @hw: pointer to the HW structure
0867  *  @active: true to enable LPLU, false to disable
0868  *
0869  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
0870  *  this function also disables smart speed and vice versa.  LPLU will not be
0871  *  activated unless the device autonegotiation advertisement meets standards
0872  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
0873  *  pointer entry point only called by PHY setup routines.
0874  **/
0875 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
0876 {
0877     struct e1000_phy_info *phy = &hw->phy;
0878     s32 ret_val;
0879     u16 data;
0880 
0881     ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
0882     if (ret_val)
0883         return ret_val;
0884 
0885     if (active) {
0886         data |= IGP02E1000_PM_D0_LPLU;
0887         ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
0888         if (ret_val)
0889             return ret_val;
0890 
0891         /* When LPLU is enabled, we should disable SmartSpeed */
0892         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
0893         if (ret_val)
0894             return ret_val;
0895         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
0896         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
0897         if (ret_val)
0898             return ret_val;
0899     } else {
0900         data &= ~IGP02E1000_PM_D0_LPLU;
0901         ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
0902         if (ret_val)
0903             return ret_val;
0904         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
0905          * during Dx states where the power conservation is most
0906          * important.  During driver activity we should enable
0907          * SmartSpeed, so performance is maintained.
0908          */
0909         if (phy->smart_speed == e1000_smart_speed_on) {
0910             ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
0911                        &data);
0912             if (ret_val)
0913                 return ret_val;
0914 
0915             data |= IGP01E1000_PSCFR_SMART_SPEED;
0916             ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
0917                        data);
0918             if (ret_val)
0919                 return ret_val;
0920         } else if (phy->smart_speed == e1000_smart_speed_off) {
0921             ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
0922                        &data);
0923             if (ret_val)
0924                 return ret_val;
0925 
0926             data &= ~IGP01E1000_PSCFR_SMART_SPEED;
0927             ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
0928                        data);
0929             if (ret_val)
0930                 return ret_val;
0931         }
0932     }
0933 
0934     return 0;
0935 }
0936 
0937 /**
0938  *  e1000_reset_hw_82571 - Reset hardware
0939  *  @hw: pointer to the HW structure
0940  *
0941  *  This resets the hardware into a known state.
0942  **/
0943 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
0944 {
0945     u32 ctrl, ctrl_ext, eecd, tctl;
0946     s32 ret_val;
0947 
0948     /* Prevent the PCI-E bus from sticking if there is no TLP connection
0949      * on the last TLP read/write transaction when MAC is reset.
0950      */
0951     ret_val = e1000e_disable_pcie_master(hw);
0952     if (ret_val)
0953         e_dbg("PCI-E Master disable polling has failed.\n");
0954 
0955     e_dbg("Masking off all interrupts\n");
0956     ew32(IMC, 0xffffffff);
0957 
0958     ew32(RCTL, 0);
0959     tctl = er32(TCTL);
0960     tctl &= ~E1000_TCTL_EN;
0961     ew32(TCTL, tctl);
0962     e1e_flush();
0963 
0964     usleep_range(10000, 11000);
0965 
0966     /* Must acquire the MDIO ownership before MAC reset.
0967      * Ownership defaults to firmware after a reset.
0968      */
0969     switch (hw->mac.type) {
0970     case e1000_82573:
0971         ret_val = e1000_get_hw_semaphore_82573(hw);
0972         break;
0973     case e1000_82574:
0974     case e1000_82583:
0975         ret_val = e1000_get_hw_semaphore_82574(hw);
0976         break;
0977     default:
0978         break;
0979     }
0980 
0981     ctrl = er32(CTRL);
0982 
0983     e_dbg("Issuing a global reset to MAC\n");
0984     ew32(CTRL, ctrl | E1000_CTRL_RST);
0985 
0986     /* Must release MDIO ownership and mutex after MAC reset. */
0987     switch (hw->mac.type) {
0988     case e1000_82573:
0989         /* Release mutex only if the hw semaphore is acquired */
0990         if (!ret_val)
0991             e1000_put_hw_semaphore_82573(hw);
0992         break;
0993     case e1000_82574:
0994     case e1000_82583:
0995         /* Release mutex only if the hw semaphore is acquired */
0996         if (!ret_val)
0997             e1000_put_hw_semaphore_82574(hw);
0998         break;
0999     default:
1000         break;
1001     }
1002 
1003     if (hw->nvm.type == e1000_nvm_flash_hw) {
1004         usleep_range(10, 20);
1005         ctrl_ext = er32(CTRL_EXT);
1006         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1007         ew32(CTRL_EXT, ctrl_ext);
1008         e1e_flush();
1009     }
1010 
1011     ret_val = e1000e_get_auto_rd_done(hw);
1012     if (ret_val)
1013         /* We don't want to continue accessing MAC registers. */
1014         return ret_val;
1015 
1016     /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1017      * Need to wait for Phy configuration completion before accessing
1018      * NVM and Phy.
1019      */
1020 
1021     switch (hw->mac.type) {
1022     case e1000_82571:
1023     case e1000_82572:
1024         /* REQ and GNT bits need to be cleared when using AUTO_RD
1025          * to access the EEPROM.
1026          */
1027         eecd = er32(EECD);
1028         eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1029         ew32(EECD, eecd);
1030         break;
1031     case e1000_82573:
1032     case e1000_82574:
1033     case e1000_82583:
1034         msleep(25);
1035         break;
1036     default:
1037         break;
1038     }
1039 
1040     /* Clear any pending interrupt events. */
1041     ew32(IMC, 0xffffffff);
1042     er32(ICR);
1043 
1044     if (hw->mac.type == e1000_82571) {
1045         /* Install any alternate MAC address into RAR0 */
1046         ret_val = e1000_check_alt_mac_addr_generic(hw);
1047         if (ret_val)
1048             return ret_val;
1049 
1050         e1000e_set_laa_state_82571(hw, true);
1051     }
1052 
1053     /* Reinitialize the 82571 serdes link state machine */
1054     if (hw->phy.media_type == e1000_media_type_internal_serdes)
1055         hw->mac.serdes_link_state = e1000_serdes_link_down;
1056 
1057     return 0;
1058 }
1059 
1060 /**
1061  *  e1000_init_hw_82571 - Initialize hardware
1062  *  @hw: pointer to the HW structure
1063  *
1064  *  This inits the hardware readying it for operation.
1065  **/
1066 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1067 {
1068     struct e1000_mac_info *mac = &hw->mac;
1069     u32 reg_data;
1070     s32 ret_val;
1071     u16 i, rar_count = mac->rar_entry_count;
1072 
1073     e1000_initialize_hw_bits_82571(hw);
1074 
1075     /* Initialize identification LED */
1076     ret_val = mac->ops.id_led_init(hw);
1077     /* An error is not fatal and we should not stop init due to this */
1078     if (ret_val)
1079         e_dbg("Error initializing identification LED\n");
1080 
1081     /* Disabling VLAN filtering */
1082     e_dbg("Initializing the IEEE VLAN\n");
1083     mac->ops.clear_vfta(hw);
1084 
1085     /* Setup the receive address.
1086      * If, however, a locally administered address was assigned to the
1087      * 82571, we must reserve a RAR for it to work around an issue where
1088      * resetting one port will reload the MAC on the other port.
1089      */
1090     if (e1000e_get_laa_state_82571(hw))
1091         rar_count--;
1092     e1000e_init_rx_addrs(hw, rar_count);
1093 
1094     /* Zero out the Multicast HASH table */
1095     e_dbg("Zeroing the MTA\n");
1096     for (i = 0; i < mac->mta_reg_count; i++)
1097         E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1098 
1099     /* Setup link and flow control */
1100     ret_val = mac->ops.setup_link(hw);
1101 
1102     /* Set the transmit descriptor write-back policy */
1103     reg_data = er32(TXDCTL(0));
1104     reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1105             E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1106     ew32(TXDCTL(0), reg_data);
1107 
1108     /* ...for both queues. */
1109     switch (mac->type) {
1110     case e1000_82573:
1111         e1000e_enable_tx_pkt_filtering(hw);
1112         fallthrough;
1113     case e1000_82574:
1114     case e1000_82583:
1115         reg_data = er32(GCR);
1116         reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1117         ew32(GCR, reg_data);
1118         break;
1119     default:
1120         reg_data = er32(TXDCTL(1));
1121         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1122                 E1000_TXDCTL_FULL_TX_DESC_WB |
1123                 E1000_TXDCTL_COUNT_DESC);
1124         ew32(TXDCTL(1), reg_data);
1125         break;
1126     }
1127 
1128     /* Clear all of the statistics registers (clear on read).  It is
1129      * important that we do this after we have tried to establish link
1130      * because the symbol error count will increment wildly if there
1131      * is no link.
1132      */
1133     e1000_clear_hw_cntrs_82571(hw);
1134 
1135     return ret_val;
1136 }
1137 
1138 /**
1139  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1140  *  @hw: pointer to the HW structure
1141  *
1142  *  Initializes required hardware-dependent bits needed for normal operation.
1143  **/
1144 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1145 {
1146     u32 reg;
1147 
1148     /* Transmit Descriptor Control 0 */
1149     reg = er32(TXDCTL(0));
1150     reg |= BIT(22);
1151     ew32(TXDCTL(0), reg);
1152 
1153     /* Transmit Descriptor Control 1 */
1154     reg = er32(TXDCTL(1));
1155     reg |= BIT(22);
1156     ew32(TXDCTL(1), reg);
1157 
1158     /* Transmit Arbitration Control 0 */
1159     reg = er32(TARC(0));
1160     reg &= ~(0xF << 27);    /* 30:27 */
1161     switch (hw->mac.type) {
1162     case e1000_82571:
1163     case e1000_82572:
1164         reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1165         break;
1166     case e1000_82574:
1167     case e1000_82583:
1168         reg |= BIT(26);
1169         break;
1170     default:
1171         break;
1172     }
1173     ew32(TARC(0), reg);
1174 
1175     /* Transmit Arbitration Control 1 */
1176     reg = er32(TARC(1));
1177     switch (hw->mac.type) {
1178     case e1000_82571:
1179     case e1000_82572:
1180         reg &= ~(BIT(29) | BIT(30));
1181         reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1182         if (er32(TCTL) & E1000_TCTL_MULR)
1183             reg &= ~BIT(28);
1184         else
1185             reg |= BIT(28);
1186         ew32(TARC(1), reg);
1187         break;
1188     default:
1189         break;
1190     }
1191 
1192     /* Device Control */
1193     switch (hw->mac.type) {
1194     case e1000_82573:
1195     case e1000_82574:
1196     case e1000_82583:
1197         reg = er32(CTRL);
1198         reg &= ~BIT(29);
1199         ew32(CTRL, reg);
1200         break;
1201     default:
1202         break;
1203     }
1204 
1205     /* Extended Device Control */
1206     switch (hw->mac.type) {
1207     case e1000_82573:
1208     case e1000_82574:
1209     case e1000_82583:
1210         reg = er32(CTRL_EXT);
1211         reg &= ~BIT(23);
1212         reg |= BIT(22);
1213         ew32(CTRL_EXT, reg);
1214         break;
1215     default:
1216         break;
1217     }
1218 
1219     if (hw->mac.type == e1000_82571) {
1220         reg = er32(PBA_ECC);
1221         reg |= E1000_PBA_ECC_CORR_EN;
1222         ew32(PBA_ECC, reg);
1223     }
1224 
1225     /* Workaround for hardware errata.
1226      * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1227      */
1228     if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1229         reg = er32(CTRL_EXT);
1230         reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1231         ew32(CTRL_EXT, reg);
1232     }
1233 
1234     /* Disable IPv6 extension header parsing because some malformed
1235      * IPv6 headers can hang the Rx.
1236      */
1237     if (hw->mac.type <= e1000_82573) {
1238         reg = er32(RFCTL);
1239         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1240         ew32(RFCTL, reg);
1241     }
1242 
1243     /* PCI-Ex Control Registers */
1244     switch (hw->mac.type) {
1245     case e1000_82574:
1246     case e1000_82583:
1247         reg = er32(GCR);
1248         reg |= BIT(22);
1249         ew32(GCR, reg);
1250 
1251         /* Workaround for hardware errata.
1252          * apply workaround for hardware errata documented in errata
1253          * docs Fixes issue where some error prone or unreliable PCIe
1254          * completions are occurring, particularly with ASPM enabled.
1255          * Without fix, issue can cause Tx timeouts.
1256          */
1257         reg = er32(GCR2);
1258         reg |= 1;
1259         ew32(GCR2, reg);
1260         break;
1261     default:
1262         break;
1263     }
1264 }
1265 
1266 /**
1267  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1268  *  @hw: pointer to the HW structure
1269  *
1270  *  Clears the register array which contains the VLAN filter table by
1271  *  setting all the values to 0.
1272  **/
1273 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1274 {
1275     u32 offset;
1276     u32 vfta_value = 0;
1277     u32 vfta_offset = 0;
1278     u32 vfta_bit_in_reg = 0;
1279 
1280     switch (hw->mac.type) {
1281     case e1000_82573:
1282     case e1000_82574:
1283     case e1000_82583:
1284         if (hw->mng_cookie.vlan_id != 0) {
1285             /* The VFTA is a 4096b bit-field, each identifying
1286              * a single VLAN ID.  The following operations
1287              * determine which 32b entry (i.e. offset) into the
1288              * array we want to set the VLAN ID (i.e. bit) of
1289              * the manageability unit.
1290              */
1291             vfta_offset = (hw->mng_cookie.vlan_id >>
1292                        E1000_VFTA_ENTRY_SHIFT) &
1293                 E1000_VFTA_ENTRY_MASK;
1294             vfta_bit_in_reg =
1295                 BIT(hw->mng_cookie.vlan_id &
1296                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1297         }
1298         break;
1299     default:
1300         break;
1301     }
1302     for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1303         /* If the offset we want to clear is the same offset of the
1304          * manageability VLAN ID, then clear all bits except that of
1305          * the manageability unit.
1306          */
1307         vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1308         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1309         e1e_flush();
1310     }
1311 }
1312 
1313 /**
1314  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1315  *  @hw: pointer to the HW structure
1316  *
1317  *  Reads the NVM Initialization Control Word 2 and returns true
1318  *  (>0) if any manageability is enabled, else false (0).
1319  **/
1320 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1321 {
1322     u16 data;
1323 
1324     e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1325     return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1326 }
1327 
1328 /**
1329  *  e1000_led_on_82574 - Turn LED on
1330  *  @hw: pointer to the HW structure
1331  *
1332  *  Turn LED on.
1333  **/
1334 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1335 {
1336     u32 ctrl;
1337     u32 i;
1338 
1339     ctrl = hw->mac.ledctl_mode2;
1340     if (!(E1000_STATUS_LU & er32(STATUS))) {
1341         /* If no link, then turn LED on by setting the invert bit
1342          * for each LED that's "on" (0x0E) in ledctl_mode2.
1343          */
1344         for (i = 0; i < 4; i++)
1345             if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1346                 E1000_LEDCTL_MODE_LED_ON)
1347                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1348     }
1349     ew32(LEDCTL, ctrl);
1350 
1351     return 0;
1352 }
1353 
1354 /**
1355  *  e1000_check_phy_82574 - check 82574 phy hung state
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  Returns whether phy is hung or not
1359  **/
1360 bool e1000_check_phy_82574(struct e1000_hw *hw)
1361 {
1362     u16 status_1kbt = 0;
1363     u16 receive_errors = 0;
1364     s32 ret_val;
1365 
1366     /* Read PHY Receive Error counter first, if its is max - all F's then
1367      * read the Base1000T status register If both are max then PHY is hung.
1368      */
1369     ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1370     if (ret_val)
1371         return false;
1372     if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1373         ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1374         if (ret_val)
1375             return false;
1376         if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1377             E1000_IDLE_ERROR_COUNT_MASK)
1378             return true;
1379     }
1380 
1381     return false;
1382 }
1383 
1384 /**
1385  *  e1000_setup_link_82571 - Setup flow control and link settings
1386  *  @hw: pointer to the HW structure
1387  *
1388  *  Determines which flow control settings to use, then configures flow
1389  *  control.  Calls the appropriate media-specific link configuration
1390  *  function.  Assuming the adapter has a valid link partner, a valid link
1391  *  should be established.  Assumes the hardware has previously been reset
1392  *  and the transmitter and receiver are not enabled.
1393  **/
1394 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1395 {
1396     /* 82573 does not have a word in the NVM to determine
1397      * the default flow control setting, so we explicitly
1398      * set it to full.
1399      */
1400     switch (hw->mac.type) {
1401     case e1000_82573:
1402     case e1000_82574:
1403     case e1000_82583:
1404         if (hw->fc.requested_mode == e1000_fc_default)
1405             hw->fc.requested_mode = e1000_fc_full;
1406         break;
1407     default:
1408         break;
1409     }
1410 
1411     return e1000e_setup_link_generic(hw);
1412 }
1413 
1414 /**
1415  *  e1000_setup_copper_link_82571 - Configure copper link settings
1416  *  @hw: pointer to the HW structure
1417  *
1418  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1419  *  for link, once link is established calls to configure collision distance
1420  *  and flow control are called.
1421  **/
1422 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1423 {
1424     u32 ctrl;
1425     s32 ret_val;
1426 
1427     ctrl = er32(CTRL);
1428     ctrl |= E1000_CTRL_SLU;
1429     ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1430     ew32(CTRL, ctrl);
1431 
1432     switch (hw->phy.type) {
1433     case e1000_phy_m88:
1434     case e1000_phy_bm:
1435         ret_val = e1000e_copper_link_setup_m88(hw);
1436         break;
1437     case e1000_phy_igp_2:
1438         ret_val = e1000e_copper_link_setup_igp(hw);
1439         break;
1440     default:
1441         return -E1000_ERR_PHY;
1442     }
1443 
1444     if (ret_val)
1445         return ret_val;
1446 
1447     return e1000e_setup_copper_link(hw);
1448 }
1449 
1450 /**
1451  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1452  *  @hw: pointer to the HW structure
1453  *
1454  *  Configures collision distance and flow control for fiber and serdes links.
1455  *  Upon successful setup, poll for link.
1456  **/
1457 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1458 {
1459     switch (hw->mac.type) {
1460     case e1000_82571:
1461     case e1000_82572:
1462         /* If SerDes loopback mode is entered, there is no form
1463          * of reset to take the adapter out of that mode.  So we
1464          * have to explicitly take the adapter out of loopback
1465          * mode.  This prevents drivers from twiddling their thumbs
1466          * if another tool failed to take it out of loopback mode.
1467          */
1468         ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1469         break;
1470     default:
1471         break;
1472     }
1473 
1474     return e1000e_setup_fiber_serdes_link(hw);
1475 }
1476 
1477 /**
1478  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1479  *  @hw: pointer to the HW structure
1480  *
1481  *  Reports the link state as up or down.
1482  *
1483  *  If autonegotiation is supported by the link partner, the link state is
1484  *  determined by the result of autonegotiation. This is the most likely case.
1485  *  If autonegotiation is not supported by the link partner, and the link
1486  *  has a valid signal, force the link up.
1487  *
1488  *  The link state is represented internally here by 4 states:
1489  *
1490  *  1) down
1491  *  2) autoneg_progress
1492  *  3) autoneg_complete (the link successfully autonegotiated)
1493  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1494  *
1495  **/
1496 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1497 {
1498     struct e1000_mac_info *mac = &hw->mac;
1499     u32 rxcw;
1500     u32 ctrl;
1501     u32 status;
1502     u32 txcw;
1503     u32 i;
1504     s32 ret_val = 0;
1505 
1506     ctrl = er32(CTRL);
1507     status = er32(STATUS);
1508     er32(RXCW);
1509     /* SYNCH bit and IV bit are sticky */
1510     usleep_range(10, 20);
1511     rxcw = er32(RXCW);
1512 
1513     if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1514         /* Receiver is synchronized with no invalid bits.  */
1515         switch (mac->serdes_link_state) {
1516         case e1000_serdes_link_autoneg_complete:
1517             if (!(status & E1000_STATUS_LU)) {
1518                 /* We have lost link, retry autoneg before
1519                  * reporting link failure
1520                  */
1521                 mac->serdes_link_state =
1522                     e1000_serdes_link_autoneg_progress;
1523                 mac->serdes_has_link = false;
1524                 e_dbg("AN_UP     -> AN_PROG\n");
1525             } else {
1526                 mac->serdes_has_link = true;
1527             }
1528             break;
1529 
1530         case e1000_serdes_link_forced_up:
1531             /* If we are receiving /C/ ordered sets, re-enable
1532              * auto-negotiation in the TXCW register and disable
1533              * forced link in the Device Control register in an
1534              * attempt to auto-negotiate with our link partner.
1535              */
1536             if (rxcw & E1000_RXCW_C) {
1537                 /* Enable autoneg, and unforce link up */
1538                 ew32(TXCW, mac->txcw);
1539                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1540                 mac->serdes_link_state =
1541                     e1000_serdes_link_autoneg_progress;
1542                 mac->serdes_has_link = false;
1543                 e_dbg("FORCED_UP -> AN_PROG\n");
1544             } else {
1545                 mac->serdes_has_link = true;
1546             }
1547             break;
1548 
1549         case e1000_serdes_link_autoneg_progress:
1550             if (rxcw & E1000_RXCW_C) {
1551                 /* We received /C/ ordered sets, meaning the
1552                  * link partner has autonegotiated, and we can
1553                  * trust the Link Up (LU) status bit.
1554                  */
1555                 if (status & E1000_STATUS_LU) {
1556                     mac->serdes_link_state =
1557                         e1000_serdes_link_autoneg_complete;
1558                     e_dbg("AN_PROG   -> AN_UP\n");
1559                     mac->serdes_has_link = true;
1560                 } else {
1561                     /* Autoneg completed, but failed. */
1562                     mac->serdes_link_state =
1563                         e1000_serdes_link_down;
1564                     e_dbg("AN_PROG   -> DOWN\n");
1565                 }
1566             } else {
1567                 /* The link partner did not autoneg.
1568                  * Force link up and full duplex, and change
1569                  * state to forced.
1570                  */
1571                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1572                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1573                 ew32(CTRL, ctrl);
1574 
1575                 /* Configure Flow Control after link up. */
1576                 ret_val = e1000e_config_fc_after_link_up(hw);
1577                 if (ret_val) {
1578                     e_dbg("Error config flow control\n");
1579                     break;
1580                 }
1581                 mac->serdes_link_state =
1582                     e1000_serdes_link_forced_up;
1583                 mac->serdes_has_link = true;
1584                 e_dbg("AN_PROG   -> FORCED_UP\n");
1585             }
1586             break;
1587 
1588         case e1000_serdes_link_down:
1589         default:
1590             /* The link was down but the receiver has now gained
1591              * valid sync, so lets see if we can bring the link
1592              * up.
1593              */
1594             ew32(TXCW, mac->txcw);
1595             ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1596             mac->serdes_link_state =
1597                 e1000_serdes_link_autoneg_progress;
1598             mac->serdes_has_link = false;
1599             e_dbg("DOWN      -> AN_PROG\n");
1600             break;
1601         }
1602     } else {
1603         if (!(rxcw & E1000_RXCW_SYNCH)) {
1604             mac->serdes_has_link = false;
1605             mac->serdes_link_state = e1000_serdes_link_down;
1606             e_dbg("ANYSTATE  -> DOWN\n");
1607         } else {
1608             /* Check several times, if SYNCH bit and CONFIG
1609              * bit both are consistently 1 then simply ignore
1610              * the IV bit and restart Autoneg
1611              */
1612             for (i = 0; i < AN_RETRY_COUNT; i++) {
1613                 usleep_range(10, 20);
1614                 rxcw = er32(RXCW);
1615                 if ((rxcw & E1000_RXCW_SYNCH) &&
1616                     (rxcw & E1000_RXCW_C))
1617                     continue;
1618 
1619                 if (rxcw & E1000_RXCW_IV) {
1620                     mac->serdes_has_link = false;
1621                     mac->serdes_link_state =
1622                         e1000_serdes_link_down;
1623                     e_dbg("ANYSTATE  -> DOWN\n");
1624                     break;
1625                 }
1626             }
1627 
1628             if (i == AN_RETRY_COUNT) {
1629                 txcw = er32(TXCW);
1630                 txcw |= E1000_TXCW_ANE;
1631                 ew32(TXCW, txcw);
1632                 mac->serdes_link_state =
1633                     e1000_serdes_link_autoneg_progress;
1634                 mac->serdes_has_link = false;
1635                 e_dbg("ANYSTATE  -> AN_PROG\n");
1636             }
1637         }
1638     }
1639 
1640     return ret_val;
1641 }
1642 
1643 /**
1644  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1645  *  @hw: pointer to the HW structure
1646  *  @data: pointer to the NVM (EEPROM)
1647  *
1648  *  Read the EEPROM for the current default LED configuration.  If the
1649  *  LED configuration is not valid, set to a valid LED configuration.
1650  **/
1651 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1652 {
1653     s32 ret_val;
1654 
1655     ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1656     if (ret_val) {
1657         e_dbg("NVM Read Error\n");
1658         return ret_val;
1659     }
1660 
1661     switch (hw->mac.type) {
1662     case e1000_82573:
1663     case e1000_82574:
1664     case e1000_82583:
1665         if (*data == ID_LED_RESERVED_F746)
1666             *data = ID_LED_DEFAULT_82573;
1667         break;
1668     default:
1669         if (*data == ID_LED_RESERVED_0000 ||
1670             *data == ID_LED_RESERVED_FFFF)
1671             *data = ID_LED_DEFAULT;
1672         break;
1673     }
1674 
1675     return 0;
1676 }
1677 
1678 /**
1679  *  e1000e_get_laa_state_82571 - Get locally administered address state
1680  *  @hw: pointer to the HW structure
1681  *
1682  *  Retrieve and return the current locally administered address state.
1683  **/
1684 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1685 {
1686     if (hw->mac.type != e1000_82571)
1687         return false;
1688 
1689     return hw->dev_spec.e82571.laa_is_present;
1690 }
1691 
1692 /**
1693  *  e1000e_set_laa_state_82571 - Set locally administered address state
1694  *  @hw: pointer to the HW structure
1695  *  @state: enable/disable locally administered address
1696  *
1697  *  Enable/Disable the current locally administered address state.
1698  **/
1699 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1700 {
1701     if (hw->mac.type != e1000_82571)
1702         return;
1703 
1704     hw->dev_spec.e82571.laa_is_present = state;
1705 
1706     /* If workaround is activated... */
1707     if (state)
1708         /* Hold a copy of the LAA in RAR[14] This is done so that
1709          * between the time RAR[0] gets clobbered and the time it
1710          * gets fixed, the actual LAA is in one of the RARs and no
1711          * incoming packets directed to this port are dropped.
1712          * Eventually the LAA will be in RAR[0] and RAR[14].
1713          */
1714         hw->mac.ops.rar_set(hw, hw->mac.addr,
1715                     hw->mac.rar_entry_count - 1);
1716 }
1717 
1718 /**
1719  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1720  *  @hw: pointer to the HW structure
1721  *
1722  *  Verifies that the EEPROM has completed the update.  After updating the
1723  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1724  *  the checksum fix is not implemented, we need to set the bit and update
1725  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1726  *  we need to return bad checksum.
1727  **/
1728 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1729 {
1730     struct e1000_nvm_info *nvm = &hw->nvm;
1731     s32 ret_val;
1732     u16 data;
1733 
1734     if (nvm->type != e1000_nvm_flash_hw)
1735         return 0;
1736 
1737     /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1738      * 10h-12h.  Checksum may need to be fixed.
1739      */
1740     ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1741     if (ret_val)
1742         return ret_val;
1743 
1744     if (!(data & 0x10)) {
1745         /* Read 0x23 and check bit 15.  This bit is a 1
1746          * when the checksum has already been fixed.  If
1747          * the checksum is still wrong and this bit is a
1748          * 1, we need to return bad checksum.  Otherwise,
1749          * we need to set this bit to a 1 and update the
1750          * checksum.
1751          */
1752         ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1753         if (ret_val)
1754             return ret_val;
1755 
1756         if (!(data & 0x8000)) {
1757             data |= 0x8000;
1758             ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1759             if (ret_val)
1760                 return ret_val;
1761             ret_val = e1000e_update_nvm_checksum(hw);
1762             if (ret_val)
1763                 return ret_val;
1764         }
1765     }
1766 
1767     return 0;
1768 }
1769 
1770 /**
1771  *  e1000_read_mac_addr_82571 - Read device MAC address
1772  *  @hw: pointer to the HW structure
1773  **/
1774 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1775 {
1776     if (hw->mac.type == e1000_82571) {
1777         s32 ret_val;
1778 
1779         /* If there's an alternate MAC address place it in RAR0
1780          * so that it will override the Si installed default perm
1781          * address.
1782          */
1783         ret_val = e1000_check_alt_mac_addr_generic(hw);
1784         if (ret_val)
1785             return ret_val;
1786     }
1787 
1788     return e1000_read_mac_addr_generic(hw);
1789 }
1790 
1791 /**
1792  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1793  * @hw: pointer to the HW structure
1794  *
1795  * In the case of a PHY power down to save power, or to turn off link during a
1796  * driver unload, or wake on lan is not enabled, remove the link.
1797  **/
1798 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1799 {
1800     struct e1000_phy_info *phy = &hw->phy;
1801     struct e1000_mac_info *mac = &hw->mac;
1802 
1803     if (!phy->ops.check_reset_block)
1804         return;
1805 
1806     /* If the management interface is not enabled, then power down */
1807     if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1808         e1000_power_down_phy_copper(hw);
1809 }
1810 
1811 /**
1812  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1813  *  @hw: pointer to the HW structure
1814  *
1815  *  Clears the hardware counters by reading the counter registers.
1816  **/
1817 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1818 {
1819     e1000e_clear_hw_cntrs_base(hw);
1820 
1821     er32(PRC64);
1822     er32(PRC127);
1823     er32(PRC255);
1824     er32(PRC511);
1825     er32(PRC1023);
1826     er32(PRC1522);
1827     er32(PTC64);
1828     er32(PTC127);
1829     er32(PTC255);
1830     er32(PTC511);
1831     er32(PTC1023);
1832     er32(PTC1522);
1833 
1834     er32(ALGNERRC);
1835     er32(RXERRC);
1836     er32(TNCRS);
1837     er32(CEXTERR);
1838     er32(TSCTC);
1839     er32(TSCTFC);
1840 
1841     er32(MGTPRC);
1842     er32(MGTPDC);
1843     er32(MGTPTC);
1844 
1845     er32(IAC);
1846     er32(ICRXOC);
1847 
1848     er32(ICRXPTC);
1849     er32(ICRXATC);
1850     er32(ICTXPTC);
1851     er32(ICTXATC);
1852     er32(ICTXQEC);
1853     er32(ICTXQMTC);
1854     er32(ICRXDMTC);
1855 }
1856 
1857 static const struct e1000_mac_operations e82571_mac_ops = {
1858     /* .check_mng_mode: mac type dependent */
1859     /* .check_for_link: media type dependent */
1860     .id_led_init        = e1000e_id_led_init_generic,
1861     .cleanup_led        = e1000e_cleanup_led_generic,
1862     .clear_hw_cntrs     = e1000_clear_hw_cntrs_82571,
1863     .get_bus_info       = e1000e_get_bus_info_pcie,
1864     .set_lan_id     = e1000_set_lan_id_multi_port_pcie,
1865     /* .get_link_up_info: media type dependent */
1866     /* .led_on: mac type dependent */
1867     .led_off        = e1000e_led_off_generic,
1868     .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1869     .write_vfta     = e1000_write_vfta_generic,
1870     .clear_vfta     = e1000_clear_vfta_82571,
1871     .reset_hw       = e1000_reset_hw_82571,
1872     .init_hw        = e1000_init_hw_82571,
1873     .setup_link     = e1000_setup_link_82571,
1874     /* .setup_physical_interface: media type dependent */
1875     .setup_led      = e1000e_setup_led_generic,
1876     .config_collision_dist  = e1000e_config_collision_dist_generic,
1877     .read_mac_addr      = e1000_read_mac_addr_82571,
1878     .rar_set        = e1000e_rar_set_generic,
1879     .rar_get_count      = e1000e_rar_get_count_generic,
1880 };
1881 
1882 static const struct e1000_phy_operations e82_phy_ops_igp = {
1883     .acquire        = e1000_get_hw_semaphore_82571,
1884     .check_polarity     = e1000_check_polarity_igp,
1885     .check_reset_block  = e1000e_check_reset_block_generic,
1886     .commit         = NULL,
1887     .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1888     .get_cfg_done       = e1000_get_cfg_done_82571,
1889     .get_cable_length   = e1000e_get_cable_length_igp_2,
1890     .get_info       = e1000e_get_phy_info_igp,
1891     .read_reg       = e1000e_read_phy_reg_igp,
1892     .release        = e1000_put_hw_semaphore_82571,
1893     .reset          = e1000e_phy_hw_reset_generic,
1894     .set_d0_lplu_state  = e1000_set_d0_lplu_state_82571,
1895     .set_d3_lplu_state  = e1000e_set_d3_lplu_state,
1896     .write_reg      = e1000e_write_phy_reg_igp,
1897     .cfg_on_link_up     = NULL,
1898 };
1899 
1900 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1901     .acquire        = e1000_get_hw_semaphore_82571,
1902     .check_polarity     = e1000_check_polarity_m88,
1903     .check_reset_block  = e1000e_check_reset_block_generic,
1904     .commit         = e1000e_phy_sw_reset,
1905     .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1906     .get_cfg_done       = e1000e_get_cfg_done_generic,
1907     .get_cable_length   = e1000e_get_cable_length_m88,
1908     .get_info       = e1000e_get_phy_info_m88,
1909     .read_reg       = e1000e_read_phy_reg_m88,
1910     .release        = e1000_put_hw_semaphore_82571,
1911     .reset          = e1000e_phy_hw_reset_generic,
1912     .set_d0_lplu_state  = e1000_set_d0_lplu_state_82571,
1913     .set_d3_lplu_state  = e1000e_set_d3_lplu_state,
1914     .write_reg      = e1000e_write_phy_reg_m88,
1915     .cfg_on_link_up     = NULL,
1916 };
1917 
1918 static const struct e1000_phy_operations e82_phy_ops_bm = {
1919     .acquire        = e1000_get_hw_semaphore_82571,
1920     .check_polarity     = e1000_check_polarity_m88,
1921     .check_reset_block  = e1000e_check_reset_block_generic,
1922     .commit         = e1000e_phy_sw_reset,
1923     .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1924     .get_cfg_done       = e1000e_get_cfg_done_generic,
1925     .get_cable_length   = e1000e_get_cable_length_m88,
1926     .get_info       = e1000e_get_phy_info_m88,
1927     .read_reg       = e1000e_read_phy_reg_bm2,
1928     .release        = e1000_put_hw_semaphore_82571,
1929     .reset          = e1000e_phy_hw_reset_generic,
1930     .set_d0_lplu_state  = e1000_set_d0_lplu_state_82571,
1931     .set_d3_lplu_state  = e1000e_set_d3_lplu_state,
1932     .write_reg      = e1000e_write_phy_reg_bm2,
1933     .cfg_on_link_up     = NULL,
1934 };
1935 
1936 static const struct e1000_nvm_operations e82571_nvm_ops = {
1937     .acquire        = e1000_acquire_nvm_82571,
1938     .read           = e1000e_read_nvm_eerd,
1939     .release        = e1000_release_nvm_82571,
1940     .reload         = e1000e_reload_nvm_generic,
1941     .update         = e1000_update_nvm_checksum_82571,
1942     .valid_led_default  = e1000_valid_led_default_82571,
1943     .validate       = e1000_validate_nvm_checksum_82571,
1944     .write          = e1000_write_nvm_82571,
1945 };
1946 
1947 const struct e1000_info e1000_82571_info = {
1948     .mac            = e1000_82571,
1949     .flags          = FLAG_HAS_HW_VLAN_FILTER
1950                   | FLAG_HAS_JUMBO_FRAMES
1951                   | FLAG_HAS_WOL
1952                   | FLAG_APME_IN_CTRL3
1953                   | FLAG_HAS_CTRLEXT_ON_LOAD
1954                   | FLAG_HAS_SMART_POWER_DOWN
1955                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1956                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1957                   | FLAG_APME_CHECK_PORT_B,
1958     .flags2         = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1959                   | FLAG2_DMA_BURST,
1960     .pba            = 38,
1961     .max_hw_frame_size  = DEFAULT_JUMBO,
1962     .get_variants       = e1000_get_variants_82571,
1963     .mac_ops        = &e82571_mac_ops,
1964     .phy_ops        = &e82_phy_ops_igp,
1965     .nvm_ops        = &e82571_nvm_ops,
1966 };
1967 
1968 const struct e1000_info e1000_82572_info = {
1969     .mac            = e1000_82572,
1970     .flags          = FLAG_HAS_HW_VLAN_FILTER
1971                   | FLAG_HAS_JUMBO_FRAMES
1972                   | FLAG_HAS_WOL
1973                   | FLAG_APME_IN_CTRL3
1974                   | FLAG_HAS_CTRLEXT_ON_LOAD
1975                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1976     .flags2         = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1977                   | FLAG2_DMA_BURST,
1978     .pba            = 38,
1979     .max_hw_frame_size  = DEFAULT_JUMBO,
1980     .get_variants       = e1000_get_variants_82571,
1981     .mac_ops        = &e82571_mac_ops,
1982     .phy_ops        = &e82_phy_ops_igp,
1983     .nvm_ops        = &e82571_nvm_ops,
1984 };
1985 
1986 const struct e1000_info e1000_82573_info = {
1987     .mac            = e1000_82573,
1988     .flags          = FLAG_HAS_HW_VLAN_FILTER
1989                   | FLAG_HAS_WOL
1990                   | FLAG_APME_IN_CTRL3
1991                   | FLAG_HAS_SMART_POWER_DOWN
1992                   | FLAG_HAS_AMT
1993                   | FLAG_HAS_SWSM_ON_LOAD,
1994     .flags2         = FLAG2_DISABLE_ASPM_L1
1995                   | FLAG2_DISABLE_ASPM_L0S,
1996     .pba            = 20,
1997     .max_hw_frame_size  = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
1998     .get_variants       = e1000_get_variants_82571,
1999     .mac_ops        = &e82571_mac_ops,
2000     .phy_ops        = &e82_phy_ops_m88,
2001     .nvm_ops        = &e82571_nvm_ops,
2002 };
2003 
2004 const struct e1000_info e1000_82574_info = {
2005     .mac            = e1000_82574,
2006     .flags          = FLAG_HAS_HW_VLAN_FILTER
2007                   | FLAG_HAS_MSIX
2008                   | FLAG_HAS_JUMBO_FRAMES
2009                   | FLAG_HAS_WOL
2010                   | FLAG_HAS_HW_TIMESTAMP
2011                   | FLAG_APME_IN_CTRL3
2012                   | FLAG_HAS_SMART_POWER_DOWN
2013                   | FLAG_HAS_AMT
2014                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2015     .flags2          = FLAG2_CHECK_PHY_HANG
2016                   | FLAG2_DISABLE_ASPM_L0S
2017                   | FLAG2_DISABLE_ASPM_L1
2018                   | FLAG2_NO_DISABLE_RX
2019                   | FLAG2_DMA_BURST
2020                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
2021     .pba            = 32,
2022     .max_hw_frame_size  = DEFAULT_JUMBO,
2023     .get_variants       = e1000_get_variants_82571,
2024     .mac_ops        = &e82571_mac_ops,
2025     .phy_ops        = &e82_phy_ops_bm,
2026     .nvm_ops        = &e82571_nvm_ops,
2027 };
2028 
2029 const struct e1000_info e1000_82583_info = {
2030     .mac            = e1000_82583,
2031     .flags          = FLAG_HAS_HW_VLAN_FILTER
2032                   | FLAG_HAS_WOL
2033                   | FLAG_HAS_HW_TIMESTAMP
2034                   | FLAG_APME_IN_CTRL3
2035                   | FLAG_HAS_SMART_POWER_DOWN
2036                   | FLAG_HAS_AMT
2037                   | FLAG_HAS_JUMBO_FRAMES
2038                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2039     .flags2         = FLAG2_DISABLE_ASPM_L0S
2040                   | FLAG2_DISABLE_ASPM_L1
2041                   | FLAG2_NO_DISABLE_RX
2042                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
2043     .pba            = 32,
2044     .max_hw_frame_size  = DEFAULT_JUMBO,
2045     .get_variants       = e1000_get_variants_82571,
2046     .mac_ops        = &e82571_mac_ops,
2047     .phy_ops        = &e82_phy_ops_bm,
2048     .nvm_ops        = &e82571_nvm_ops,
2049 };
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