intel/e1000e/80003es2lan.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000E_80003ES2LAN_H_
0005 #define _E1000E_80003ES2LAN_H_
0006
0007 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL  0x00
0008 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL   0x02
0009 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL    0x10
0010 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
0011
0012 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS   0x0008
0013 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS   0x0800
0014 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING  0x0010
0015
0016 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
0017 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT  0x0000
0018 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE     0x2000
0019
0020 #define E1000_KMRNCTRLSTA_OPMODE_MASK       0x000C
0021 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO    0x0004
0022
0023 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
0024 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN   0x00010000
0025
0026 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN  0x8
0027 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN    0x9
0028
0029 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
0030 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002  /* 1=Reversal Dis */
0031 #define GG82563_PSCR_CROSSOVER_MODE_MASK    0x0060
0032 #define GG82563_PSCR_CROSSOVER_MODE_MDI     0x0000  /* 00=Manual MDI */
0033 #define GG82563_PSCR_CROSSOVER_MODE_MDIX    0x0020  /* 01=Manual MDIX */
0034 #define GG82563_PSCR_CROSSOVER_MODE_AUTO    0x0060  /* 11=Auto crossover */
0035
0036 /* PHY Specific Control Register 2 (Page 0, Register 26) */
0037 #define GG82563_PSCR2_REVERSE_AUTO_NEG      0x2000  /* 1=Reverse Auto-Neg */
0038
0039 /* MAC Specific Control Register (Page 2, Register 21) */
0040 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
0041 #define GG82563_MSCR_TX_CLK_MASK        0x0007
0042 #define GG82563_MSCR_TX_CLK_10MBPS_2_5      0x0004
0043 #define GG82563_MSCR_TX_CLK_100MBPS_25      0x0005
0044 #define GG82563_MSCR_TX_CLK_1000MBPS_25     0x0007
0045
0046 #define GG82563_MSCR_ASSERT_CRS_ON_TX       0x0010  /* 1=Assert */
0047
0048 /* DSP Distance Register (Page 5, Register 26)
0049  * 0 = <50M
0050  * 1 = 50-80M
0051  * 2 = 80-100M
0052  * 3 = 110-140M
0053  * 4 = >140M
0054  */
0055 #define GG82563_DSPD_CABLE_LENGTH       0x0007
0056
0057 /* Kumeran Mode Control Register (Page 193, Register 16) */
0058 #define GG82563_KMCR_PASS_FALSE_CARRIER     0x0800
0059
0060 /* Max number of times Kumeran read/write should be validated */
0061 #define GG82563_MAX_KMRN_RETRY          0x5
0062
0063 /* Power Management Control Register (Page 193, Register 20) */
0064 /* 1=Enable SERDES Electrical Idle */
0065 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
0066
0067 /* In-Band Control Register (Page 194, Register 18) */
0068 #define GG82563_ICR_DIS_PADDING         0x0010  /* Disable Padding */
0069
0070 #endif