Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003 
0004 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
0005  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
0006  */
0007 
0008 #include "e1000.h"
0009 
0010 /* A table for the GG82563 cable length where the range is defined
0011  * with a lower bound at "index" and the upper bound at
0012  * "index + 5".
0013  */
0014 static const u16 e1000_gg82563_cable_length_table[] = {
0015     0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
0016 };
0017 
0018 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
0019         ARRAY_SIZE(e1000_gg82563_cable_length_table)
0020 
0021 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
0022 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
0023 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
0024 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
0025 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
0026 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
0027 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
0028 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
0029                        u16 *data);
0030 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
0031                         u16 data);
0032 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
0033 
0034 /**
0035  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
0036  *  @hw: pointer to the HW structure
0037  **/
0038 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
0039 {
0040     struct e1000_phy_info *phy = &hw->phy;
0041     s32 ret_val;
0042 
0043     if (hw->phy.media_type != e1000_media_type_copper) {
0044         phy->type = e1000_phy_none;
0045         return 0;
0046     } else {
0047         phy->ops.power_up = e1000_power_up_phy_copper;
0048         phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
0049     }
0050 
0051     phy->addr = 1;
0052     phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
0053     phy->reset_delay_us = 100;
0054     phy->type = e1000_phy_gg82563;
0055 
0056     /* This can only be done after all function pointers are setup. */
0057     ret_val = e1000e_get_phy_id(hw);
0058 
0059     /* Verify phy id */
0060     if (phy->id != GG82563_E_PHY_ID)
0061         return -E1000_ERR_PHY;
0062 
0063     return ret_val;
0064 }
0065 
0066 /**
0067  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
0068  *  @hw: pointer to the HW structure
0069  **/
0070 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
0071 {
0072     struct e1000_nvm_info *nvm = &hw->nvm;
0073     u32 eecd = er32(EECD);
0074     u16 size;
0075 
0076     nvm->opcode_bits = 8;
0077     nvm->delay_usec = 1;
0078     switch (nvm->override) {
0079     case e1000_nvm_override_spi_large:
0080         nvm->page_size = 32;
0081         nvm->address_bits = 16;
0082         break;
0083     case e1000_nvm_override_spi_small:
0084         nvm->page_size = 8;
0085         nvm->address_bits = 8;
0086         break;
0087     default:
0088         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
0089         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
0090         break;
0091     }
0092 
0093     nvm->type = e1000_nvm_eeprom_spi;
0094 
0095     size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
0096              E1000_EECD_SIZE_EX_SHIFT);
0097 
0098     /* Added to a constant, "size" becomes the left-shift value
0099      * for setting word_size.
0100      */
0101     size += NVM_WORD_SIZE_BASE_SHIFT;
0102 
0103     /* EEPROM access above 16k is unsupported */
0104     if (size > 14)
0105         size = 14;
0106     nvm->word_size = BIT(size);
0107 
0108     return 0;
0109 }
0110 
0111 /**
0112  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
0113  *  @hw: pointer to the HW structure
0114  **/
0115 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
0116 {
0117     struct e1000_mac_info *mac = &hw->mac;
0118 
0119     /* Set media type and media-dependent function pointers */
0120     switch (hw->adapter->pdev->device) {
0121     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
0122         hw->phy.media_type = e1000_media_type_internal_serdes;
0123         mac->ops.check_for_link = e1000e_check_for_serdes_link;
0124         mac->ops.setup_physical_interface =
0125             e1000e_setup_fiber_serdes_link;
0126         break;
0127     default:
0128         hw->phy.media_type = e1000_media_type_copper;
0129         mac->ops.check_for_link = e1000e_check_for_copper_link;
0130         mac->ops.setup_physical_interface =
0131             e1000_setup_copper_link_80003es2lan;
0132         break;
0133     }
0134 
0135     /* Set mta register count */
0136     mac->mta_reg_count = 128;
0137     /* Set rar entry count */
0138     mac->rar_entry_count = E1000_RAR_ENTRIES;
0139     /* FWSM register */
0140     mac->has_fwsm = true;
0141     /* ARC supported; valid only if manageability features are enabled. */
0142     mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
0143     /* Adaptive IFS not supported */
0144     mac->adaptive_ifs = false;
0145 
0146     /* set lan id for port to determine which phy lock to use */
0147     hw->mac.ops.set_lan_id(hw);
0148 
0149     return 0;
0150 }
0151 
0152 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
0153 {
0154     struct e1000_hw *hw = &adapter->hw;
0155     s32 rc;
0156 
0157     rc = e1000_init_mac_params_80003es2lan(hw);
0158     if (rc)
0159         return rc;
0160 
0161     rc = e1000_init_nvm_params_80003es2lan(hw);
0162     if (rc)
0163         return rc;
0164 
0165     rc = e1000_init_phy_params_80003es2lan(hw);
0166     if (rc)
0167         return rc;
0168 
0169     return 0;
0170 }
0171 
0172 /**
0173  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
0174  *  @hw: pointer to the HW structure
0175  *
0176  *  A wrapper to acquire access rights to the correct PHY.
0177  **/
0178 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
0179 {
0180     u16 mask;
0181 
0182     mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
0183     return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
0184 }
0185 
0186 /**
0187  *  e1000_release_phy_80003es2lan - Release rights to access PHY
0188  *  @hw: pointer to the HW structure
0189  *
0190  *  A wrapper to release access rights to the correct PHY.
0191  **/
0192 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
0193 {
0194     u16 mask;
0195 
0196     mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
0197     e1000_release_swfw_sync_80003es2lan(hw, mask);
0198 }
0199 
0200 /**
0201  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
0202  *  @hw: pointer to the HW structure
0203  *
0204  *  Acquire the semaphore to access the Kumeran interface.
0205  *
0206  **/
0207 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
0208 {
0209     u16 mask;
0210 
0211     mask = E1000_SWFW_CSR_SM;
0212 
0213     return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
0214 }
0215 
0216 /**
0217  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
0218  *  @hw: pointer to the HW structure
0219  *
0220  *  Release the semaphore used to access the Kumeran interface
0221  **/
0222 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
0223 {
0224     u16 mask;
0225 
0226     mask = E1000_SWFW_CSR_SM;
0227 
0228     e1000_release_swfw_sync_80003es2lan(hw, mask);
0229 }
0230 
0231 /**
0232  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
0233  *  @hw: pointer to the HW structure
0234  *
0235  *  Acquire the semaphore to access the EEPROM.
0236  **/
0237 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
0238 {
0239     s32 ret_val;
0240 
0241     ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
0242     if (ret_val)
0243         return ret_val;
0244 
0245     ret_val = e1000e_acquire_nvm(hw);
0246 
0247     if (ret_val)
0248         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
0249 
0250     return ret_val;
0251 }
0252 
0253 /**
0254  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
0255  *  @hw: pointer to the HW structure
0256  *
0257  *  Release the semaphore used to access the EEPROM.
0258  **/
0259 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
0260 {
0261     e1000e_release_nvm(hw);
0262     e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
0263 }
0264 
0265 /**
0266  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
0267  *  @hw: pointer to the HW structure
0268  *  @mask: specifies which semaphore to acquire
0269  *
0270  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
0271  *  will also specify which port we're acquiring the lock for.
0272  **/
0273 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
0274 {
0275     u32 swfw_sync;
0276     u32 swmask = mask;
0277     u32 fwmask = mask << 16;
0278     s32 i = 0;
0279     s32 timeout = 50;
0280 
0281     while (i < timeout) {
0282         if (e1000e_get_hw_semaphore(hw))
0283             return -E1000_ERR_SWFW_SYNC;
0284 
0285         swfw_sync = er32(SW_FW_SYNC);
0286         if (!(swfw_sync & (fwmask | swmask)))
0287             break;
0288 
0289         /* Firmware currently using resource (fwmask)
0290          * or other software thread using resource (swmask)
0291          */
0292         e1000e_put_hw_semaphore(hw);
0293         mdelay(5);
0294         i++;
0295     }
0296 
0297     if (i == timeout) {
0298         e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
0299         return -E1000_ERR_SWFW_SYNC;
0300     }
0301 
0302     swfw_sync |= swmask;
0303     ew32(SW_FW_SYNC, swfw_sync);
0304 
0305     e1000e_put_hw_semaphore(hw);
0306 
0307     return 0;
0308 }
0309 
0310 /**
0311  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
0312  *  @hw: pointer to the HW structure
0313  *  @mask: specifies which semaphore to acquire
0314  *
0315  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
0316  *  will also specify which port we're releasing the lock for.
0317  **/
0318 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
0319 {
0320     u32 swfw_sync;
0321 
0322     while (e1000e_get_hw_semaphore(hw) != 0)
0323         ; /* Empty */
0324 
0325     swfw_sync = er32(SW_FW_SYNC);
0326     swfw_sync &= ~mask;
0327     ew32(SW_FW_SYNC, swfw_sync);
0328 
0329     e1000e_put_hw_semaphore(hw);
0330 }
0331 
0332 /**
0333  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
0334  *  @hw: pointer to the HW structure
0335  *  @offset: offset of the register to read
0336  *  @data: pointer to the data returned from the operation
0337  *
0338  *  Read the GG82563 PHY register.
0339  **/
0340 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
0341                           u32 offset, u16 *data)
0342 {
0343     s32 ret_val;
0344     u32 page_select;
0345     u16 temp;
0346 
0347     ret_val = e1000_acquire_phy_80003es2lan(hw);
0348     if (ret_val)
0349         return ret_val;
0350 
0351     /* Select Configuration Page */
0352     if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
0353         page_select = GG82563_PHY_PAGE_SELECT;
0354     } else {
0355         /* Use Alternative Page Select register to access
0356          * registers 30 and 31
0357          */
0358         page_select = GG82563_PHY_PAGE_SELECT_ALT;
0359     }
0360 
0361     temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
0362     ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
0363     if (ret_val) {
0364         e1000_release_phy_80003es2lan(hw);
0365         return ret_val;
0366     }
0367 
0368     if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
0369         /* The "ready" bit in the MDIC register may be incorrectly set
0370          * before the device has completed the "Page Select" MDI
0371          * transaction.  So we wait 200us after each MDI command...
0372          */
0373         usleep_range(200, 400);
0374 
0375         /* ...and verify the command was successful. */
0376         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
0377 
0378         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
0379             e1000_release_phy_80003es2lan(hw);
0380             return -E1000_ERR_PHY;
0381         }
0382 
0383         usleep_range(200, 400);
0384 
0385         ret_val = e1000e_read_phy_reg_mdic(hw,
0386                            MAX_PHY_REG_ADDRESS & offset,
0387                            data);
0388 
0389         usleep_range(200, 400);
0390     } else {
0391         ret_val = e1000e_read_phy_reg_mdic(hw,
0392                            MAX_PHY_REG_ADDRESS & offset,
0393                            data);
0394     }
0395 
0396     e1000_release_phy_80003es2lan(hw);
0397 
0398     return ret_val;
0399 }
0400 
0401 /**
0402  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
0403  *  @hw: pointer to the HW structure
0404  *  @offset: offset of the register to read
0405  *  @data: value to write to the register
0406  *
0407  *  Write to the GG82563 PHY register.
0408  **/
0409 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
0410                            u32 offset, u16 data)
0411 {
0412     s32 ret_val;
0413     u32 page_select;
0414     u16 temp;
0415 
0416     ret_val = e1000_acquire_phy_80003es2lan(hw);
0417     if (ret_val)
0418         return ret_val;
0419 
0420     /* Select Configuration Page */
0421     if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
0422         page_select = GG82563_PHY_PAGE_SELECT;
0423     } else {
0424         /* Use Alternative Page Select register to access
0425          * registers 30 and 31
0426          */
0427         page_select = GG82563_PHY_PAGE_SELECT_ALT;
0428     }
0429 
0430     temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
0431     ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
0432     if (ret_val) {
0433         e1000_release_phy_80003es2lan(hw);
0434         return ret_val;
0435     }
0436 
0437     if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
0438         /* The "ready" bit in the MDIC register may be incorrectly set
0439          * before the device has completed the "Page Select" MDI
0440          * transaction.  So we wait 200us after each MDI command...
0441          */
0442         usleep_range(200, 400);
0443 
0444         /* ...and verify the command was successful. */
0445         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
0446 
0447         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
0448             e1000_release_phy_80003es2lan(hw);
0449             return -E1000_ERR_PHY;
0450         }
0451 
0452         usleep_range(200, 400);
0453 
0454         ret_val = e1000e_write_phy_reg_mdic(hw,
0455                             MAX_PHY_REG_ADDRESS &
0456                             offset, data);
0457 
0458         usleep_range(200, 400);
0459     } else {
0460         ret_val = e1000e_write_phy_reg_mdic(hw,
0461                             MAX_PHY_REG_ADDRESS &
0462                             offset, data);
0463     }
0464 
0465     e1000_release_phy_80003es2lan(hw);
0466 
0467     return ret_val;
0468 }
0469 
0470 /**
0471  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
0472  *  @hw: pointer to the HW structure
0473  *  @offset: offset of the register to read
0474  *  @words: number of words to write
0475  *  @data: buffer of data to write to the NVM
0476  *
0477  *  Write "words" of data to the ESB2 NVM.
0478  **/
0479 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
0480                        u16 words, u16 *data)
0481 {
0482     return e1000e_write_nvm_spi(hw, offset, words, data);
0483 }
0484 
0485 /**
0486  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
0487  *  @hw: pointer to the HW structure
0488  *
0489  *  Wait a specific amount of time for manageability processes to complete.
0490  *  This is a function pointer entry point called by the phy module.
0491  **/
0492 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
0493 {
0494     s32 timeout = PHY_CFG_TIMEOUT;
0495     u32 mask = E1000_NVM_CFG_DONE_PORT_0;
0496 
0497     if (hw->bus.func == 1)
0498         mask = E1000_NVM_CFG_DONE_PORT_1;
0499 
0500     while (timeout) {
0501         if (er32(EEMNGCTL) & mask)
0502             break;
0503         usleep_range(1000, 2000);
0504         timeout--;
0505     }
0506     if (!timeout) {
0507         e_dbg("MNG configuration cycle has not completed.\n");
0508         return -E1000_ERR_RESET;
0509     }
0510 
0511     return 0;
0512 }
0513 
0514 /**
0515  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
0516  *  @hw: pointer to the HW structure
0517  *
0518  *  Force the speed and duplex settings onto the PHY.  This is a
0519  *  function pointer entry point called by the phy module.
0520  **/
0521 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
0522 {
0523     s32 ret_val;
0524     u16 phy_data;
0525     bool link;
0526 
0527     /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
0528      * forced whenever speed and duplex are forced.
0529      */
0530     ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
0531     if (ret_val)
0532         return ret_val;
0533 
0534     phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
0535     ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
0536     if (ret_val)
0537         return ret_val;
0538 
0539     e_dbg("GG82563 PSCR: %X\n", phy_data);
0540 
0541     ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
0542     if (ret_val)
0543         return ret_val;
0544 
0545     e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
0546 
0547     /* Reset the phy to commit changes. */
0548     phy_data |= BMCR_RESET;
0549 
0550     ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
0551     if (ret_val)
0552         return ret_val;
0553 
0554     udelay(1);
0555 
0556     if (hw->phy.autoneg_wait_to_complete) {
0557         e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
0558 
0559         ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
0560                               100000, &link);
0561         if (ret_val)
0562             return ret_val;
0563 
0564         if (!link) {
0565             /* We didn't get link.
0566              * Reset the DSP and cross our fingers.
0567              */
0568             ret_val = e1000e_phy_reset_dsp(hw);
0569             if (ret_val)
0570                 return ret_val;
0571         }
0572 
0573         /* Try once more */
0574         ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
0575                               100000, &link);
0576         if (ret_val)
0577             return ret_val;
0578     }
0579 
0580     ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
0581     if (ret_val)
0582         return ret_val;
0583 
0584     /* Resetting the phy means we need to verify the TX_CLK corresponds
0585      * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
0586      */
0587     phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
0588     if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
0589         phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
0590     else
0591         phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
0592 
0593     /* In addition, we must re-enable CRS on Tx for both half and full
0594      * duplex.
0595      */
0596     phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
0597     ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
0598 
0599     return ret_val;
0600 }
0601 
0602 /**
0603  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
0604  *  @hw: pointer to the HW structure
0605  *
0606  *  Find the approximate cable length as measured by the GG82563 PHY.
0607  *  This is a function pointer entry point called by the phy module.
0608  **/
0609 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
0610 {
0611     struct e1000_phy_info *phy = &hw->phy;
0612     s32 ret_val;
0613     u16 phy_data, index;
0614 
0615     ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
0616     if (ret_val)
0617         return ret_val;
0618 
0619     index = phy_data & GG82563_DSPD_CABLE_LENGTH;
0620 
0621     if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
0622         return -E1000_ERR_PHY;
0623 
0624     phy->min_cable_length = e1000_gg82563_cable_length_table[index];
0625     phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
0626 
0627     phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
0628 
0629     return 0;
0630 }
0631 
0632 /**
0633  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
0634  *  @hw: pointer to the HW structure
0635  *  @speed: pointer to speed buffer
0636  *  @duplex: pointer to duplex buffer
0637  *
0638  *  Retrieve the current speed and duplex configuration.
0639  **/
0640 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
0641                           u16 *duplex)
0642 {
0643     s32 ret_val;
0644 
0645     if (hw->phy.media_type == e1000_media_type_copper) {
0646         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
0647         hw->phy.ops.cfg_on_link_up(hw);
0648     } else {
0649         ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
0650                                    speed,
0651                                    duplex);
0652     }
0653 
0654     return ret_val;
0655 }
0656 
0657 /**
0658  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
0659  *  @hw: pointer to the HW structure
0660  *
0661  *  Perform a global reset to the ESB2 controller.
0662  **/
0663 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
0664 {
0665     u32 ctrl;
0666     s32 ret_val;
0667     u16 kum_reg_data;
0668 
0669     /* Prevent the PCI-E bus from sticking if there is no TLP connection
0670      * on the last TLP read/write transaction when MAC is reset.
0671      */
0672     ret_val = e1000e_disable_pcie_master(hw);
0673     if (ret_val)
0674         e_dbg("PCI-E Master disable polling has failed.\n");
0675 
0676     e_dbg("Masking off all interrupts\n");
0677     ew32(IMC, 0xffffffff);
0678 
0679     ew32(RCTL, 0);
0680     ew32(TCTL, E1000_TCTL_PSP);
0681     e1e_flush();
0682 
0683     usleep_range(10000, 11000);
0684 
0685     ctrl = er32(CTRL);
0686 
0687     ret_val = e1000_acquire_phy_80003es2lan(hw);
0688     if (ret_val)
0689         return ret_val;
0690 
0691     e_dbg("Issuing a global reset to MAC\n");
0692     ew32(CTRL, ctrl | E1000_CTRL_RST);
0693     e1000_release_phy_80003es2lan(hw);
0694 
0695     /* Disable IBIST slave mode (far-end loopback) */
0696     ret_val =
0697         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
0698                         &kum_reg_data);
0699     if (!ret_val) {
0700         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
0701         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
0702                          E1000_KMRNCTRLSTA_INBAND_PARAM,
0703                          kum_reg_data);
0704         if (ret_val)
0705             e_dbg("Error disabling far-end loopback\n");
0706     } else {
0707         e_dbg("Error disabling far-end loopback\n");
0708     }
0709 
0710     ret_val = e1000e_get_auto_rd_done(hw);
0711     if (ret_val)
0712         /* We don't want to continue accessing MAC registers. */
0713         return ret_val;
0714 
0715     /* Clear any pending interrupt events. */
0716     ew32(IMC, 0xffffffff);
0717     er32(ICR);
0718 
0719     return e1000_check_alt_mac_addr_generic(hw);
0720 }
0721 
0722 /**
0723  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
0724  *  @hw: pointer to the HW structure
0725  *
0726  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
0727  **/
0728 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
0729 {
0730     struct e1000_mac_info *mac = &hw->mac;
0731     u32 reg_data;
0732     s32 ret_val;
0733     u16 kum_reg_data;
0734     u16 i;
0735 
0736     e1000_initialize_hw_bits_80003es2lan(hw);
0737 
0738     /* Initialize identification LED */
0739     ret_val = mac->ops.id_led_init(hw);
0740     /* An error is not fatal and we should not stop init due to this */
0741     if (ret_val)
0742         e_dbg("Error initializing identification LED\n");
0743 
0744     /* Disabling VLAN filtering */
0745     e_dbg("Initializing the IEEE VLAN\n");
0746     mac->ops.clear_vfta(hw);
0747 
0748     /* Setup the receive address. */
0749     e1000e_init_rx_addrs(hw, mac->rar_entry_count);
0750 
0751     /* Zero out the Multicast HASH table */
0752     e_dbg("Zeroing the MTA\n");
0753     for (i = 0; i < mac->mta_reg_count; i++)
0754         E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
0755 
0756     /* Setup link and flow control */
0757     ret_val = mac->ops.setup_link(hw);
0758     if (ret_val)
0759         return ret_val;
0760 
0761     /* Disable IBIST slave mode (far-end loopback) */
0762     ret_val =
0763         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
0764                         &kum_reg_data);
0765     if (!ret_val) {
0766         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
0767         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
0768                          E1000_KMRNCTRLSTA_INBAND_PARAM,
0769                          kum_reg_data);
0770         if (ret_val)
0771             e_dbg("Error disabling far-end loopback\n");
0772     } else {
0773         e_dbg("Error disabling far-end loopback\n");
0774     }
0775 
0776     /* Set the transmit descriptor write-back policy */
0777     reg_data = er32(TXDCTL(0));
0778     reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
0779             E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
0780     ew32(TXDCTL(0), reg_data);
0781 
0782     /* ...for both queues. */
0783     reg_data = er32(TXDCTL(1));
0784     reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
0785             E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
0786     ew32(TXDCTL(1), reg_data);
0787 
0788     /* Enable retransmit on late collisions */
0789     reg_data = er32(TCTL);
0790     reg_data |= E1000_TCTL_RTLC;
0791     ew32(TCTL, reg_data);
0792 
0793     /* Configure Gigabit Carry Extend Padding */
0794     reg_data = er32(TCTL_EXT);
0795     reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
0796     reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
0797     ew32(TCTL_EXT, reg_data);
0798 
0799     /* Configure Transmit Inter-Packet Gap */
0800     reg_data = er32(TIPG);
0801     reg_data &= ~E1000_TIPG_IPGT_MASK;
0802     reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
0803     ew32(TIPG, reg_data);
0804 
0805     reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
0806     reg_data &= ~0x00100000;
0807     E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
0808 
0809     /* default to true to enable the MDIC W/A */
0810     hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
0811 
0812     ret_val =
0813         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
0814                         E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
0815     if (!ret_val) {
0816         if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
0817             E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
0818             hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
0819     }
0820 
0821     /* Clear all of the statistics registers (clear on read).  It is
0822      * important that we do this after we have tried to establish link
0823      * because the symbol error count will increment wildly if there
0824      * is no link.
0825      */
0826     e1000_clear_hw_cntrs_80003es2lan(hw);
0827 
0828     return ret_val;
0829 }
0830 
0831 /**
0832  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
0833  *  @hw: pointer to the HW structure
0834  *
0835  *  Initializes required hardware-dependent bits needed for normal operation.
0836  **/
0837 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
0838 {
0839     u32 reg;
0840 
0841     /* Transmit Descriptor Control 0 */
0842     reg = er32(TXDCTL(0));
0843     reg |= BIT(22);
0844     ew32(TXDCTL(0), reg);
0845 
0846     /* Transmit Descriptor Control 1 */
0847     reg = er32(TXDCTL(1));
0848     reg |= BIT(22);
0849     ew32(TXDCTL(1), reg);
0850 
0851     /* Transmit Arbitration Control 0 */
0852     reg = er32(TARC(0));
0853     reg &= ~(0xF << 27);    /* 30:27 */
0854     if (hw->phy.media_type != e1000_media_type_copper)
0855         reg &= ~BIT(20);
0856     ew32(TARC(0), reg);
0857 
0858     /* Transmit Arbitration Control 1 */
0859     reg = er32(TARC(1));
0860     if (er32(TCTL) & E1000_TCTL_MULR)
0861         reg &= ~BIT(28);
0862     else
0863         reg |= BIT(28);
0864     ew32(TARC(1), reg);
0865 
0866     /* Disable IPv6 extension header parsing because some malformed
0867      * IPv6 headers can hang the Rx.
0868      */
0869     reg = er32(RFCTL);
0870     reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
0871     ew32(RFCTL, reg);
0872 }
0873 
0874 /**
0875  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
0876  *  @hw: pointer to the HW structure
0877  *
0878  *  Setup some GG82563 PHY registers for obtaining link
0879  **/
0880 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
0881 {
0882     struct e1000_phy_info *phy = &hw->phy;
0883     s32 ret_val;
0884     u32 reg;
0885     u16 data;
0886 
0887     ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
0888     if (ret_val)
0889         return ret_val;
0890 
0891     data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
0892     /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
0893     data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
0894 
0895     ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
0896     if (ret_val)
0897         return ret_val;
0898 
0899     /* Options:
0900      *   MDI/MDI-X = 0 (default)
0901      *   0 - Auto for all speeds
0902      *   1 - MDI mode
0903      *   2 - MDI-X mode
0904      *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
0905      */
0906     ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
0907     if (ret_val)
0908         return ret_val;
0909 
0910     data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
0911 
0912     switch (phy->mdix) {
0913     case 1:
0914         data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
0915         break;
0916     case 2:
0917         data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
0918         break;
0919     case 0:
0920     default:
0921         data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
0922         break;
0923     }
0924 
0925     /* Options:
0926      *   disable_polarity_correction = 0 (default)
0927      *       Automatic Correction for Reversed Cable Polarity
0928      *   0 - Disabled
0929      *   1 - Enabled
0930      */
0931     data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
0932     if (phy->disable_polarity_correction)
0933         data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
0934 
0935     ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
0936     if (ret_val)
0937         return ret_val;
0938 
0939     /* SW Reset the PHY so all changes take effect */
0940     ret_val = hw->phy.ops.commit(hw);
0941     if (ret_val) {
0942         e_dbg("Error Resetting the PHY\n");
0943         return ret_val;
0944     }
0945 
0946     /* Bypass Rx and Tx FIFO's */
0947     reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
0948     data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
0949         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
0950     ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
0951     if (ret_val)
0952         return ret_val;
0953 
0954     reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
0955     ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
0956     if (ret_val)
0957         return ret_val;
0958     data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
0959     ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
0960     if (ret_val)
0961         return ret_val;
0962 
0963     ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
0964     if (ret_val)
0965         return ret_val;
0966 
0967     data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
0968     ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
0969     if (ret_val)
0970         return ret_val;
0971 
0972     reg = er32(CTRL_EXT);
0973     reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
0974     ew32(CTRL_EXT, reg);
0975 
0976     ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
0977     if (ret_val)
0978         return ret_val;
0979 
0980     /* Do not init these registers when the HW is in IAMT mode, since the
0981      * firmware will have already initialized them.  We only initialize
0982      * them if the HW is not in IAMT mode.
0983      */
0984     if (!hw->mac.ops.check_mng_mode(hw)) {
0985         /* Enable Electrical Idle on the PHY */
0986         data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
0987         ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
0988         if (ret_val)
0989             return ret_val;
0990 
0991         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
0992         if (ret_val)
0993             return ret_val;
0994 
0995         data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
0996         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
0997         if (ret_val)
0998             return ret_val;
0999     }
1000 
1001     /* Workaround: Disable padding in Kumeran interface in the MAC
1002      * and in the PHY to avoid CRC errors.
1003      */
1004     ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1005     if (ret_val)
1006         return ret_val;
1007 
1008     data |= GG82563_ICR_DIS_PADDING;
1009     ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1010     if (ret_val)
1011         return ret_val;
1012 
1013     return 0;
1014 }
1015 
1016 /**
1017  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1018  *  @hw: pointer to the HW structure
1019  *
1020  *  Essentially a wrapper for setting up all things "copper" related.
1021  *  This is a function pointer entry point called by the mac module.
1022  **/
1023 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1024 {
1025     u32 ctrl;
1026     s32 ret_val;
1027     u16 reg_data;
1028 
1029     ctrl = er32(CTRL);
1030     ctrl |= E1000_CTRL_SLU;
1031     ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1032     ew32(CTRL, ctrl);
1033 
1034     /* Set the mac to wait the maximum time between each
1035      * iteration and increase the max iterations when
1036      * polling the phy; this fixes erroneous timeouts at 10Mbps.
1037      */
1038     ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1039                            0xFFFF);
1040     if (ret_val)
1041         return ret_val;
1042     ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1043                           &reg_data);
1044     if (ret_val)
1045         return ret_val;
1046     reg_data |= 0x3F;
1047     ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1048                            reg_data);
1049     if (ret_val)
1050         return ret_val;
1051     ret_val =
1052         e1000_read_kmrn_reg_80003es2lan(hw,
1053                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1054                         &reg_data);
1055     if (ret_val)
1056         return ret_val;
1057     reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1058     ret_val =
1059         e1000_write_kmrn_reg_80003es2lan(hw,
1060                          E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1061                          reg_data);
1062     if (ret_val)
1063         return ret_val;
1064 
1065     ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1066     if (ret_val)
1067         return ret_val;
1068 
1069     return e1000e_setup_copper_link(hw);
1070 }
1071 
1072 /**
1073  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1074  *  @hw: pointer to the HW structure
1075  *
1076  *  Configure the KMRN interface by applying last minute quirks for
1077  *  10/100 operation.
1078  **/
1079 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1080 {
1081     s32 ret_val = 0;
1082     u16 speed;
1083     u16 duplex;
1084 
1085     if (hw->phy.media_type == e1000_media_type_copper) {
1086         ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1087                                  &duplex);
1088         if (ret_val)
1089             return ret_val;
1090 
1091         if (speed == SPEED_1000)
1092             ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1093         else
1094             ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1095     }
1096 
1097     return ret_val;
1098 }
1099 
1100 /**
1101  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1102  *  @hw: pointer to the HW structure
1103  *  @duplex: current duplex setting
1104  *
1105  *  Configure the KMRN interface by applying last minute quirks for
1106  *  10/100 operation.
1107  **/
1108 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1109 {
1110     s32 ret_val;
1111     u32 tipg;
1112     u32 i = 0;
1113     u16 reg_data, reg_data2;
1114 
1115     reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1116     ret_val =
1117         e1000_write_kmrn_reg_80003es2lan(hw,
1118                          E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1119                          reg_data);
1120     if (ret_val)
1121         return ret_val;
1122 
1123     /* Configure Transmit Inter-Packet Gap */
1124     tipg = er32(TIPG);
1125     tipg &= ~E1000_TIPG_IPGT_MASK;
1126     tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1127     ew32(TIPG, tipg);
1128 
1129     do {
1130         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1131         if (ret_val)
1132             return ret_val;
1133 
1134         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1135         if (ret_val)
1136             return ret_val;
1137         i++;
1138     } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1139 
1140     if (duplex == HALF_DUPLEX)
1141         reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1142     else
1143         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1144 
1145     return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1146 }
1147 
1148 /**
1149  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1150  *  @hw: pointer to the HW structure
1151  *
1152  *  Configure the KMRN interface by applying last minute quirks for
1153  *  gigabit operation.
1154  **/
1155 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1156 {
1157     s32 ret_val;
1158     u16 reg_data, reg_data2;
1159     u32 tipg;
1160     u32 i = 0;
1161 
1162     reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1163     ret_val =
1164         e1000_write_kmrn_reg_80003es2lan(hw,
1165                          E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1166                          reg_data);
1167     if (ret_val)
1168         return ret_val;
1169 
1170     /* Configure Transmit Inter-Packet Gap */
1171     tipg = er32(TIPG);
1172     tipg &= ~E1000_TIPG_IPGT_MASK;
1173     tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1174     ew32(TIPG, tipg);
1175 
1176     do {
1177         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1178         if (ret_val)
1179             return ret_val;
1180 
1181         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1182         if (ret_val)
1183             return ret_val;
1184         i++;
1185     } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1186 
1187     reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1188 
1189     return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1190 }
1191 
1192 /**
1193  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1194  *  @hw: pointer to the HW structure
1195  *  @offset: register offset to be read
1196  *  @data: pointer to the read data
1197  *
1198  *  Acquire semaphore, then read the PHY register at offset
1199  *  using the kumeran interface.  The information retrieved is stored in data.
1200  *  Release the semaphore before exiting.
1201  **/
1202 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1203                        u16 *data)
1204 {
1205     u32 kmrnctrlsta;
1206     s32 ret_val;
1207 
1208     ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1209     if (ret_val)
1210         return ret_val;
1211 
1212     kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1213                E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1214     ew32(KMRNCTRLSTA, kmrnctrlsta);
1215     e1e_flush();
1216 
1217     udelay(2);
1218 
1219     kmrnctrlsta = er32(KMRNCTRLSTA);
1220     *data = (u16)kmrnctrlsta;
1221 
1222     e1000_release_mac_csr_80003es2lan(hw);
1223 
1224     return ret_val;
1225 }
1226 
1227 /**
1228  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1229  *  @hw: pointer to the HW structure
1230  *  @offset: register offset to write to
1231  *  @data: data to write at register offset
1232  *
1233  *  Acquire semaphore, then write the data to PHY register
1234  *  at the offset using the kumeran interface.  Release semaphore
1235  *  before exiting.
1236  **/
1237 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1238                         u16 data)
1239 {
1240     u32 kmrnctrlsta;
1241     s32 ret_val;
1242 
1243     ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1244     if (ret_val)
1245         return ret_val;
1246 
1247     kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1248                E1000_KMRNCTRLSTA_OFFSET) | data;
1249     ew32(KMRNCTRLSTA, kmrnctrlsta);
1250     e1e_flush();
1251 
1252     udelay(2);
1253 
1254     e1000_release_mac_csr_80003es2lan(hw);
1255 
1256     return ret_val;
1257 }
1258 
1259 /**
1260  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1261  *  @hw: pointer to the HW structure
1262  **/
1263 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1264 {
1265     s32 ret_val;
1266 
1267     /* If there's an alternate MAC address place it in RAR0
1268      * so that it will override the Si installed default perm
1269      * address.
1270      */
1271     ret_val = e1000_check_alt_mac_addr_generic(hw);
1272     if (ret_val)
1273         return ret_val;
1274 
1275     return e1000_read_mac_addr_generic(hw);
1276 }
1277 
1278 /**
1279  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1280  * @hw: pointer to the HW structure
1281  *
1282  * In the case of a PHY power down to save power, or to turn off link during a
1283  * driver unload, or wake on lan is not enabled, remove the link.
1284  **/
1285 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1286 {
1287     /* If the management interface is not enabled, then power down */
1288     if (!(hw->mac.ops.check_mng_mode(hw) ||
1289           hw->phy.ops.check_reset_block(hw)))
1290         e1000_power_down_phy_copper(hw);
1291 }
1292 
1293 /**
1294  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1295  *  @hw: pointer to the HW structure
1296  *
1297  *  Clears the hardware counters by reading the counter registers.
1298  **/
1299 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1300 {
1301     e1000e_clear_hw_cntrs_base(hw);
1302 
1303     er32(PRC64);
1304     er32(PRC127);
1305     er32(PRC255);
1306     er32(PRC511);
1307     er32(PRC1023);
1308     er32(PRC1522);
1309     er32(PTC64);
1310     er32(PTC127);
1311     er32(PTC255);
1312     er32(PTC511);
1313     er32(PTC1023);
1314     er32(PTC1522);
1315 
1316     er32(ALGNERRC);
1317     er32(RXERRC);
1318     er32(TNCRS);
1319     er32(CEXTERR);
1320     er32(TSCTC);
1321     er32(TSCTFC);
1322 
1323     er32(MGTPRC);
1324     er32(MGTPDC);
1325     er32(MGTPTC);
1326 
1327     er32(IAC);
1328     er32(ICRXOC);
1329 
1330     er32(ICRXPTC);
1331     er32(ICRXATC);
1332     er32(ICTXPTC);
1333     er32(ICTXATC);
1334     er32(ICTXQEC);
1335     er32(ICTXQMTC);
1336     er32(ICRXDMTC);
1337 }
1338 
1339 static const struct e1000_mac_operations es2_mac_ops = {
1340     .read_mac_addr      = e1000_read_mac_addr_80003es2lan,
1341     .id_led_init        = e1000e_id_led_init_generic,
1342     .blink_led      = e1000e_blink_led_generic,
1343     .check_mng_mode     = e1000e_check_mng_mode_generic,
1344     /* check_for_link dependent on media type */
1345     .cleanup_led        = e1000e_cleanup_led_generic,
1346     .clear_hw_cntrs     = e1000_clear_hw_cntrs_80003es2lan,
1347     .get_bus_info       = e1000e_get_bus_info_pcie,
1348     .set_lan_id     = e1000_set_lan_id_multi_port_pcie,
1349     .get_link_up_info   = e1000_get_link_up_info_80003es2lan,
1350     .led_on         = e1000e_led_on_generic,
1351     .led_off        = e1000e_led_off_generic,
1352     .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1353     .write_vfta     = e1000_write_vfta_generic,
1354     .clear_vfta     = e1000_clear_vfta_generic,
1355     .reset_hw       = e1000_reset_hw_80003es2lan,
1356     .init_hw        = e1000_init_hw_80003es2lan,
1357     .setup_link     = e1000e_setup_link_generic,
1358     /* setup_physical_interface dependent on media type */
1359     .setup_led      = e1000e_setup_led_generic,
1360     .config_collision_dist  = e1000e_config_collision_dist_generic,
1361     .rar_set        = e1000e_rar_set_generic,
1362     .rar_get_count      = e1000e_rar_get_count_generic,
1363 };
1364 
1365 static const struct e1000_phy_operations es2_phy_ops = {
1366     .acquire        = e1000_acquire_phy_80003es2lan,
1367     .check_polarity     = e1000_check_polarity_m88,
1368     .check_reset_block  = e1000e_check_reset_block_generic,
1369     .commit         = e1000e_phy_sw_reset,
1370     .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1371     .get_cfg_done       = e1000_get_cfg_done_80003es2lan,
1372     .get_cable_length   = e1000_get_cable_length_80003es2lan,
1373     .get_info       = e1000e_get_phy_info_m88,
1374     .read_reg       = e1000_read_phy_reg_gg82563_80003es2lan,
1375     .release        = e1000_release_phy_80003es2lan,
1376     .reset          = e1000e_phy_hw_reset_generic,
1377     .set_d0_lplu_state  = NULL,
1378     .set_d3_lplu_state  = e1000e_set_d3_lplu_state,
1379     .write_reg      = e1000_write_phy_reg_gg82563_80003es2lan,
1380     .cfg_on_link_up     = e1000_cfg_on_link_up_80003es2lan,
1381 };
1382 
1383 static const struct e1000_nvm_operations es2_nvm_ops = {
1384     .acquire        = e1000_acquire_nvm_80003es2lan,
1385     .read           = e1000e_read_nvm_eerd,
1386     .release        = e1000_release_nvm_80003es2lan,
1387     .reload         = e1000e_reload_nvm_generic,
1388     .update         = e1000e_update_nvm_checksum_generic,
1389     .valid_led_default  = e1000e_valid_led_default,
1390     .validate       = e1000e_validate_nvm_checksum_generic,
1391     .write          = e1000_write_nvm_80003es2lan,
1392 };
1393 
1394 const struct e1000_info e1000_es2_info = {
1395     .mac            = e1000_80003es2lan,
1396     .flags          = FLAG_HAS_HW_VLAN_FILTER
1397                   | FLAG_HAS_JUMBO_FRAMES
1398                   | FLAG_HAS_WOL
1399                   | FLAG_APME_IN_CTRL3
1400                   | FLAG_HAS_CTRLEXT_ON_LOAD
1401                   | FLAG_RX_NEEDS_RESTART /* errata */
1402                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1403                   | FLAG_APME_CHECK_PORT_B
1404                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1405     .flags2         = FLAG2_DMA_BURST,
1406     .pba            = 38,
1407     .max_hw_frame_size  = DEFAULT_JUMBO,
1408     .get_variants       = e1000_get_variants_80003es2lan,
1409     .mac_ops        = &es2_mac_ops,
1410     .phy_ops        = &es2_phy_ops,
1411     .nvm_ops        = &es2_nvm_ops,
1412 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!