intel/e1000/e1000_osdep.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2006 Intel Corporation. */
0003
0004 /* glue for the OS independent part of e1000
0005  * includes register access macros
0006  */
0007
0008 #ifndef _E1000_OSDEP_H_
0009 #define _E1000_OSDEP_H_
0010
0011 #include <asm/io.h>
0012
0013 #define CONFIG_RAM_BASE         0x60000
0014 #define GBE_CONFIG_OFFSET       0x0
0015
0016 #define GBE_CONFIG_RAM_BASE \
0017     ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
0018
0019 #define GBE_CONFIG_BASE_VIRT \
0020     ((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
0021
0022 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
0023     (iowrite16_rep(base + offset, data, count))
0024
0025 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
0026     (ioread16_rep(base + (offset << 1), data, count))
0027
0028 #define er32(reg)                           \
0029     (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543)     \
0030                    ? E1000_##reg : E1000_82542_##reg)))
0031
0032 #define ew32(reg, value)                        \
0033     (writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543)  \
0034                      ? E1000_##reg : E1000_82542_##reg))))
0035
0036 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
0037     writel((value), ((a)->hw_addr + \
0038         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
0039         ((offset) << 2))))
0040
0041 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
0042     readl((a)->hw_addr + \
0043         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
0044         ((offset) << 2)))
0045
0046 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
0047 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
0048
0049 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
0050     writew((value), ((a)->hw_addr + \
0051         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
0052         ((offset) << 1))))
0053
0054 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
0055     readw((a)->hw_addr + \
0056         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
0057         ((offset) << 1)))
0058
0059 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
0060     writeb((value), ((a)->hw_addr + \
0061         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
0062         (offset))))
0063
0064 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
0065     readb((a)->hw_addr + \
0066         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
0067         (offset)))
0068
0069 #define E1000_WRITE_FLUSH() er32(STATUS)
0070
0071 #define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
0072     writel((value), ((a)->flash_address + reg)))
0073
0074 #define E1000_READ_ICH_FLASH_REG(a, reg) ( \
0075     readl((a)->flash_address + reg))
0076
0077 #define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
0078     writew((value), ((a)->flash_address + reg)))
0079
0080 #define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
0081     readw((a)->flash_address + reg))
0082
0083 #endif /* _E1000_OSDEP_H_ */