ibm/emac/mal.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * drivers/net/ethernet/ibm/emac/mal.h
0004  *
0005  * Memory Access Layer (MAL) support
0006  *
0007  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
0008  *                <benh@kernel.crashing.org>
0009  *
0010  * Based on the arch/ppc version of the driver:
0011  *
0012  * Copyright (c) 2004, 2005 Zultys Technologies.
0013  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
0014  *
0015  * Based on original work by
0016  *      Armin Kuster <akuster@mvista.com>
0017  *      Copyright 2002 MontaVista Softare Inc.
0018  */
0019 #ifndef __IBM_NEWEMAC_MAL_H
0020 #define __IBM_NEWEMAC_MAL_H
0021
0022 /*
0023  * There are some variations on the MAL, we express them in this driver as
0024  * MAL Version 1 and 2 though that doesn't match any IBM terminology.
0025  *
0026  * We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
0027  * NP405H.
0028  *
0029  * We call MAL 2 the version in 440GP, 440GX, 440SP, 440SPE and Axon
0030  *
0031  * The driver expects a "version" property in the emac node containing
0032  * a number 1 or 2. New device-trees for EMAC capable platforms are thus
0033  * required to include that when porting to arch/powerpc.
0034  */
0035
0036 /* MALx DCR registers */
0037 #define MAL_CFG         0x00
0038 #define   MAL_CFG_SR        0x80000000
0039 #define   MAL_CFG_PLBB      0x00004000
0040 #define   MAL_CFG_OPBBL     0x00000080
0041 #define   MAL_CFG_EOPIE     0x00000004
0042 #define   MAL_CFG_LEA       0x00000002
0043 #define   MAL_CFG_SD        0x00000001
0044
0045 /* MAL V1 CFG bits */
0046 #define   MAL1_CFG_PLBP_MASK    0x00c00000
0047 #define   MAL1_CFG_PLBP_10  0x00800000
0048 #define   MAL1_CFG_GA       0x00200000
0049 #define   MAL1_CFG_OA       0x00100000
0050 #define   MAL1_CFG_PLBLE    0x00080000
0051 #define   MAL1_CFG_PLBT_MASK    0x00078000
0052 #define   MAL1_CFG_DEFAULT  (MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
0053
0054 /* MAL V2 CFG bits */
0055 #define   MAL2_CFG_RPP_MASK 0x00c00000
0056 #define   MAL2_CFG_RPP_10   0x00800000
0057 #define   MAL2_CFG_RMBS_MASK    0x00300000
0058 #define   MAL2_CFG_WPP_MASK 0x000c0000
0059 #define   MAL2_CFG_WPP_10   0x00080000
0060 #define   MAL2_CFG_WMBS_MASK    0x00030000
0061 #define   MAL2_CFG_PLBLE    0x00008000
0062 #define   MAL2_CFG_DEFAULT  (MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
0063                  MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
0064
0065 #define MAL_ESR         0x01
0066 #define   MAL_ESR_EVB       0x80000000
0067 #define   MAL_ESR_CIDT      0x40000000
0068 #define   MAL_ESR_CID_MASK  0x3e000000
0069 #define   MAL_ESR_CID_SHIFT 25
0070 #define   MAL_ESR_DE        0x00100000
0071 #define   MAL_ESR_OTE       0x00040000
0072 #define   MAL_ESR_OSE       0x00020000
0073 #define   MAL_ESR_PEIN      0x00010000
0074 #define   MAL_ESR_DEI       0x00000010
0075 #define   MAL_ESR_OTEI      0x00000004
0076 #define   MAL_ESR_OSEI      0x00000002
0077 #define   MAL_ESR_PBEI      0x00000001
0078
0079 /* MAL V1 ESR bits */
0080 #define   MAL1_ESR_ONE      0x00080000
0081 #define   MAL1_ESR_ONEI     0x00000008
0082
0083 /* MAL V2 ESR bits */
0084 #define   MAL2_ESR_PTE      0x00800000
0085 #define   MAL2_ESR_PRE      0x00400000
0086 #define   MAL2_ESR_PWE      0x00200000
0087 #define   MAL2_ESR_PTEI     0x00000080
0088 #define   MAL2_ESR_PREI     0x00000040
0089 #define   MAL2_ESR_PWEI     0x00000020
0090
0091
0092 #define MAL_IER         0x02
0093 /* MAL IER bits */
0094 #define   MAL_IER_DE        0x00000010
0095 #define   MAL_IER_OTE       0x00000004
0096 #define   MAL_IER_OE        0x00000002
0097 #define   MAL_IER_PE        0x00000001
0098
0099 /* PLB read/write/timeout errors */
0100 #define   MAL_IER_PTE       0x00000080
0101 #define   MAL_IER_PRE       0x00000040
0102 #define   MAL_IER_PWE       0x00000020
0103
0104 #define   MAL_IER_SOC_EVENTS    (MAL_IER_PTE | MAL_IER_PRE | MAL_IER_PWE)
0105 #define   MAL_IER_EVENTS    (MAL_IER_SOC_EVENTS | MAL_IER_DE | \
0106                  MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
0107
0108 #define MAL_TXCASR      0x04
0109 #define MAL_TXCARR      0x05
0110 #define MAL_TXEOBISR        0x06
0111 #define MAL_TXDEIR      0x07
0112 #define MAL_RXCASR      0x10
0113 #define MAL_RXCARR      0x11
0114 #define MAL_RXEOBISR        0x12
0115 #define MAL_RXDEIR      0x13
0116 #define MAL_TXCTPR(n)       ((n) + 0x20)
0117 #define MAL_RXCTPR(n)       ((n) + 0x40)
0118 #define MAL_RCBS(n)     ((n) + 0x60)
0119
0120 /* In reality MAL can handle TX buffers up to 4095 bytes long,
0121  * but this isn't a good round number :)         --ebs
0122  */
0123 #define MAL_MAX_TX_SIZE     4080
0124 #define MAL_MAX_RX_SIZE     4080
0125
0126 static inline int mal_rx_size(int len)
0127 {
0128     len = (len + 0xf) & ~0xf;
0129     return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
0130 }
0131
0132 static inline int mal_tx_chunks(int len)
0133 {
0134     return DIV_ROUND_UP(len, MAL_MAX_TX_SIZE);
0135 }
0136
0137 #define MAL_CHAN_MASK(n)    (0x80000000 >> (n))
0138
0139 /* MAL Buffer Descriptor structure */
0140 struct mal_descriptor {
0141     u16 ctrl;       /* MAL / Commac status control bits */
0142     u16 data_len;       /* Max length is 4K-1 (12 bits)     */
0143     u32 data_ptr;       /* pointer to actual data buffer    */
0144 };
0145
0146 /* the following defines are for the MadMAL status and control registers. */
0147 /* MADMAL transmit and receive status/control bits  */
0148 #define MAL_RX_CTRL_EMPTY   0x8000
0149 #define MAL_RX_CTRL_WRAP    0x4000
0150 #define MAL_RX_CTRL_CM      0x2000
0151 #define MAL_RX_CTRL_LAST    0x1000
0152 #define MAL_RX_CTRL_FIRST   0x0800
0153 #define MAL_RX_CTRL_INTR    0x0400
0154 #define MAL_RX_CTRL_SINGLE  (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
0155 #define MAL_IS_SINGLE_RX(ctrl)  (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
0156
0157 #define MAL_TX_CTRL_READY   0x8000
0158 #define MAL_TX_CTRL_WRAP    0x4000
0159 #define MAL_TX_CTRL_CM      0x2000
0160 #define MAL_TX_CTRL_LAST    0x1000
0161 #define MAL_TX_CTRL_INTR    0x0400
0162
0163 struct mal_commac_ops {
0164     void    (*poll_tx) (void *dev);
0165     int (*poll_rx) (void *dev, int budget);
0166     int (*peek_rx) (void *dev);
0167     void    (*rxde) (void *dev);
0168 };
0169
0170 struct mal_commac {
0171     struct mal_commac_ops   *ops;
0172     void            *dev;
0173     struct list_head    poll_list;
0174     long            flags;
0175 #define MAL_COMMAC_RX_STOPPED       0
0176 #define MAL_COMMAC_POLL_DISABLED    1
0177     u32         tx_chan_mask;
0178     u32         rx_chan_mask;
0179     struct list_head    list;
0180 };
0181
0182 struct mal_instance {
0183     int         version;
0184     dcr_host_t      dcr_host;
0185
0186     int         num_tx_chans;   /* Number of TX channels */
0187     int         num_rx_chans;   /* Number of RX channels */
0188     int             txeob_irq;  /* TX End Of Buffer IRQ  */
0189     int             rxeob_irq;  /* RX End Of Buffer IRQ  */
0190     int         txde_irq;   /* TX Descriptor Error IRQ */
0191     int         rxde_irq;   /* RX Descriptor Error IRQ */
0192     int         serr_irq;   /* MAL System Error IRQ    */
0193
0194     struct list_head    poll_list;
0195     struct napi_struct  napi;
0196
0197     struct list_head    list;
0198     u32         tx_chan_mask;
0199     u32         rx_chan_mask;
0200
0201     dma_addr_t      bd_dma;
0202     struct mal_descriptor   *bd_virt;
0203
0204     struct platform_device  *ofdev;
0205     int         index;
0206     spinlock_t      lock;
0207
0208     struct net_device   dummy_dev;
0209
0210     unsigned int features;
0211 };
0212
0213 static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
0214 {
0215     return dcr_read(mal->dcr_host, reg);
0216 }
0217
0218 static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
0219 {
0220     dcr_write(mal->dcr_host, reg, val);
0221 }
0222
0223 /* Features of various MAL implementations */
0224
0225 /* Set if you have interrupt coalescing and you have to clear the SDR
0226  * register for TXEOB and RXEOB interrupts to work
0227  */
0228 #define MAL_FTR_CLEAR_ICINTSTAT 0x00000001
0229
0230 /* Set if your MAL has SERR, TXDE, and RXDE OR'd into a single UIC
0231  * interrupt
0232  */
0233 #define MAL_FTR_COMMON_ERR_INT  0x00000002
0234
0235 enum {
0236     MAL_FTRS_ALWAYS = 0,
0237
0238     MAL_FTRS_POSSIBLE =
0239 #ifdef CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT
0240         MAL_FTR_CLEAR_ICINTSTAT |
0241 #endif
0242 #ifdef CONFIG_IBM_EMAC_MAL_COMMON_ERR
0243         MAL_FTR_COMMON_ERR_INT |
0244 #endif
0245         0,
0246 };
0247
0248 static inline int mal_has_feature(struct mal_instance *dev,
0249         unsigned long feature)
0250 {
0251     return (MAL_FTRS_ALWAYS & feature) ||
0252         (MAL_FTRS_POSSIBLE & dev->features & feature);
0253 }
0254
0255 /* Register MAL devices */
0256 int mal_init(void);
0257 void mal_exit(void);
0258
0259 int mal_register_commac(struct mal_instance *mal,
0260             struct mal_commac *commac);
0261 void mal_unregister_commac(struct mal_instance *mal,
0262                struct mal_commac *commac);
0263 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
0264
0265 /* Returns BD ring offset for a particular channel
0266    (in 'struct mal_descriptor' elements)
0267 */
0268 int mal_tx_bd_offset(struct mal_instance *mal, int channel);
0269 int mal_rx_bd_offset(struct mal_instance *mal, int channel);
0270
0271 void mal_enable_tx_channel(struct mal_instance *mal, int channel);
0272 void mal_disable_tx_channel(struct mal_instance *mal, int channel);
0273 void mal_enable_rx_channel(struct mal_instance *mal, int channel);
0274 void mal_disable_rx_channel(struct mal_instance *mal, int channel);
0275
0276 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
0277 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
0278
0279 /* Add/remove EMAC to/from MAL polling list */
0280 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
0281 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
0282
0283 /* Ethtool MAL registers */
0284 struct mal_regs {
0285     u32 tx_count;
0286     u32 rx_count;
0287
0288     u32 cfg;
0289     u32 esr;
0290     u32 ier;
0291     u32 tx_casr;
0292     u32 tx_carr;
0293     u32 tx_eobisr;
0294     u32 tx_deir;
0295     u32 rx_casr;
0296     u32 rx_carr;
0297     u32 rx_eobisr;
0298     u32 rx_deir;
0299     u32 tx_ctpr[32];
0300     u32 rx_ctpr[32];
0301     u32 rcbs[32];
0302 };
0303
0304 int mal_get_regs_len(struct mal_instance *mal);
0305 void *mal_dump_regs(struct mal_instance *mal, void *buf);
0306
0307 #endif /* __IBM_NEWEMAC_MAL_H */