ibm/emac/core.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * drivers/net/ethernet/ibm/emac/core.c
0004  *
0005  * Driver for PowerPC 4xx on-chip ethernet controller.
0006  *
0007  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
0008  *                <benh@kernel.crashing.org>
0009  *
0010  * Based on the arch/ppc version of the driver:
0011  *
0012  * Copyright (c) 2004, 2005 Zultys Technologies.
0013  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
0014  *
0015  * Based on original work by
0016  *  Matt Porter <mporter@kernel.crashing.org>
0017  *  (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
0018  *      Armin Kuster <akuster@mvista.com>
0019  *  Johnnie Peters <jpeters@mvista.com>
0020  */
0021
0022 #include <linux/module.h>
0023 #include <linux/sched.h>
0024 #include <linux/string.h>
0025 #include <linux/errno.h>
0026 #include <linux/delay.h>
0027 #include <linux/types.h>
0028 #include <linux/pci.h>
0029 #include <linux/etherdevice.h>
0030 #include <linux/skbuff.h>
0031 #include <linux/crc32.h>
0032 #include <linux/ethtool.h>
0033 #include <linux/mii.h>
0034 #include <linux/bitops.h>
0035 #include <linux/workqueue.h>
0036 #include <linux/of.h>
0037 #include <linux/of_address.h>
0038 #include <linux/of_irq.h>
0039 #include <linux/of_net.h>
0040 #include <linux/of_mdio.h>
0041 #include <linux/platform_device.h>
0042 #include <linux/slab.h>
0043
0044 #include <asm/processor.h>
0045 #include <asm/io.h>
0046 #include <asm/dma.h>
0047 #include <linux/uaccess.h>
0048 #include <asm/dcr.h>
0049 #include <asm/dcr-regs.h>
0050
0051 #include "core.h"
0052
0053 /*
0054  * Lack of dma_unmap_???? calls is intentional.
0055  *
0056  * API-correct usage requires additional support state information to be
0057  * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
0058  * EMAC design (e.g. TX buffer passed from network stack can be split into
0059  * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
0060  * maintaining such information will add additional overhead.
0061  * Current DMA API implementation for 4xx processors only ensures cache coherency
0062  * and dma_unmap_???? routines are empty and are likely to stay this way.
0063  * I decided to omit dma_unmap_??? calls because I don't want to add additional
0064  * complexity just for the sake of following some abstract API, when it doesn't
0065  * add any real benefit to the driver. I understand that this decision maybe
0066  * controversial, but I really tried to make code API-correct and efficient
0067  * at the same time and didn't come up with code I liked :(.                --ebs
0068  */
0069
0070 #define DRV_NAME        "emac"
0071 #define DRV_VERSION     "3.54"
0072 #define DRV_DESC        "PPC 4xx OCP EMAC driver"
0073
0074 MODULE_DESCRIPTION(DRV_DESC);
0075 MODULE_AUTHOR
0076     ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
0077 MODULE_LICENSE("GPL");
0078
0079 /* minimum number of free TX descriptors required to wake up TX process */
0080 #define EMAC_TX_WAKEUP_THRESH       (NUM_TX_BUFF / 4)
0081
0082 /* If packet size is less than this number, we allocate small skb and copy packet
0083  * contents into it instead of just sending original big skb up
0084  */
0085 #define EMAC_RX_COPY_THRESH     CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
0086
0087 /* Since multiple EMACs share MDIO lines in various ways, we need
0088  * to avoid re-using the same PHY ID in cases where the arch didn't
0089  * setup precise phy_map entries
0090  *
0091  * XXX This is something that needs to be reworked as we can have multiple
0092  * EMAC "sets" (multiple ASICs containing several EMACs) though we can
0093  * probably require in that case to have explicit PHY IDs in the device-tree
0094  */
0095 static u32 busy_phy_map;
0096 static DEFINE_MUTEX(emac_phy_map_lock);
0097
0098 /* This is the wait queue used to wait on any event related to probe, that
0099  * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
0100  */
0101 static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
0102
0103 /* Having stable interface names is a doomed idea. However, it would be nice
0104  * if we didn't have completely random interface names at boot too :-) It's
0105  * just a matter of making everybody's life easier. Since we are doing
0106  * threaded probing, it's a bit harder though. The base idea here is that
0107  * we make up a list of all emacs in the device-tree before we register the
0108  * driver. Every emac will then wait for the previous one in the list to
0109  * initialize before itself. We should also keep that list ordered by
0110  * cell_index.
0111  * That list is only 4 entries long, meaning that additional EMACs don't
0112  * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
0113  */
0114
0115 #define EMAC_BOOT_LIST_SIZE 4
0116 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
0117
0118 /* How long should I wait for dependent devices ? */
0119 #define EMAC_PROBE_DEP_TIMEOUT  (HZ * 5)
0120
0121 /* I don't want to litter system log with timeout errors
0122  * when we have brain-damaged PHY.
0123  */
0124 static inline void emac_report_timeout_error(struct emac_instance *dev,
0125                          const char *error)
0126 {
0127     if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
0128                   EMAC_FTR_460EX_PHY_CLK_FIX |
0129                   EMAC_FTR_440EP_PHY_CLK_FIX))
0130         DBG(dev, "%s" NL, error);
0131     else if (net_ratelimit())
0132         printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
0133 }
0134
0135 /* EMAC PHY clock workaround:
0136  * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
0137  * which allows controlling each EMAC clock
0138  */
0139 static inline void emac_rx_clk_tx(struct emac_instance *dev)
0140 {
0141 #ifdef CONFIG_PPC_DCR_NATIVE
0142     if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
0143         dcri_clrset(SDR0, SDR0_MFR,
0144                 0, SDR0_MFR_ECS >> dev->cell_index);
0145 #endif
0146 }
0147
0148 static inline void emac_rx_clk_default(struct emac_instance *dev)
0149 {
0150 #ifdef CONFIG_PPC_DCR_NATIVE
0151     if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
0152         dcri_clrset(SDR0, SDR0_MFR,
0153                 SDR0_MFR_ECS >> dev->cell_index, 0);
0154 #endif
0155 }
0156
0157 /* PHY polling intervals */
0158 #define PHY_POLL_LINK_ON    HZ
0159 #define PHY_POLL_LINK_OFF   (HZ / 5)
0160
0161 /* Graceful stop timeouts in us.
0162  * We should allow up to 1 frame time (full-duplex, ignoring collisions)
0163  */
0164 #define STOP_TIMEOUT_10     1230
0165 #define STOP_TIMEOUT_100    124
0166 #define STOP_TIMEOUT_1000   13
0167 #define STOP_TIMEOUT_1000_JUMBO 73
0168
0169 static unsigned char default_mcast_addr[] = {
0170     0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
0171 };
0172
0173 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
0174 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
0175     "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
0176     "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
0177     "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
0178     "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
0179     "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
0180     "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
0181     "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
0182     "rx_bad_packet", "rx_runt_packet", "rx_short_event",
0183     "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
0184     "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
0185     "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
0186     "tx_bd_excessive_collisions", "tx_bd_late_collision",
0187     "tx_bd_multple_collisions", "tx_bd_single_collision",
0188     "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
0189     "tx_errors"
0190 };
0191
0192 static irqreturn_t emac_irq(int irq, void *dev_instance);
0193 static void emac_clean_tx_ring(struct emac_instance *dev);
0194 static void __emac_set_multicast_list(struct emac_instance *dev);
0195
0196 static inline int emac_phy_supports_gige(int phy_mode)
0197 {
0198     return  phy_interface_mode_is_rgmii(phy_mode) ||
0199         phy_mode == PHY_INTERFACE_MODE_GMII ||
0200         phy_mode == PHY_INTERFACE_MODE_SGMII ||
0201         phy_mode == PHY_INTERFACE_MODE_TBI ||
0202         phy_mode == PHY_INTERFACE_MODE_RTBI;
0203 }
0204
0205 static inline int emac_phy_gpcs(int phy_mode)
0206 {
0207     return  phy_mode == PHY_INTERFACE_MODE_SGMII ||
0208         phy_mode == PHY_INTERFACE_MODE_TBI ||
0209         phy_mode == PHY_INTERFACE_MODE_RTBI;
0210 }
0211
0212 static inline void emac_tx_enable(struct emac_instance *dev)
0213 {
0214     struct emac_regs __iomem *p = dev->emacp;
0215     u32 r;
0216
0217     DBG(dev, "tx_enable" NL);
0218
0219     r = in_be32(&p->mr0);
0220     if (!(r & EMAC_MR0_TXE))
0221         out_be32(&p->mr0, r | EMAC_MR0_TXE);
0222 }
0223
0224 static void emac_tx_disable(struct emac_instance *dev)
0225 {
0226     struct emac_regs __iomem *p = dev->emacp;
0227     u32 r;
0228
0229     DBG(dev, "tx_disable" NL);
0230
0231     r = in_be32(&p->mr0);
0232     if (r & EMAC_MR0_TXE) {
0233         int n = dev->stop_timeout;
0234         out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
0235         while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
0236             udelay(1);
0237             --n;
0238         }
0239         if (unlikely(!n))
0240             emac_report_timeout_error(dev, "TX disable timeout");
0241     }
0242 }
0243
0244 static void emac_rx_enable(struct emac_instance *dev)
0245 {
0246     struct emac_regs __iomem *p = dev->emacp;
0247     u32 r;
0248
0249     if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
0250         goto out;
0251
0252     DBG(dev, "rx_enable" NL);
0253
0254     r = in_be32(&p->mr0);
0255     if (!(r & EMAC_MR0_RXE)) {
0256         if (unlikely(!(r & EMAC_MR0_RXI))) {
0257             /* Wait if previous async disable is still in progress */
0258             int n = dev->stop_timeout;
0259             while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
0260                 udelay(1);
0261                 --n;
0262             }
0263             if (unlikely(!n))
0264                 emac_report_timeout_error(dev,
0265                               "RX disable timeout");
0266         }
0267         out_be32(&p->mr0, r | EMAC_MR0_RXE);
0268     }
0269  out:
0270     ;
0271 }
0272
0273 static void emac_rx_disable(struct emac_instance *dev)
0274 {
0275     struct emac_regs __iomem *p = dev->emacp;
0276     u32 r;
0277
0278     DBG(dev, "rx_disable" NL);
0279
0280     r = in_be32(&p->mr0);
0281     if (r & EMAC_MR0_RXE) {
0282         int n = dev->stop_timeout;
0283         out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
0284         while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
0285             udelay(1);
0286             --n;
0287         }
0288         if (unlikely(!n))
0289             emac_report_timeout_error(dev, "RX disable timeout");
0290     }
0291 }
0292
0293 static inline void emac_netif_stop(struct emac_instance *dev)
0294 {
0295     netif_tx_lock_bh(dev->ndev);
0296     netif_addr_lock(dev->ndev);
0297     dev->no_mcast = 1;
0298     netif_addr_unlock(dev->ndev);
0299     netif_tx_unlock_bh(dev->ndev);
0300     netif_trans_update(dev->ndev);  /* prevent tx timeout */
0301     mal_poll_disable(dev->mal, &dev->commac);
0302     netif_tx_disable(dev->ndev);
0303 }
0304
0305 static inline void emac_netif_start(struct emac_instance *dev)
0306 {
0307     netif_tx_lock_bh(dev->ndev);
0308     netif_addr_lock(dev->ndev);
0309     dev->no_mcast = 0;
0310     if (dev->mcast_pending && netif_running(dev->ndev))
0311         __emac_set_multicast_list(dev);
0312     netif_addr_unlock(dev->ndev);
0313     netif_tx_unlock_bh(dev->ndev);
0314
0315     netif_wake_queue(dev->ndev);
0316
0317     /* NOTE: unconditional netif_wake_queue is only appropriate
0318      * so long as all callers are assured to have free tx slots
0319      * (taken from tg3... though the case where that is wrong is
0320      *  not terribly harmful)
0321      */
0322     mal_poll_enable(dev->mal, &dev->commac);
0323 }
0324
0325 static inline void emac_rx_disable_async(struct emac_instance *dev)
0326 {
0327     struct emac_regs __iomem *p = dev->emacp;
0328     u32 r;
0329
0330     DBG(dev, "rx_disable_async" NL);
0331
0332     r = in_be32(&p->mr0);
0333     if (r & EMAC_MR0_RXE)
0334         out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
0335 }
0336
0337 static int emac_reset(struct emac_instance *dev)
0338 {
0339     struct emac_regs __iomem *p = dev->emacp;
0340     int n = 20;
0341     bool __maybe_unused try_internal_clock = false;
0342
0343     DBG(dev, "reset" NL);
0344
0345     if (!dev->reset_failed) {
0346         /* 40x erratum suggests stopping RX channel before reset,
0347          * we stop TX as well
0348          */
0349         emac_rx_disable(dev);
0350         emac_tx_disable(dev);
0351     }
0352
0353 #ifdef CONFIG_PPC_DCR_NATIVE
0354 do_retry:
0355     /*
0356      * PPC460EX/GT Embedded Processor Advanced User's Manual
0357      * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
0358      * Note: The PHY must provide a TX Clk in order to perform a soft reset
0359      * of the EMAC. If none is present, select the internal clock
0360      * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
0361      * After a soft reset, select the external clock.
0362      *
0363      * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
0364      * ethernet cable is not attached. This causes the reset to timeout
0365      * and the PHY detection code in emac_init_phy() is unable to
0366      * communicate and detect the AR8035-A PHY. As a result, the emac
0367      * driver bails out early and the user has no ethernet.
0368      * In order to stay compatible with existing configurations, the
0369      * driver will temporarily switch to the internal clock, after
0370      * the first reset fails.
0371      */
0372     if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
0373         if (try_internal_clock || (dev->phy_address == 0xffffffff &&
0374                        dev->phy_map == 0xffffffff)) {
0375             /* No PHY: select internal loop clock before reset */
0376             dcri_clrset(SDR0, SDR0_ETH_CFG,
0377                     0, SDR0_ETH_CFG_ECS << dev->cell_index);
0378         } else {
0379             /* PHY present: select external clock before reset */
0380             dcri_clrset(SDR0, SDR0_ETH_CFG,
0381                     SDR0_ETH_CFG_ECS << dev->cell_index, 0);
0382         }
0383     }
0384 #endif
0385
0386     out_be32(&p->mr0, EMAC_MR0_SRST);
0387     while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
0388         --n;
0389
0390 #ifdef CONFIG_PPC_DCR_NATIVE
0391     if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
0392         if (!n && !try_internal_clock) {
0393             /* first attempt has timed out. */
0394             n = 20;
0395             try_internal_clock = true;
0396             goto do_retry;
0397         }
0398
0399         if (try_internal_clock || (dev->phy_address == 0xffffffff &&
0400                        dev->phy_map == 0xffffffff)) {
0401             /* No PHY: restore external clock source after reset */
0402             dcri_clrset(SDR0, SDR0_ETH_CFG,
0403                     SDR0_ETH_CFG_ECS << dev->cell_index, 0);
0404         }
0405     }
0406 #endif
0407
0408     if (n) {
0409         dev->reset_failed = 0;
0410         return 0;
0411     } else {
0412         emac_report_timeout_error(dev, "reset timeout");
0413         dev->reset_failed = 1;
0414         return -ETIMEDOUT;
0415     }
0416 }
0417
0418 static void emac_hash_mc(struct emac_instance *dev)
0419 {
0420     const int regs = EMAC_XAHT_REGS(dev);
0421     u32 *gaht_base = emac_gaht_base(dev);
0422     u32 gaht_temp[EMAC_XAHT_MAX_REGS];
0423     struct netdev_hw_addr *ha;
0424     int i;
0425
0426     DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
0427
0428     memset(gaht_temp, 0, sizeof (gaht_temp));
0429
0430     netdev_for_each_mc_addr(ha, dev->ndev) {
0431         int slot, reg, mask;
0432         DBG2(dev, "mc %pM" NL, ha->addr);
0433
0434         slot = EMAC_XAHT_CRC_TO_SLOT(dev,
0435                          ether_crc(ETH_ALEN, ha->addr));
0436         reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
0437         mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
0438
0439         gaht_temp[reg] |= mask;
0440     }
0441
0442     for (i = 0; i < regs; i++)
0443         out_be32(gaht_base + i, gaht_temp[i]);
0444 }
0445
0446 static inline u32 emac_iff2rmr(struct net_device *ndev)
0447 {
0448     struct emac_instance *dev = netdev_priv(ndev);
0449     u32 r;
0450
0451     r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
0452
0453     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0454         r |= EMAC4_RMR_BASE;
0455     else
0456         r |= EMAC_RMR_BASE;
0457
0458     if (ndev->flags & IFF_PROMISC)
0459         r |= EMAC_RMR_PME;
0460     else if (ndev->flags & IFF_ALLMULTI ||
0461              (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
0462         r |= EMAC_RMR_PMME;
0463     else if (!netdev_mc_empty(ndev))
0464         r |= EMAC_RMR_MAE;
0465
0466     if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
0467         r &= ~EMAC4_RMR_MJS_MASK;
0468         r |= EMAC4_RMR_MJS(ndev->mtu);
0469     }
0470
0471     return r;
0472 }
0473
0474 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
0475 {
0476     u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
0477
0478     DBG2(dev, "__emac_calc_base_mr1" NL);
0479
0480     switch(tx_size) {
0481     case 2048:
0482         ret |= EMAC_MR1_TFS_2K;
0483         break;
0484     default:
0485         printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
0486                dev->ndev->name, tx_size);
0487     }
0488
0489     switch(rx_size) {
0490     case 16384:
0491         ret |= EMAC_MR1_RFS_16K;
0492         break;
0493     case 4096:
0494         ret |= EMAC_MR1_RFS_4K;
0495         break;
0496     default:
0497         printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
0498                dev->ndev->name, rx_size);
0499     }
0500
0501     return ret;
0502 }
0503
0504 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
0505 {
0506     u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
0507         EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
0508
0509     DBG2(dev, "__emac4_calc_base_mr1" NL);
0510
0511     switch(tx_size) {
0512     case 16384:
0513         ret |= EMAC4_MR1_TFS_16K;
0514         break;
0515     case 8192:
0516         ret |= EMAC4_MR1_TFS_8K;
0517         break;
0518     case 4096:
0519         ret |= EMAC4_MR1_TFS_4K;
0520         break;
0521     case 2048:
0522         ret |= EMAC4_MR1_TFS_2K;
0523         break;
0524     default:
0525         printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
0526                dev->ndev->name, tx_size);
0527     }
0528
0529     switch(rx_size) {
0530     case 16384:
0531         ret |= EMAC4_MR1_RFS_16K;
0532         break;
0533     case 8192:
0534         ret |= EMAC4_MR1_RFS_8K;
0535         break;
0536     case 4096:
0537         ret |= EMAC4_MR1_RFS_4K;
0538         break;
0539     case 2048:
0540         ret |= EMAC4_MR1_RFS_2K;
0541         break;
0542     default:
0543         printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
0544                dev->ndev->name, rx_size);
0545     }
0546
0547     return ret;
0548 }
0549
0550 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
0551 {
0552     return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
0553         __emac4_calc_base_mr1(dev, tx_size, rx_size) :
0554         __emac_calc_base_mr1(dev, tx_size, rx_size);
0555 }
0556
0557 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
0558 {
0559     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0560         return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
0561     else
0562         return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
0563 }
0564
0565 static inline u32 emac_calc_rwmr(struct emac_instance *dev,
0566                  unsigned int low, unsigned int high)
0567 {
0568     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0569         return (low << 22) | ( (high & 0x3ff) << 6);
0570     else
0571         return (low << 23) | ( (high & 0x1ff) << 7);
0572 }
0573
0574 static int emac_configure(struct emac_instance *dev)
0575 {
0576     struct emac_regs __iomem *p = dev->emacp;
0577     struct net_device *ndev = dev->ndev;
0578     int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
0579     u32 r, mr1 = 0;
0580
0581     DBG(dev, "configure" NL);
0582
0583     if (!link) {
0584         out_be32(&p->mr1, in_be32(&p->mr1)
0585              | EMAC_MR1_FDE | EMAC_MR1_ILE);
0586         udelay(100);
0587     } else if (emac_reset(dev) < 0)
0588         return -ETIMEDOUT;
0589
0590     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
0591         tah_reset(dev->tah_dev);
0592
0593     DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
0594         link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
0595
0596     /* Default fifo sizes */
0597     tx_size = dev->tx_fifo_size;
0598     rx_size = dev->rx_fifo_size;
0599
0600     /* No link, force loopback */
0601     if (!link)
0602         mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
0603
0604     /* Check for full duplex */
0605     else if (dev->phy.duplex == DUPLEX_FULL)
0606         mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
0607
0608     /* Adjust fifo sizes, mr1 and timeouts based on link speed */
0609     dev->stop_timeout = STOP_TIMEOUT_10;
0610     switch (dev->phy.speed) {
0611     case SPEED_1000:
0612         if (emac_phy_gpcs(dev->phy.mode)) {
0613             mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
0614                 (dev->phy.gpcs_address != 0xffffffff) ?
0615                  dev->phy.gpcs_address : dev->phy.address);
0616
0617             /* Put some arbitrary OUI, Manuf & Rev IDs so we can
0618              * identify this GPCS PHY later.
0619              */
0620             out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
0621         } else
0622             mr1 |= EMAC_MR1_MF_1000;
0623
0624         /* Extended fifo sizes */
0625         tx_size = dev->tx_fifo_size_gige;
0626         rx_size = dev->rx_fifo_size_gige;
0627
0628         if (dev->ndev->mtu > ETH_DATA_LEN) {
0629             if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0630                 mr1 |= EMAC4_MR1_JPSM;
0631             else
0632                 mr1 |= EMAC_MR1_JPSM;
0633             dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
0634         } else
0635             dev->stop_timeout = STOP_TIMEOUT_1000;
0636         break;
0637     case SPEED_100:
0638         mr1 |= EMAC_MR1_MF_100;
0639         dev->stop_timeout = STOP_TIMEOUT_100;
0640         break;
0641     default: /* make gcc happy */
0642         break;
0643     }
0644
0645     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
0646         rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
0647                 dev->phy.speed);
0648     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
0649         zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
0650
0651     /* on 40x erratum forces us to NOT use integrated flow control,
0652      * let's hope it works on 44x ;)
0653      */
0654     if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
0655         dev->phy.duplex == DUPLEX_FULL) {
0656         if (dev->phy.pause)
0657             mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
0658         else if (dev->phy.asym_pause)
0659             mr1 |= EMAC_MR1_APP;
0660     }
0661
0662     /* Add base settings & fifo sizes & program MR1 */
0663     mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
0664     out_be32(&p->mr1, mr1);
0665
0666     /* Set individual MAC address */
0667     out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
0668     out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
0669          (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
0670          ndev->dev_addr[5]);
0671
0672     /* VLAN Tag Protocol ID */
0673     out_be32(&p->vtpid, 0x8100);
0674
0675     /* Receive mode register */
0676     r = emac_iff2rmr(ndev);
0677     if (r & EMAC_RMR_MAE)
0678         emac_hash_mc(dev);
0679     out_be32(&p->rmr, r);
0680
0681     /* FIFOs thresholds */
0682     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0683         r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
0684                    tx_size / 2 / dev->fifo_entry_size);
0685     else
0686         r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
0687                   tx_size / 2 / dev->fifo_entry_size);
0688     out_be32(&p->tmr1, r);
0689     out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
0690
0691     /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
0692        there should be still enough space in FIFO to allow the our link
0693        partner time to process this frame and also time to send PAUSE
0694        frame itself.
0695
0696        Here is the worst case scenario for the RX FIFO "headroom"
0697        (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
0698
0699        1) One maximum-length frame on TX                    1522 bytes
0700        2) One PAUSE frame time                                64 bytes
0701        3) PAUSE frame decode time allowance                   64 bytes
0702        4) One maximum-length frame on RX                    1522 bytes
0703        5) Round-trip propagation delay of the link (100Mb)    15 bytes
0704        ----------
0705        3187 bytes
0706
0707        I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
0708        low-water mark  to RX_FIFO_SIZE / 8 (512 bytes)
0709      */
0710     r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
0711                rx_size / 4 / dev->fifo_entry_size);
0712     out_be32(&p->rwmr, r);
0713
0714     /* Set PAUSE timer to the maximum */
0715     out_be32(&p->ptr, 0xffff);
0716
0717     /* IRQ sources */
0718     r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
0719         EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
0720         EMAC_ISR_IRE | EMAC_ISR_TE;
0721     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0722         r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
0723                           EMAC4_ISR_RXOE | */;
0724     out_be32(&p->iser,  r);
0725
0726     /* We need to take GPCS PHY out of isolate mode after EMAC reset */
0727     if (emac_phy_gpcs(dev->phy.mode)) {
0728         if (dev->phy.gpcs_address != 0xffffffff)
0729             emac_mii_reset_gpcs(&dev->phy);
0730         else
0731             emac_mii_reset_phy(&dev->phy);
0732     }
0733
0734     return 0;
0735 }
0736
0737 static void emac_reinitialize(struct emac_instance *dev)
0738 {
0739     DBG(dev, "reinitialize" NL);
0740
0741     emac_netif_stop(dev);
0742     if (!emac_configure(dev)) {
0743         emac_tx_enable(dev);
0744         emac_rx_enable(dev);
0745     }
0746     emac_netif_start(dev);
0747 }
0748
0749 static void emac_full_tx_reset(struct emac_instance *dev)
0750 {
0751     DBG(dev, "full_tx_reset" NL);
0752
0753     emac_tx_disable(dev);
0754     mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
0755     emac_clean_tx_ring(dev);
0756     dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
0757
0758     emac_configure(dev);
0759
0760     mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
0761     emac_tx_enable(dev);
0762     emac_rx_enable(dev);
0763 }
0764
0765 static void emac_reset_work(struct work_struct *work)
0766 {
0767     struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
0768
0769     DBG(dev, "reset_work" NL);
0770
0771     mutex_lock(&dev->link_lock);
0772     if (dev->opened) {
0773         emac_netif_stop(dev);
0774         emac_full_tx_reset(dev);
0775         emac_netif_start(dev);
0776     }
0777     mutex_unlock(&dev->link_lock);
0778 }
0779
0780 static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
0781 {
0782     struct emac_instance *dev = netdev_priv(ndev);
0783
0784     DBG(dev, "tx_timeout" NL);
0785
0786     schedule_work(&dev->reset_work);
0787 }
0788
0789
0790 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
0791 {
0792     int done = !!(stacr & EMAC_STACR_OC);
0793
0794     if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
0795         done = !done;
0796
0797     return done;
0798 };
0799
0800 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
0801 {
0802     struct emac_regs __iomem *p = dev->emacp;
0803     u32 r = 0;
0804     int n, err = -ETIMEDOUT;
0805
0806     mutex_lock(&dev->mdio_lock);
0807
0808     DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
0809
0810     /* Enable proper MDIO port */
0811     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
0812         zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
0813     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
0814         rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
0815
0816     /* Wait for management interface to become idle */
0817     n = 20;
0818     while (!emac_phy_done(dev, in_be32(&p->stacr))) {
0819         udelay(1);
0820         if (!--n) {
0821             DBG2(dev, " -> timeout wait idle\n");
0822             goto bail;
0823         }
0824     }
0825
0826     /* Issue read command */
0827     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0828         r = EMAC4_STACR_BASE(dev->opb_bus_freq);
0829     else
0830         r = EMAC_STACR_BASE(dev->opb_bus_freq);
0831     if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
0832         r |= EMAC_STACR_OC;
0833     if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
0834         r |= EMACX_STACR_STAC_READ;
0835     else
0836         r |= EMAC_STACR_STAC_READ;
0837     r |= (reg & EMAC_STACR_PRA_MASK)
0838         | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
0839     out_be32(&p->stacr, r);
0840
0841     /* Wait for read to complete */
0842     n = 200;
0843     while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
0844         udelay(1);
0845         if (!--n) {
0846             DBG2(dev, " -> timeout wait complete\n");
0847             goto bail;
0848         }
0849     }
0850
0851     if (unlikely(r & EMAC_STACR_PHYE)) {
0852         DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
0853         err = -EREMOTEIO;
0854         goto bail;
0855     }
0856
0857     r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
0858
0859     DBG2(dev, "mdio_read -> %04x" NL, r);
0860     err = 0;
0861  bail:
0862     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
0863         rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
0864     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
0865         zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
0866     mutex_unlock(&dev->mdio_lock);
0867
0868     return err == 0 ? r : err;
0869 }
0870
0871 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
0872                   u16 val)
0873 {
0874     struct emac_regs __iomem *p = dev->emacp;
0875     u32 r = 0;
0876     int n;
0877
0878     mutex_lock(&dev->mdio_lock);
0879
0880     DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
0881
0882     /* Enable proper MDIO port */
0883     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
0884         zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
0885     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
0886         rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
0887
0888     /* Wait for management interface to be idle */
0889     n = 20;
0890     while (!emac_phy_done(dev, in_be32(&p->stacr))) {
0891         udelay(1);
0892         if (!--n) {
0893             DBG2(dev, " -> timeout wait idle\n");
0894             goto bail;
0895         }
0896     }
0897
0898     /* Issue write command */
0899     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
0900         r = EMAC4_STACR_BASE(dev->opb_bus_freq);
0901     else
0902         r = EMAC_STACR_BASE(dev->opb_bus_freq);
0903     if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
0904         r |= EMAC_STACR_OC;
0905     if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
0906         r |= EMACX_STACR_STAC_WRITE;
0907     else
0908         r |= EMAC_STACR_STAC_WRITE;
0909     r |= (reg & EMAC_STACR_PRA_MASK) |
0910         ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
0911         (val << EMAC_STACR_PHYD_SHIFT);
0912     out_be32(&p->stacr, r);
0913
0914     /* Wait for write to complete */
0915     n = 200;
0916     while (!emac_phy_done(dev, in_be32(&p->stacr))) {
0917         udelay(1);
0918         if (!--n) {
0919             DBG2(dev, " -> timeout wait complete\n");
0920             goto bail;
0921         }
0922     }
0923  bail:
0924     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
0925         rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
0926     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
0927         zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
0928     mutex_unlock(&dev->mdio_lock);
0929 }
0930
0931 static int emac_mdio_read(struct net_device *ndev, int id, int reg)
0932 {
0933     struct emac_instance *dev = netdev_priv(ndev);
0934     int res;
0935
0936     res = __emac_mdio_read((dev->mdio_instance &&
0937                 dev->phy.gpcs_address != id) ?
0938                 dev->mdio_instance : dev,
0939                    (u8) id, (u8) reg);
0940     return res;
0941 }
0942
0943 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
0944 {
0945     struct emac_instance *dev = netdev_priv(ndev);
0946
0947     __emac_mdio_write((dev->mdio_instance &&
0948                dev->phy.gpcs_address != id) ?
0949                dev->mdio_instance : dev,
0950               (u8) id, (u8) reg, (u16) val);
0951 }
0952
0953 /* Tx lock BH */
0954 static void __emac_set_multicast_list(struct emac_instance *dev)
0955 {
0956     struct emac_regs __iomem *p = dev->emacp;
0957     u32 rmr = emac_iff2rmr(dev->ndev);
0958
0959     DBG(dev, "__multicast %08x" NL, rmr);
0960
0961     /* I decided to relax register access rules here to avoid
0962      * full EMAC reset.
0963      *
0964      * There is a real problem with EMAC4 core if we use MWSW_001 bit
0965      * in MR1 register and do a full EMAC reset.
0966      * One TX BD status update is delayed and, after EMAC reset, it
0967      * never happens, resulting in TX hung (it'll be recovered by TX
0968      * timeout handler eventually, but this is just gross).
0969      * So we either have to do full TX reset or try to cheat here :)
0970      *
0971      * The only required change is to RX mode register, so I *think* all
0972      * we need is just to stop RX channel. This seems to work on all
0973      * tested SoCs.                                                --ebs
0974      *
0975      * If we need the full reset, we might just trigger the workqueue
0976      * and do it async... a bit nasty but should work --BenH
0977      */
0978     dev->mcast_pending = 0;
0979     emac_rx_disable(dev);
0980     if (rmr & EMAC_RMR_MAE)
0981         emac_hash_mc(dev);
0982     out_be32(&p->rmr, rmr);
0983     emac_rx_enable(dev);
0984 }
0985
0986 /* Tx lock BH */
0987 static void emac_set_multicast_list(struct net_device *ndev)
0988 {
0989     struct emac_instance *dev = netdev_priv(ndev);
0990
0991     DBG(dev, "multicast" NL);
0992
0993     BUG_ON(!netif_running(dev->ndev));
0994
0995     if (dev->no_mcast) {
0996         dev->mcast_pending = 1;
0997         return;
0998     }
0999
1000     mutex_lock(&dev->link_lock);
1001     __emac_set_multicast_list(dev);
1002     mutex_unlock(&dev->link_lock);
1003 }
1004
1005 static int emac_set_mac_address(struct net_device *ndev, void *sa)
1006 {
1007     struct emac_instance *dev = netdev_priv(ndev);
1008     struct sockaddr *addr = sa;
1009     struct emac_regs __iomem *p = dev->emacp;
1010
1011     if (!is_valid_ether_addr(addr->sa_data))
1012            return -EADDRNOTAVAIL;
1013
1014     mutex_lock(&dev->link_lock);
1015
1016     eth_hw_addr_set(ndev, addr->sa_data);
1017
1018     emac_rx_disable(dev);
1019     emac_tx_disable(dev);
1020     out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
1021     out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
1022         (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
1023         ndev->dev_addr[5]);
1024     emac_tx_enable(dev);
1025     emac_rx_enable(dev);
1026
1027     mutex_unlock(&dev->link_lock);
1028
1029     return 0;
1030 }
1031
1032 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1033 {
1034     int rx_sync_size = emac_rx_sync_size(new_mtu);
1035     int rx_skb_size = emac_rx_skb_size(new_mtu);
1036     int i, ret = 0;
1037     int mr1_jumbo_bit_change = 0;
1038
1039     mutex_lock(&dev->link_lock);
1040     emac_netif_stop(dev);
1041     emac_rx_disable(dev);
1042     mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1043
1044     if (dev->rx_sg_skb) {
1045         ++dev->estats.rx_dropped_resize;
1046         dev_kfree_skb(dev->rx_sg_skb);
1047         dev->rx_sg_skb = NULL;
1048     }
1049
1050     /* Make a first pass over RX ring and mark BDs ready, dropping
1051      * non-processed packets on the way. We need this as a separate pass
1052      * to simplify error recovery in the case of allocation failure later.
1053      */
1054     for (i = 0; i < NUM_RX_BUFF; ++i) {
1055         if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1056             ++dev->estats.rx_dropped_resize;
1057
1058         dev->rx_desc[i].data_len = 0;
1059         dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1060             (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1061     }
1062
1063     /* Reallocate RX ring only if bigger skb buffers are required */
1064     if (rx_skb_size <= dev->rx_skb_size)
1065         goto skip;
1066
1067     /* Second pass, allocate new skbs */
1068     for (i = 0; i < NUM_RX_BUFF; ++i) {
1069         struct sk_buff *skb;
1070
1071         skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size);
1072         if (!skb) {
1073             ret = -ENOMEM;
1074             goto oom;
1075         }
1076
1077         BUG_ON(!dev->rx_skb[i]);
1078         dev_kfree_skb(dev->rx_skb[i]);
1079
1080         dev->rx_desc[i].data_ptr =
1081             dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1082                    rx_sync_size, DMA_FROM_DEVICE)
1083                    + NET_IP_ALIGN;
1084         dev->rx_skb[i] = skb;
1085     }
1086  skip:
1087     /* Check if we need to change "Jumbo" bit in MR1 */
1088     if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1089         mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1090                 (dev->ndev->mtu > ETH_DATA_LEN);
1091     } else {
1092         mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1093                 (dev->ndev->mtu > ETH_DATA_LEN);
1094     }
1095
1096     if (mr1_jumbo_bit_change) {
1097         /* This is to prevent starting RX channel in emac_rx_enable() */
1098         set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1099
1100         dev->ndev->mtu = new_mtu;
1101         emac_full_tx_reset(dev);
1102     }
1103
1104     mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1105  oom:
1106     /* Restart RX */
1107     clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1108     dev->rx_slot = 0;
1109     mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1110     emac_rx_enable(dev);
1111     emac_netif_start(dev);
1112     mutex_unlock(&dev->link_lock);
1113
1114     return ret;
1115 }
1116
1117 /* Process ctx, rtnl_lock semaphore */
1118 static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1119 {
1120     struct emac_instance *dev = netdev_priv(ndev);
1121     int ret = 0;
1122
1123     DBG(dev, "change_mtu(%d)" NL, new_mtu);
1124
1125     if (netif_running(ndev)) {
1126         /* Check if we really need to reinitialize RX ring */
1127         if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1128             ret = emac_resize_rx_ring(dev, new_mtu);
1129     }
1130
1131     if (!ret) {
1132         ndev->mtu = new_mtu;
1133         dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1134         dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1135     }
1136
1137     return ret;
1138 }
1139
1140 static void emac_clean_tx_ring(struct emac_instance *dev)
1141 {
1142     int i;
1143
1144     for (i = 0; i < NUM_TX_BUFF; ++i) {
1145         if (dev->tx_skb[i]) {
1146             dev_kfree_skb(dev->tx_skb[i]);
1147             dev->tx_skb[i] = NULL;
1148             if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1149                 ++dev->estats.tx_dropped;
1150         }
1151         dev->tx_desc[i].ctrl = 0;
1152         dev->tx_desc[i].data_ptr = 0;
1153     }
1154 }
1155
1156 static void emac_clean_rx_ring(struct emac_instance *dev)
1157 {
1158     int i;
1159
1160     for (i = 0; i < NUM_RX_BUFF; ++i)
1161         if (dev->rx_skb[i]) {
1162             dev->rx_desc[i].ctrl = 0;
1163             dev_kfree_skb(dev->rx_skb[i]);
1164             dev->rx_skb[i] = NULL;
1165             dev->rx_desc[i].data_ptr = 0;
1166         }
1167
1168     if (dev->rx_sg_skb) {
1169         dev_kfree_skb(dev->rx_sg_skb);
1170         dev->rx_sg_skb = NULL;
1171     }
1172 }
1173
1174 static int
1175 __emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot)
1176 {
1177     if (unlikely(!skb))
1178         return -ENOMEM;
1179
1180     dev->rx_skb[slot] = skb;
1181     dev->rx_desc[slot].data_len = 0;
1182
1183     dev->rx_desc[slot].data_ptr =
1184         dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1185                dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN;
1186     wmb();
1187     dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1188         (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1189
1190     return 0;
1191 }
1192
1193 static int
1194 emac_alloc_rx_skb(struct emac_instance *dev, int slot)
1195 {
1196     struct sk_buff *skb;
1197
1198     skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size,
1199                       GFP_KERNEL);
1200
1201     return __emac_prepare_rx_skb(skb, dev, slot);
1202 }
1203
1204 static int
1205 emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot)
1206 {
1207     struct sk_buff *skb;
1208
1209     skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size);
1210
1211     return __emac_prepare_rx_skb(skb, dev, slot);
1212 }
1213
1214 static void emac_print_link_status(struct emac_instance *dev)
1215 {
1216     if (netif_carrier_ok(dev->ndev))
1217         printk(KERN_INFO "%s: link is up, %d %s%s\n",
1218                dev->ndev->name, dev->phy.speed,
1219                dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1220                dev->phy.pause ? ", pause enabled" :
1221                dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1222     else
1223         printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1224 }
1225
1226 /* Process ctx, rtnl_lock semaphore */
1227 static int emac_open(struct net_device *ndev)
1228 {
1229     struct emac_instance *dev = netdev_priv(ndev);
1230     int err, i;
1231
1232     DBG(dev, "open" NL);
1233
1234     /* Setup error IRQ handler */
1235     err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1236     if (err) {
1237         printk(KERN_ERR "%s: failed to request IRQ %d\n",
1238                ndev->name, dev->emac_irq);
1239         return err;
1240     }
1241
1242     /* Allocate RX ring */
1243     for (i = 0; i < NUM_RX_BUFF; ++i)
1244         if (emac_alloc_rx_skb(dev, i)) {
1245             printk(KERN_ERR "%s: failed to allocate RX ring\n",
1246                    ndev->name);
1247             goto oom;
1248         }
1249
1250     dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1251     clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1252     dev->rx_sg_skb = NULL;
1253
1254     mutex_lock(&dev->link_lock);
1255     dev->opened = 1;
1256
1257     /* Start PHY polling now.
1258      */
1259     if (dev->phy.address >= 0) {
1260         int link_poll_interval;
1261         if (dev->phy.def->ops->poll_link(&dev->phy)) {
1262             dev->phy.def->ops->read_link(&dev->phy);
1263             emac_rx_clk_default(dev);
1264             netif_carrier_on(dev->ndev);
1265             link_poll_interval = PHY_POLL_LINK_ON;
1266         } else {
1267             emac_rx_clk_tx(dev);
1268             netif_carrier_off(dev->ndev);
1269             link_poll_interval = PHY_POLL_LINK_OFF;
1270         }
1271         dev->link_polling = 1;
1272         wmb();
1273         schedule_delayed_work(&dev->link_work, link_poll_interval);
1274         emac_print_link_status(dev);
1275     } else
1276         netif_carrier_on(dev->ndev);
1277
1278     /* Required for Pause packet support in EMAC */
1279     dev_mc_add_global(ndev, default_mcast_addr);
1280
1281     emac_configure(dev);
1282     mal_poll_add(dev->mal, &dev->commac);
1283     mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1284     mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1285     mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1286     emac_tx_enable(dev);
1287     emac_rx_enable(dev);
1288     emac_netif_start(dev);
1289
1290     mutex_unlock(&dev->link_lock);
1291
1292     return 0;
1293  oom:
1294     emac_clean_rx_ring(dev);
1295     free_irq(dev->emac_irq, dev);
1296
1297     return -ENOMEM;
1298 }
1299
1300 /* BHs disabled */
1301 #if 0
1302 static int emac_link_differs(struct emac_instance *dev)
1303 {
1304     u32 r = in_be32(&dev->emacp->mr1);
1305
1306     int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1307     int speed, pause, asym_pause;
1308
1309     if (r & EMAC_MR1_MF_1000)
1310         speed = SPEED_1000;
1311     else if (r & EMAC_MR1_MF_100)
1312         speed = SPEED_100;
1313     else
1314         speed = SPEED_10;
1315
1316     switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1317     case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1318         pause = 1;
1319         asym_pause = 0;
1320         break;
1321     case EMAC_MR1_APP:
1322         pause = 0;
1323         asym_pause = 1;
1324         break;
1325     default:
1326         pause = asym_pause = 0;
1327     }
1328     return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1329         pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1330 }
1331 #endif
1332
1333 static void emac_link_timer(struct work_struct *work)
1334 {
1335     struct emac_instance *dev =
1336         container_of(to_delayed_work(work),
1337                  struct emac_instance, link_work);
1338     int link_poll_interval;
1339
1340     mutex_lock(&dev->link_lock);
1341     DBG2(dev, "link timer" NL);
1342
1343     if (!dev->opened)
1344         goto bail;
1345
1346     if (dev->phy.def->ops->poll_link(&dev->phy)) {
1347         if (!netif_carrier_ok(dev->ndev)) {
1348             emac_rx_clk_default(dev);
1349             /* Get new link parameters */
1350             dev->phy.def->ops->read_link(&dev->phy);
1351
1352             netif_carrier_on(dev->ndev);
1353             emac_netif_stop(dev);
1354             emac_full_tx_reset(dev);
1355             emac_netif_start(dev);
1356             emac_print_link_status(dev);
1357         }
1358         link_poll_interval = PHY_POLL_LINK_ON;
1359     } else {
1360         if (netif_carrier_ok(dev->ndev)) {
1361             emac_rx_clk_tx(dev);
1362             netif_carrier_off(dev->ndev);
1363             netif_tx_disable(dev->ndev);
1364             emac_reinitialize(dev);
1365             emac_print_link_status(dev);
1366         }
1367         link_poll_interval = PHY_POLL_LINK_OFF;
1368     }
1369     schedule_delayed_work(&dev->link_work, link_poll_interval);
1370  bail:
1371     mutex_unlock(&dev->link_lock);
1372 }
1373
1374 static void emac_force_link_update(struct emac_instance *dev)
1375 {
1376     netif_carrier_off(dev->ndev);
1377     smp_rmb();
1378     if (dev->link_polling) {
1379         cancel_delayed_work_sync(&dev->link_work);
1380         if (dev->link_polling)
1381             schedule_delayed_work(&dev->link_work,  PHY_POLL_LINK_OFF);
1382     }
1383 }
1384
1385 /* Process ctx, rtnl_lock semaphore */
1386 static int emac_close(struct net_device *ndev)
1387 {
1388     struct emac_instance *dev = netdev_priv(ndev);
1389
1390     DBG(dev, "close" NL);
1391
1392     if (dev->phy.address >= 0) {
1393         dev->link_polling = 0;
1394         cancel_delayed_work_sync(&dev->link_work);
1395     }
1396     mutex_lock(&dev->link_lock);
1397     emac_netif_stop(dev);
1398     dev->opened = 0;
1399     mutex_unlock(&dev->link_lock);
1400
1401     emac_rx_disable(dev);
1402     emac_tx_disable(dev);
1403     mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1404     mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1405     mal_poll_del(dev->mal, &dev->commac);
1406
1407     emac_clean_tx_ring(dev);
1408     emac_clean_rx_ring(dev);
1409
1410     free_irq(dev->emac_irq, dev);
1411
1412     netif_carrier_off(ndev);
1413
1414     return 0;
1415 }
1416
1417 static inline u16 emac_tx_csum(struct emac_instance *dev,
1418                    struct sk_buff *skb)
1419 {
1420     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1421         (skb->ip_summed == CHECKSUM_PARTIAL)) {
1422         ++dev->stats.tx_packets_csum;
1423         return EMAC_TX_CTRL_TAH_CSUM;
1424     }
1425     return 0;
1426 }
1427
1428 static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len)
1429 {
1430     struct emac_regs __iomem *p = dev->emacp;
1431     struct net_device *ndev = dev->ndev;
1432
1433     /* Send the packet out. If the if makes a significant perf
1434      * difference, then we can store the TMR0 value in "dev"
1435      * instead
1436      */
1437     if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1438         out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1439     else
1440         out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1441
1442     if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1443         netif_stop_queue(ndev);
1444         DBG2(dev, "stopped TX queue" NL);
1445     }
1446
1447     netif_trans_update(ndev);
1448     ++dev->stats.tx_packets;
1449     dev->stats.tx_bytes += len;
1450
1451     return NETDEV_TX_OK;
1452 }
1453
1454 /* Tx lock BH */
1455 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1456 {
1457     struct emac_instance *dev = netdev_priv(ndev);
1458     unsigned int len = skb->len;
1459     int slot;
1460
1461     u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1462         MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1463
1464     slot = dev->tx_slot++;
1465     if (dev->tx_slot == NUM_TX_BUFF) {
1466         dev->tx_slot = 0;
1467         ctrl |= MAL_TX_CTRL_WRAP;
1468     }
1469
1470     DBG2(dev, "xmit(%u) %d" NL, len, slot);
1471
1472     dev->tx_skb[slot] = skb;
1473     dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1474                              skb->data, len,
1475                              DMA_TO_DEVICE);
1476     dev->tx_desc[slot].data_len = (u16) len;
1477     wmb();
1478     dev->tx_desc[slot].ctrl = ctrl;
1479
1480     return emac_xmit_finish(dev, len);
1481 }
1482
1483 static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1484                   u32 pd, int len, int last, u16 base_ctrl)
1485 {
1486     while (1) {
1487         u16 ctrl = base_ctrl;
1488         int chunk = min(len, MAL_MAX_TX_SIZE);
1489         len -= chunk;
1490
1491         slot = (slot + 1) % NUM_TX_BUFF;
1492
1493         if (last && !len)
1494             ctrl |= MAL_TX_CTRL_LAST;
1495         if (slot == NUM_TX_BUFF - 1)
1496             ctrl |= MAL_TX_CTRL_WRAP;
1497
1498         dev->tx_skb[slot] = NULL;
1499         dev->tx_desc[slot].data_ptr = pd;
1500         dev->tx_desc[slot].data_len = (u16) chunk;
1501         dev->tx_desc[slot].ctrl = ctrl;
1502         ++dev->tx_cnt;
1503
1504         if (!len)
1505             break;
1506
1507         pd += chunk;
1508     }
1509     return slot;
1510 }
1511
1512 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1513 static netdev_tx_t
1514 emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1515 {
1516     struct emac_instance *dev = netdev_priv(ndev);
1517     int nr_frags = skb_shinfo(skb)->nr_frags;
1518     int len = skb->len, chunk;
1519     int slot, i;
1520     u16 ctrl;
1521     u32 pd;
1522
1523     /* This is common "fast" path */
1524     if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1525         return emac_start_xmit(skb, ndev);
1526
1527     len -= skb->data_len;
1528
1529     /* Note, this is only an *estimation*, we can still run out of empty
1530      * slots because of the additional fragmentation into
1531      * MAL_MAX_TX_SIZE-sized chunks
1532      */
1533     if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1534         goto stop_queue;
1535
1536     ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1537         emac_tx_csum(dev, skb);
1538     slot = dev->tx_slot;
1539
1540     /* skb data */
1541     dev->tx_skb[slot] = NULL;
1542     chunk = min(len, MAL_MAX_TX_SIZE);
1543     dev->tx_desc[slot].data_ptr = pd =
1544         dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1545     dev->tx_desc[slot].data_len = (u16) chunk;
1546     len -= chunk;
1547     if (unlikely(len))
1548         slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1549                        ctrl);
1550     /* skb fragments */
1551     for (i = 0; i < nr_frags; ++i) {
1552         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1553         len = skb_frag_size(frag);
1554
1555         if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1556             goto undo_frame;
1557
1558         pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1559                       DMA_TO_DEVICE);
1560
1561         slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1562                        ctrl);
1563     }
1564
1565     DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1566
1567     /* Attach skb to the last slot so we don't release it too early */
1568     dev->tx_skb[slot] = skb;
1569
1570     /* Send the packet out */
1571     if (dev->tx_slot == NUM_TX_BUFF - 1)
1572         ctrl |= MAL_TX_CTRL_WRAP;
1573     wmb();
1574     dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1575     dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1576
1577     return emac_xmit_finish(dev, skb->len);
1578
1579  undo_frame:
1580     /* Well, too bad. Our previous estimation was overly optimistic.
1581      * Undo everything.
1582      */
1583     while (slot != dev->tx_slot) {
1584         dev->tx_desc[slot].ctrl = 0;
1585         --dev->tx_cnt;
1586         if (--slot < 0)
1587             slot = NUM_TX_BUFF - 1;
1588     }
1589     ++dev->estats.tx_undo;
1590
1591  stop_queue:
1592     netif_stop_queue(ndev);
1593     DBG2(dev, "stopped TX queue" NL);
1594     return NETDEV_TX_BUSY;
1595 }
1596
1597 /* Tx lock BHs */
1598 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1599 {
1600     struct emac_error_stats *st = &dev->estats;
1601
1602     DBG(dev, "BD TX error %04x" NL, ctrl);
1603
1604     ++st->tx_bd_errors;
1605     if (ctrl & EMAC_TX_ST_BFCS)
1606         ++st->tx_bd_bad_fcs;
1607     if (ctrl & EMAC_TX_ST_LCS)
1608         ++st->tx_bd_carrier_loss;
1609     if (ctrl & EMAC_TX_ST_ED)
1610         ++st->tx_bd_excessive_deferral;
1611     if (ctrl & EMAC_TX_ST_EC)
1612         ++st->tx_bd_excessive_collisions;
1613     if (ctrl & EMAC_TX_ST_LC)
1614         ++st->tx_bd_late_collision;
1615     if (ctrl & EMAC_TX_ST_MC)
1616         ++st->tx_bd_multple_collisions;
1617     if (ctrl & EMAC_TX_ST_SC)
1618         ++st->tx_bd_single_collision;
1619     if (ctrl & EMAC_TX_ST_UR)
1620         ++st->tx_bd_underrun;
1621     if (ctrl & EMAC_TX_ST_SQE)
1622         ++st->tx_bd_sqe;
1623 }
1624
1625 static void emac_poll_tx(void *param)
1626 {
1627     struct emac_instance *dev = param;
1628     u32 bad_mask;
1629
1630     DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1631
1632     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1633         bad_mask = EMAC_IS_BAD_TX_TAH;
1634     else
1635         bad_mask = EMAC_IS_BAD_TX;
1636
1637     netif_tx_lock_bh(dev->ndev);
1638     if (dev->tx_cnt) {
1639         u16 ctrl;
1640         int slot = dev->ack_slot, n = 0;
1641     again:
1642         ctrl = dev->tx_desc[slot].ctrl;
1643         if (!(ctrl & MAL_TX_CTRL_READY)) {
1644             struct sk_buff *skb = dev->tx_skb[slot];
1645             ++n;
1646
1647             if (skb) {
1648                 dev_kfree_skb(skb);
1649                 dev->tx_skb[slot] = NULL;
1650             }
1651             slot = (slot + 1) % NUM_TX_BUFF;
1652
1653             if (unlikely(ctrl & bad_mask))
1654                 emac_parse_tx_error(dev, ctrl);
1655
1656             if (--dev->tx_cnt)
1657                 goto again;
1658         }
1659         if (n) {
1660             dev->ack_slot = slot;
1661             if (netif_queue_stopped(dev->ndev) &&
1662                 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1663                 netif_wake_queue(dev->ndev);
1664
1665             DBG2(dev, "tx %d pkts" NL, n);
1666         }
1667     }
1668     netif_tx_unlock_bh(dev->ndev);
1669 }
1670
1671 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1672                        int len)
1673 {
1674     struct sk_buff *skb = dev->rx_skb[slot];
1675
1676     DBG2(dev, "recycle %d %d" NL, slot, len);
1677
1678     if (len)
1679         dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1680                    SKB_DATA_ALIGN(len + NET_IP_ALIGN),
1681                    DMA_FROM_DEVICE);
1682
1683     dev->rx_desc[slot].data_len = 0;
1684     wmb();
1685     dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1686         (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1687 }
1688
1689 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1690 {
1691     struct emac_error_stats *st = &dev->estats;
1692
1693     DBG(dev, "BD RX error %04x" NL, ctrl);
1694
1695     ++st->rx_bd_errors;
1696     if (ctrl & EMAC_RX_ST_OE)
1697         ++st->rx_bd_overrun;
1698     if (ctrl & EMAC_RX_ST_BP)
1699         ++st->rx_bd_bad_packet;
1700     if (ctrl & EMAC_RX_ST_RP)
1701         ++st->rx_bd_runt_packet;
1702     if (ctrl & EMAC_RX_ST_SE)
1703         ++st->rx_bd_short_event;
1704     if (ctrl & EMAC_RX_ST_AE)
1705         ++st->rx_bd_alignment_error;
1706     if (ctrl & EMAC_RX_ST_BFCS)
1707         ++st->rx_bd_bad_fcs;
1708     if (ctrl & EMAC_RX_ST_PTL)
1709         ++st->rx_bd_packet_too_long;
1710     if (ctrl & EMAC_RX_ST_ORE)
1711         ++st->rx_bd_out_of_range;
1712     if (ctrl & EMAC_RX_ST_IRE)
1713         ++st->rx_bd_in_range;
1714 }
1715
1716 static inline void emac_rx_csum(struct emac_instance *dev,
1717                 struct sk_buff *skb, u16 ctrl)
1718 {
1719 #ifdef CONFIG_IBM_EMAC_TAH
1720     if (!ctrl && dev->tah_dev) {
1721         skb->ip_summed = CHECKSUM_UNNECESSARY;
1722         ++dev->stats.rx_packets_csum;
1723     }
1724 #endif
1725 }
1726
1727 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1728 {
1729     if (likely(dev->rx_sg_skb != NULL)) {
1730         int len = dev->rx_desc[slot].data_len;
1731         int tot_len = dev->rx_sg_skb->len + len;
1732
1733         if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) {
1734             ++dev->estats.rx_dropped_mtu;
1735             dev_kfree_skb(dev->rx_sg_skb);
1736             dev->rx_sg_skb = NULL;
1737         } else {
1738             memcpy(skb_tail_pointer(dev->rx_sg_skb),
1739                      dev->rx_skb[slot]->data, len);
1740             skb_put(dev->rx_sg_skb, len);
1741             emac_recycle_rx_skb(dev, slot, len);
1742             return 0;
1743         }
1744     }
1745     emac_recycle_rx_skb(dev, slot, 0);
1746     return -1;
1747 }
1748
1749 /* NAPI poll context */
1750 static int emac_poll_rx(void *param, int budget)
1751 {
1752     struct emac_instance *dev = param;
1753     int slot = dev->rx_slot, received = 0;
1754
1755     DBG2(dev, "poll_rx(%d)" NL, budget);
1756
1757  again:
1758     while (budget > 0) {
1759         int len;
1760         struct sk_buff *skb;
1761         u16 ctrl = dev->rx_desc[slot].ctrl;
1762
1763         if (ctrl & MAL_RX_CTRL_EMPTY)
1764             break;
1765
1766         skb = dev->rx_skb[slot];
1767         mb();
1768         len = dev->rx_desc[slot].data_len;
1769
1770         if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1771             goto sg;
1772
1773         ctrl &= EMAC_BAD_RX_MASK;
1774         if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1775             emac_parse_rx_error(dev, ctrl);
1776             ++dev->estats.rx_dropped_error;
1777             emac_recycle_rx_skb(dev, slot, 0);
1778             len = 0;
1779             goto next;
1780         }
1781
1782         if (len < ETH_HLEN) {
1783             ++dev->estats.rx_dropped_stack;
1784             emac_recycle_rx_skb(dev, slot, len);
1785             goto next;
1786         }
1787
1788         if (len && len < EMAC_RX_COPY_THRESH) {
1789             struct sk_buff *copy_skb;
1790
1791             copy_skb = napi_alloc_skb(&dev->mal->napi, len);
1792             if (unlikely(!copy_skb))
1793                 goto oom;
1794
1795             memcpy(copy_skb->data - NET_IP_ALIGN,
1796                    skb->data - NET_IP_ALIGN,
1797                    len + NET_IP_ALIGN);
1798             emac_recycle_rx_skb(dev, slot, len);
1799             skb = copy_skb;
1800         } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot)))
1801             goto oom;
1802
1803         skb_put(skb, len);
1804     push_packet:
1805         skb->protocol = eth_type_trans(skb, dev->ndev);
1806         emac_rx_csum(dev, skb, ctrl);
1807
1808         if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1809             ++dev->estats.rx_dropped_stack;
1810     next:
1811         ++dev->stats.rx_packets;
1812     skip:
1813         dev->stats.rx_bytes += len;
1814         slot = (slot + 1) % NUM_RX_BUFF;
1815         --budget;
1816         ++received;
1817         continue;
1818     sg:
1819         if (ctrl & MAL_RX_CTRL_FIRST) {
1820             BUG_ON(dev->rx_sg_skb);
1821             if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) {
1822                 DBG(dev, "rx OOM %d" NL, slot);
1823                 ++dev->estats.rx_dropped_oom;
1824                 emac_recycle_rx_skb(dev, slot, 0);
1825             } else {
1826                 dev->rx_sg_skb = skb;
1827                 skb_put(skb, len);
1828             }
1829         } else if (!emac_rx_sg_append(dev, slot) &&
1830                (ctrl & MAL_RX_CTRL_LAST)) {
1831
1832             skb = dev->rx_sg_skb;
1833             dev->rx_sg_skb = NULL;
1834
1835             ctrl &= EMAC_BAD_RX_MASK;
1836             if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1837                 emac_parse_rx_error(dev, ctrl);
1838                 ++dev->estats.rx_dropped_error;
1839                 dev_kfree_skb(skb);
1840                 len = 0;
1841             } else
1842                 goto push_packet;
1843         }
1844         goto skip;
1845     oom:
1846         DBG(dev, "rx OOM %d" NL, slot);
1847         /* Drop the packet and recycle skb */
1848         ++dev->estats.rx_dropped_oom;
1849         emac_recycle_rx_skb(dev, slot, 0);
1850         goto next;
1851     }
1852
1853     if (received) {
1854         DBG2(dev, "rx %d BDs" NL, received);
1855         dev->rx_slot = slot;
1856     }
1857
1858     if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1859         mb();
1860         if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1861             DBG2(dev, "rx restart" NL);
1862             received = 0;
1863             goto again;
1864         }
1865
1866         if (dev->rx_sg_skb) {
1867             DBG2(dev, "dropping partial rx packet" NL);
1868             ++dev->estats.rx_dropped_error;
1869             dev_kfree_skb(dev->rx_sg_skb);
1870             dev->rx_sg_skb = NULL;
1871         }
1872
1873         clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1874         mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1875         emac_rx_enable(dev);
1876         dev->rx_slot = 0;
1877     }
1878     return received;
1879 }
1880
1881 /* NAPI poll context */
1882 static int emac_peek_rx(void *param)
1883 {
1884     struct emac_instance *dev = param;
1885
1886     return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1887 }
1888
1889 /* NAPI poll context */
1890 static int emac_peek_rx_sg(void *param)
1891 {
1892     struct emac_instance *dev = param;
1893
1894     int slot = dev->rx_slot;
1895     while (1) {
1896         u16 ctrl = dev->rx_desc[slot].ctrl;
1897         if (ctrl & MAL_RX_CTRL_EMPTY)
1898             return 0;
1899         else if (ctrl & MAL_RX_CTRL_LAST)
1900             return 1;
1901
1902         slot = (slot + 1) % NUM_RX_BUFF;
1903
1904         /* I'm just being paranoid here :) */
1905         if (unlikely(slot == dev->rx_slot))
1906             return 0;
1907     }
1908 }
1909
1910 /* Hard IRQ */
1911 static void emac_rxde(void *param)
1912 {
1913     struct emac_instance *dev = param;
1914
1915     ++dev->estats.rx_stopped;
1916     emac_rx_disable_async(dev);
1917 }
1918
1919 /* Hard IRQ */
1920 static irqreturn_t emac_irq(int irq, void *dev_instance)
1921 {
1922     struct emac_instance *dev = dev_instance;
1923     struct emac_regs __iomem *p = dev->emacp;
1924     struct emac_error_stats *st = &dev->estats;
1925     u32 isr;
1926
1927     spin_lock(&dev->lock);
1928
1929     isr = in_be32(&p->isr);
1930     out_be32(&p->isr, isr);
1931
1932     DBG(dev, "isr = %08x" NL, isr);
1933
1934     if (isr & EMAC4_ISR_TXPE)
1935         ++st->tx_parity;
1936     if (isr & EMAC4_ISR_RXPE)
1937         ++st->rx_parity;
1938     if (isr & EMAC4_ISR_TXUE)
1939         ++st->tx_underrun;
1940     if (isr & EMAC4_ISR_RXOE)
1941         ++st->rx_fifo_overrun;
1942     if (isr & EMAC_ISR_OVR)
1943         ++st->rx_overrun;
1944     if (isr & EMAC_ISR_BP)
1945         ++st->rx_bad_packet;
1946     if (isr & EMAC_ISR_RP)
1947         ++st->rx_runt_packet;
1948     if (isr & EMAC_ISR_SE)
1949         ++st->rx_short_event;
1950     if (isr & EMAC_ISR_ALE)
1951         ++st->rx_alignment_error;
1952     if (isr & EMAC_ISR_BFCS)
1953         ++st->rx_bad_fcs;
1954     if (isr & EMAC_ISR_PTLE)
1955         ++st->rx_packet_too_long;
1956     if (isr & EMAC_ISR_ORE)
1957         ++st->rx_out_of_range;
1958     if (isr & EMAC_ISR_IRE)
1959         ++st->rx_in_range;
1960     if (isr & EMAC_ISR_SQE)
1961         ++st->tx_sqe;
1962     if (isr & EMAC_ISR_TE)
1963         ++st->tx_errors;
1964
1965     spin_unlock(&dev->lock);
1966
1967     return IRQ_HANDLED;
1968 }
1969
1970 static struct net_device_stats *emac_stats(struct net_device *ndev)
1971 {
1972     struct emac_instance *dev = netdev_priv(ndev);
1973     struct emac_stats *st = &dev->stats;
1974     struct emac_error_stats *est = &dev->estats;
1975     struct net_device_stats *nst = &ndev->stats;
1976     unsigned long flags;
1977
1978     DBG2(dev, "stats" NL);
1979
1980     /* Compute "legacy" statistics */
1981     spin_lock_irqsave(&dev->lock, flags);
1982     nst->rx_packets = (unsigned long)st->rx_packets;
1983     nst->rx_bytes = (unsigned long)st->rx_bytes;
1984     nst->tx_packets = (unsigned long)st->tx_packets;
1985     nst->tx_bytes = (unsigned long)st->tx_bytes;
1986     nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1987                       est->rx_dropped_error +
1988                       est->rx_dropped_resize +
1989                       est->rx_dropped_mtu);
1990     nst->tx_dropped = (unsigned long)est->tx_dropped;
1991
1992     nst->rx_errors = (unsigned long)est->rx_bd_errors;
1993     nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1994                           est->rx_fifo_overrun +
1995                           est->rx_overrun);
1996     nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1997                            est->rx_alignment_error);
1998     nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1999                          est->rx_bad_fcs);
2000     nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
2001                         est->rx_bd_short_event +
2002                         est->rx_bd_packet_too_long +
2003                         est->rx_bd_out_of_range +
2004                         est->rx_bd_in_range +
2005                         est->rx_runt_packet +
2006                         est->rx_short_event +
2007                         est->rx_packet_too_long +
2008                         est->rx_out_of_range +
2009                         est->rx_in_range);
2010
2011     nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
2012     nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
2013                           est->tx_underrun);
2014     nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
2015     nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
2016                       est->tx_bd_excessive_collisions +
2017                       est->tx_bd_late_collision +
2018                       est->tx_bd_multple_collisions);
2019     spin_unlock_irqrestore(&dev->lock, flags);
2020     return nst;
2021 }
2022
2023 static struct mal_commac_ops emac_commac_ops = {
2024     .poll_tx = &emac_poll_tx,
2025     .poll_rx = &emac_poll_rx,
2026     .peek_rx = &emac_peek_rx,
2027     .rxde = &emac_rxde,
2028 };
2029
2030 static struct mal_commac_ops emac_commac_sg_ops = {
2031     .poll_tx = &emac_poll_tx,
2032     .poll_rx = &emac_poll_rx,
2033     .peek_rx = &emac_peek_rx_sg,
2034     .rxde = &emac_rxde,
2035 };
2036
2037 /* Ethtool support */
2038 static int emac_ethtool_get_link_ksettings(struct net_device *ndev,
2039                        struct ethtool_link_ksettings *cmd)
2040 {
2041     struct emac_instance *dev = netdev_priv(ndev);
2042     u32 supported, advertising;
2043
2044     supported = dev->phy.features;
2045     cmd->base.port = PORT_MII;
2046     cmd->base.phy_address = dev->phy.address;
2047
2048     mutex_lock(&dev->link_lock);
2049     advertising = dev->phy.advertising;
2050     cmd->base.autoneg = dev->phy.autoneg;
2051     cmd->base.speed = dev->phy.speed;
2052     cmd->base.duplex = dev->phy.duplex;
2053     mutex_unlock(&dev->link_lock);
2054
2055     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2056                         supported);
2057     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2058                         advertising);
2059
2060     return 0;
2061 }
2062
2063 static int
2064 emac_ethtool_set_link_ksettings(struct net_device *ndev,
2065                 const struct ethtool_link_ksettings *cmd)
2066 {
2067     struct emac_instance *dev = netdev_priv(ndev);
2068     u32 f = dev->phy.features;
2069     u32 advertising;
2070
2071     ethtool_convert_link_mode_to_legacy_u32(&advertising,
2072                         cmd->link_modes.advertising);
2073
2074     DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2075         cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising);
2076
2077     /* Basic sanity checks */
2078     if (dev->phy.address < 0)
2079         return -EOPNOTSUPP;
2080     if (cmd->base.autoneg != AUTONEG_ENABLE &&
2081         cmd->base.autoneg != AUTONEG_DISABLE)
2082         return -EINVAL;
2083     if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0)
2084         return -EINVAL;
2085     if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL)
2086         return -EINVAL;
2087
2088     if (cmd->base.autoneg == AUTONEG_DISABLE) {
2089         switch (cmd->base.speed) {
2090         case SPEED_10:
2091             if (cmd->base.duplex == DUPLEX_HALF &&
2092                 !(f & SUPPORTED_10baseT_Half))
2093                 return -EINVAL;
2094             if (cmd->base.duplex == DUPLEX_FULL &&
2095                 !(f & SUPPORTED_10baseT_Full))
2096                 return -EINVAL;
2097             break;
2098         case SPEED_100:
2099             if (cmd->base.duplex == DUPLEX_HALF &&
2100                 !(f & SUPPORTED_100baseT_Half))
2101                 return -EINVAL;
2102             if (cmd->base.duplex == DUPLEX_FULL &&
2103                 !(f & SUPPORTED_100baseT_Full))
2104                 return -EINVAL;
2105             break;
2106         case SPEED_1000:
2107             if (cmd->base.duplex == DUPLEX_HALF &&
2108                 !(f & SUPPORTED_1000baseT_Half))
2109                 return -EINVAL;
2110             if (cmd->base.duplex == DUPLEX_FULL &&
2111                 !(f & SUPPORTED_1000baseT_Full))
2112                 return -EINVAL;
2113             break;
2114         default:
2115             return -EINVAL;
2116         }
2117
2118         mutex_lock(&dev->link_lock);
2119         dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed,
2120                         cmd->base.duplex);
2121         mutex_unlock(&dev->link_lock);
2122
2123     } else {
2124         if (!(f & SUPPORTED_Autoneg))
2125             return -EINVAL;
2126
2127         mutex_lock(&dev->link_lock);
2128         dev->phy.def->ops->setup_aneg(&dev->phy,
2129                           (advertising & f) |
2130                           (dev->phy.advertising &
2131                            (ADVERTISED_Pause |
2132                         ADVERTISED_Asym_Pause)));
2133         mutex_unlock(&dev->link_lock);
2134     }
2135     emac_force_link_update(dev);
2136
2137     return 0;
2138 }
2139
2140 static void
2141 emac_ethtool_get_ringparam(struct net_device *ndev,
2142                struct ethtool_ringparam *rp,
2143                struct kernel_ethtool_ringparam *kernel_rp,
2144                struct netlink_ext_ack *extack)
2145 {
2146     rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2147     rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2148 }
2149
2150 static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2151                     struct ethtool_pauseparam *pp)
2152 {
2153     struct emac_instance *dev = netdev_priv(ndev);
2154
2155     mutex_lock(&dev->link_lock);
2156     if ((dev->phy.features & SUPPORTED_Autoneg) &&
2157         (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2158         pp->autoneg = 1;
2159
2160     if (dev->phy.duplex == DUPLEX_FULL) {
2161         if (dev->phy.pause)
2162             pp->rx_pause = pp->tx_pause = 1;
2163         else if (dev->phy.asym_pause)
2164             pp->tx_pause = 1;
2165     }
2166     mutex_unlock(&dev->link_lock);
2167 }
2168
2169 static int emac_get_regs_len(struct emac_instance *dev)
2170 {
2171         return sizeof(struct emac_ethtool_regs_subhdr) +
2172             sizeof(struct emac_regs);
2173 }
2174
2175 static int emac_ethtool_get_regs_len(struct net_device *ndev)
2176 {
2177     struct emac_instance *dev = netdev_priv(ndev);
2178     int size;
2179
2180     size = sizeof(struct emac_ethtool_regs_hdr) +
2181         emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2182     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2183         size += zmii_get_regs_len(dev->zmii_dev);
2184     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2185         size += rgmii_get_regs_len(dev->rgmii_dev);
2186     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2187         size += tah_get_regs_len(dev->tah_dev);
2188
2189     return size;
2190 }
2191
2192 static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2193 {
2194     struct emac_ethtool_regs_subhdr *hdr = buf;
2195
2196     hdr->index = dev->cell_index;
2197     if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2198         hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER;
2199     } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2200         hdr->version = EMAC4_ETHTOOL_REGS_VER;
2201     } else {
2202         hdr->version = EMAC_ETHTOOL_REGS_VER;
2203     }
2204     memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2205     return (void *)(hdr + 1) + sizeof(struct emac_regs);
2206 }
2207
2208 static void emac_ethtool_get_regs(struct net_device *ndev,
2209                   struct ethtool_regs *regs, void *buf)
2210 {
2211     struct emac_instance *dev = netdev_priv(ndev);
2212     struct emac_ethtool_regs_hdr *hdr = buf;
2213
2214     hdr->components = 0;
2215     buf = hdr + 1;
2216
2217     buf = mal_dump_regs(dev->mal, buf);
2218     buf = emac_dump_regs(dev, buf);
2219     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2220         hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2221         buf = zmii_dump_regs(dev->zmii_dev, buf);
2222     }
2223     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2224         hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2225         buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2226     }
2227     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2228         hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2229         buf = tah_dump_regs(dev->tah_dev, buf);
2230     }
2231 }
2232
2233 static int emac_ethtool_nway_reset(struct net_device *ndev)
2234 {
2235     struct emac_instance *dev = netdev_priv(ndev);
2236     int res = 0;
2237
2238     DBG(dev, "nway_reset" NL);
2239
2240     if (dev->phy.address < 0)
2241         return -EOPNOTSUPP;
2242
2243     mutex_lock(&dev->link_lock);
2244     if (!dev->phy.autoneg) {
2245         res = -EINVAL;
2246         goto out;
2247     }
2248
2249     dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2250  out:
2251     mutex_unlock(&dev->link_lock);
2252     emac_force_link_update(dev);
2253     return res;
2254 }
2255
2256 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2257 {
2258     if (stringset == ETH_SS_STATS)
2259         return EMAC_ETHTOOL_STATS_COUNT;
2260     else
2261         return -EINVAL;
2262 }
2263
2264 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2265                      u8 * buf)
2266 {
2267     if (stringset == ETH_SS_STATS)
2268         memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2269 }
2270
2271 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2272                        struct ethtool_stats *estats,
2273                        u64 * tmp_stats)
2274 {
2275     struct emac_instance *dev = netdev_priv(ndev);
2276
2277     memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2278     tmp_stats += sizeof(dev->stats) / sizeof(u64);
2279     memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2280 }
2281
2282 static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2283                      struct ethtool_drvinfo *info)
2284 {
2285     struct emac_instance *dev = netdev_priv(ndev);
2286
2287     strlcpy(info->driver, "ibm_emac", sizeof(info->driver));
2288     strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2289     snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF",
2290          dev->cell_index, dev->ofdev->dev.of_node);
2291 }
2292
2293 static const struct ethtool_ops emac_ethtool_ops = {
2294     .get_drvinfo = emac_ethtool_get_drvinfo,
2295
2296     .get_regs_len = emac_ethtool_get_regs_len,
2297     .get_regs = emac_ethtool_get_regs,
2298
2299     .nway_reset = emac_ethtool_nway_reset,
2300
2301     .get_ringparam = emac_ethtool_get_ringparam,
2302     .get_pauseparam = emac_ethtool_get_pauseparam,
2303
2304     .get_strings = emac_ethtool_get_strings,
2305     .get_sset_count = emac_ethtool_get_sset_count,
2306     .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2307
2308     .get_link = ethtool_op_get_link,
2309     .get_link_ksettings = emac_ethtool_get_link_ksettings,
2310     .set_link_ksettings = emac_ethtool_set_link_ksettings,
2311 };
2312
2313 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2314 {
2315     struct emac_instance *dev = netdev_priv(ndev);
2316     struct mii_ioctl_data *data = if_mii(rq);
2317
2318     DBG(dev, "ioctl %08x" NL, cmd);
2319
2320     if (dev->phy.address < 0)
2321         return -EOPNOTSUPP;
2322
2323     switch (cmd) {
2324     case SIOCGMIIPHY:
2325         data->phy_id = dev->phy.address;
2326         fallthrough;
2327     case SIOCGMIIREG:
2328         data->val_out = emac_mdio_read(ndev, dev->phy.address,
2329                            data->reg_num);
2330         return 0;
2331
2332     case SIOCSMIIREG:
2333         emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2334                 data->val_in);
2335         return 0;
2336     default:
2337         return -EOPNOTSUPP;
2338     }
2339 }
2340
2341 struct emac_depentry {
2342     u32         phandle;
2343     struct device_node  *node;
2344     struct platform_device  *ofdev;
2345     void            *drvdata;
2346 };
2347
2348 #define EMAC_DEP_MAL_IDX    0
2349 #define EMAC_DEP_ZMII_IDX   1
2350 #define EMAC_DEP_RGMII_IDX  2
2351 #define EMAC_DEP_TAH_IDX    3
2352 #define EMAC_DEP_MDIO_IDX   4
2353 #define EMAC_DEP_PREV_IDX   5
2354 #define EMAC_DEP_COUNT      6
2355
2356 static int emac_check_deps(struct emac_instance *dev,
2357                struct emac_depentry *deps)
2358 {
2359     int i, there = 0;
2360     struct device_node *np;
2361
2362     for (i = 0; i < EMAC_DEP_COUNT; i++) {
2363         /* no dependency on that item, allright */
2364         if (deps[i].phandle == 0) {
2365             there++;
2366             continue;
2367         }
2368         /* special case for blist as the dependency might go away */
2369         if (i == EMAC_DEP_PREV_IDX) {
2370             np = *(dev->blist - 1);
2371             if (np == NULL) {
2372                 deps[i].phandle = 0;
2373                 there++;
2374                 continue;
2375             }
2376             if (deps[i].node == NULL)
2377                 deps[i].node = of_node_get(np);
2378         }
2379         if (deps[i].node == NULL)
2380             deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2381         if (deps[i].node == NULL)
2382             continue;
2383         if (deps[i].ofdev == NULL)
2384             deps[i].ofdev = of_find_device_by_node(deps[i].node);
2385         if (deps[i].ofdev == NULL)
2386             continue;
2387         if (deps[i].drvdata == NULL)
2388             deps[i].drvdata = platform_get_drvdata(deps[i].ofdev);
2389         if (deps[i].drvdata != NULL)
2390             there++;
2391     }
2392     return there == EMAC_DEP_COUNT;
2393 }
2394
2395 static void emac_put_deps(struct emac_instance *dev)
2396 {
2397     platform_device_put(dev->mal_dev);
2398     platform_device_put(dev->zmii_dev);
2399     platform_device_put(dev->rgmii_dev);
2400     platform_device_put(dev->mdio_dev);
2401     platform_device_put(dev->tah_dev);
2402 }
2403
2404 static int emac_of_bus_notify(struct notifier_block *nb, unsigned long action,
2405                   void *data)
2406 {
2407     /* We are only intereted in device addition */
2408     if (action == BUS_NOTIFY_BOUND_DRIVER)
2409         wake_up_all(&emac_probe_wait);
2410     return 0;
2411 }
2412
2413 static struct notifier_block emac_of_bus_notifier = {
2414     .notifier_call = emac_of_bus_notify
2415 };
2416
2417 static int emac_wait_deps(struct emac_instance *dev)
2418 {
2419     struct emac_depentry deps[EMAC_DEP_COUNT];
2420     int i, err;
2421
2422     memset(&deps, 0, sizeof(deps));
2423
2424     deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2425     deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2426     deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2427     if (dev->tah_ph)
2428         deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2429     if (dev->mdio_ph)
2430         deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2431     if (dev->blist && dev->blist > emac_boot_list)
2432         deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2433     bus_register_notifier(&platform_bus_type, &emac_of_bus_notifier);
2434     wait_event_timeout(emac_probe_wait,
2435                emac_check_deps(dev, deps),
2436                EMAC_PROBE_DEP_TIMEOUT);
2437     bus_unregister_notifier(&platform_bus_type, &emac_of_bus_notifier);
2438     err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2439     for (i = 0; i < EMAC_DEP_COUNT; i++) {
2440         of_node_put(deps[i].node);
2441         if (err)
2442             platform_device_put(deps[i].ofdev);
2443     }
2444     if (err == 0) {
2445         dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2446         dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2447         dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2448         dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2449         dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2450     }
2451     platform_device_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2452     return err;
2453 }
2454
2455 static int emac_read_uint_prop(struct device_node *np, const char *name,
2456                    u32 *val, int fatal)
2457 {
2458     int len;
2459     const u32 *prop = of_get_property(np, name, &len);
2460     if (prop == NULL || len < sizeof(u32)) {
2461         if (fatal)
2462             printk(KERN_ERR "%pOF: missing %s property\n",
2463                    np, name);
2464         return -ENODEV;
2465     }
2466     *val = *prop;
2467     return 0;
2468 }
2469
2470 static void emac_adjust_link(struct net_device *ndev)
2471 {
2472     struct emac_instance *dev = netdev_priv(ndev);
2473     struct phy_device *phy = dev->phy_dev;
2474
2475     dev->phy.autoneg = phy->autoneg;
2476     dev->phy.speed = phy->speed;
2477     dev->phy.duplex = phy->duplex;
2478     dev->phy.pause = phy->pause;
2479     dev->phy.asym_pause = phy->asym_pause;
2480     ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising,
2481                         phy->advertising);
2482 }
2483
2484 static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
2485 {
2486     int ret = emac_mdio_read(bus->priv, addr, regnum);
2487     /* This is a workaround for powered down ports/phys.
2488      * In the wild, this was seen on the Cisco Meraki MX60(W).
2489      * This hardware disables ports as part of the handoff
2490      * procedure. Accessing the ports will lead to errors
2491      * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good.
2492      */
2493     return ret < 0 ? 0xffff : ret;
2494 }
2495
2496 static int emac_mii_bus_write(struct mii_bus *bus, int addr,
2497                   int regnum, u16 val)
2498 {
2499     emac_mdio_write(bus->priv, addr, regnum, val);
2500     return 0;
2501 }
2502
2503 static int emac_mii_bus_reset(struct mii_bus *bus)
2504 {
2505     struct emac_instance *dev = netdev_priv(bus->priv);
2506
2507     return emac_reset(dev);
2508 }
2509
2510 static int emac_mdio_phy_start_aneg(struct mii_phy *phy,
2511                     struct phy_device *phy_dev)
2512 {
2513     phy_dev->autoneg = phy->autoneg;
2514     phy_dev->speed = phy->speed;
2515     phy_dev->duplex = phy->duplex;
2516     ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising,
2517                         phy->advertising);
2518     return phy_start_aneg(phy_dev);
2519 }
2520
2521 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
2522 {
2523     struct net_device *ndev = phy->dev;
2524     struct emac_instance *dev = netdev_priv(ndev);
2525
2526     phy->autoneg = AUTONEG_ENABLE;
2527     phy->advertising = advertise;
2528     return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
2529 }
2530
2531 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
2532 {
2533     struct net_device *ndev = phy->dev;
2534     struct emac_instance *dev = netdev_priv(ndev);
2535
2536     phy->autoneg = AUTONEG_DISABLE;
2537     phy->speed = speed;
2538     phy->duplex = fd;
2539     return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
2540 }
2541
2542 static int emac_mdio_poll_link(struct mii_phy *phy)
2543 {
2544     struct net_device *ndev = phy->dev;
2545     struct emac_instance *dev = netdev_priv(ndev);
2546     int res;
2547
2548     res = phy_read_status(dev->phy_dev);
2549     if (res) {
2550         dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
2551         return ethtool_op_get_link(ndev);
2552     }
2553
2554     return dev->phy_dev->link;
2555 }
2556
2557 static int emac_mdio_read_link(struct mii_phy *phy)
2558 {
2559     struct net_device *ndev = phy->dev;
2560     struct emac_instance *dev = netdev_priv(ndev);
2561     struct phy_device *phy_dev = dev->phy_dev;
2562     int res;
2563
2564     res = phy_read_status(phy_dev);
2565     if (res)
2566         return res;
2567
2568     phy->speed = phy_dev->speed;
2569     phy->duplex = phy_dev->duplex;
2570     phy->pause = phy_dev->pause;
2571     phy->asym_pause = phy_dev->asym_pause;
2572     return 0;
2573 }
2574
2575 static int emac_mdio_init_phy(struct mii_phy *phy)
2576 {
2577     struct net_device *ndev = phy->dev;
2578     struct emac_instance *dev = netdev_priv(ndev);
2579
2580     phy_start(dev->phy_dev);
2581     return phy_init_hw(dev->phy_dev);
2582 }
2583
2584 static const struct mii_phy_ops emac_dt_mdio_phy_ops = {
2585     .init       = emac_mdio_init_phy,
2586     .setup_aneg = emac_mdio_setup_aneg,
2587     .setup_forced   = emac_mdio_setup_forced,
2588     .poll_link  = emac_mdio_poll_link,
2589     .read_link  = emac_mdio_read_link,
2590 };
2591
2592 static int emac_dt_mdio_probe(struct emac_instance *dev)
2593 {
2594     struct device_node *mii_np;
2595     int res;
2596
2597     mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio");
2598     if (!mii_np) {
2599         dev_err(&dev->ofdev->dev, "no mdio definition found.");
2600         return -ENODEV;
2601     }
2602
2603     if (!of_device_is_available(mii_np)) {
2604         res = -ENODEV;
2605         goto put_node;
2606     }
2607
2608     dev->mii_bus = devm_mdiobus_alloc(&dev->ofdev->dev);
2609     if (!dev->mii_bus) {
2610         res = -ENOMEM;
2611         goto put_node;
2612     }
2613
2614     dev->mii_bus->priv = dev->ndev;
2615     dev->mii_bus->parent = dev->ndev->dev.parent;
2616     dev->mii_bus->name = "emac_mdio";
2617     dev->mii_bus->read = &emac_mii_bus_read;
2618     dev->mii_bus->write = &emac_mii_bus_write;
2619     dev->mii_bus->reset = &emac_mii_bus_reset;
2620     snprintf(dev->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
2621     res = of_mdiobus_register(dev->mii_bus, mii_np);
2622     if (res) {
2623         dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
2624             dev->mii_bus->name, res);
2625     }
2626
2627  put_node:
2628     of_node_put(mii_np);
2629     return res;
2630 }
2631
2632 static int emac_dt_phy_connect(struct emac_instance *dev,
2633                    struct device_node *phy_handle)
2634 {
2635     dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
2636                     GFP_KERNEL);
2637     if (!dev->phy.def)
2638         return -ENOMEM;
2639
2640     dev->phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link,
2641                       0, dev->phy_mode);
2642     if (!dev->phy_dev) {
2643         dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
2644         return -ENODEV;
2645     }
2646
2647     dev->phy.def->phy_id = dev->phy_dev->drv->phy_id;
2648     dev->phy.def->phy_id_mask = dev->phy_dev->drv->phy_id_mask;
2649     dev->phy.def->name = dev->phy_dev->drv->name;
2650     dev->phy.def->ops = &emac_dt_mdio_phy_ops;
2651     ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features,
2652                         dev->phy_dev->supported);
2653     dev->phy.address = dev->phy_dev->mdio.addr;
2654     dev->phy.mode = dev->phy_dev->interface;
2655     return 0;
2656 }
2657
2658 static int emac_dt_phy_probe(struct emac_instance *dev)
2659 {
2660     struct device_node *np = dev->ofdev->dev.of_node;
2661     struct device_node *phy_handle;
2662     int res = 1;
2663
2664     phy_handle = of_parse_phandle(np, "phy-handle", 0);
2665
2666     if (phy_handle) {
2667         res = emac_dt_mdio_probe(dev);
2668         if (!res) {
2669             res = emac_dt_phy_connect(dev, phy_handle);
2670             if (res)
2671                 mdiobus_unregister(dev->mii_bus);
2672         }
2673     }
2674
2675     of_node_put(phy_handle);
2676     return res;
2677 }
2678
2679 static int emac_init_phy(struct emac_instance *dev)
2680 {
2681     struct device_node *np = dev->ofdev->dev.of_node;
2682     struct net_device *ndev = dev->ndev;
2683     u32 phy_map, adv;
2684     int i;
2685
2686     dev->phy.dev = ndev;
2687     dev->phy.mode = dev->phy_mode;
2688
2689     /* PHY-less configuration. */
2690     if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) ||
2691         of_phy_is_fixed_link(np)) {
2692         emac_reset(dev);
2693
2694         /* PHY-less configuration. */
2695         dev->phy.address = -1;
2696         dev->phy.features = SUPPORTED_MII;
2697         if (emac_phy_supports_gige(dev->phy_mode))
2698             dev->phy.features |= SUPPORTED_1000baseT_Full;
2699         else
2700             dev->phy.features |= SUPPORTED_100baseT_Full;
2701         dev->phy.pause = 1;
2702
2703         if (of_phy_is_fixed_link(np)) {
2704             int res = emac_dt_mdio_probe(dev);
2705
2706             if (res)
2707                 return res;
2708
2709             res = of_phy_register_fixed_link(np);
2710             dev->phy_dev = of_phy_find_device(np);
2711             if (res || !dev->phy_dev) {
2712                 mdiobus_unregister(dev->mii_bus);
2713                 return res ? res : -EINVAL;
2714             }
2715             emac_adjust_link(dev->ndev);
2716             put_device(&dev->phy_dev->mdio.dev);
2717         }
2718         return 0;
2719     }
2720
2721     mutex_lock(&emac_phy_map_lock);
2722     phy_map = dev->phy_map | busy_phy_map;
2723
2724     DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2725
2726     dev->phy.mdio_read = emac_mdio_read;
2727     dev->phy.mdio_write = emac_mdio_write;
2728
2729     /* Enable internal clock source */
2730 #ifdef CONFIG_PPC_DCR_NATIVE
2731     if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2732         dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2733 #endif
2734     /* PHY clock workaround */
2735     emac_rx_clk_tx(dev);
2736
2737     /* Enable internal clock source on 440GX*/
2738 #ifdef CONFIG_PPC_DCR_NATIVE
2739     if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2740         dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2741 #endif
2742     /* Configure EMAC with defaults so we can at least use MDIO
2743      * This is needed mostly for 440GX
2744      */
2745     if (emac_phy_gpcs(dev->phy.mode)) {
2746         /* XXX
2747          * Make GPCS PHY address equal to EMAC index.
2748          * We probably should take into account busy_phy_map
2749          * and/or phy_map here.
2750          *
2751          * Note that the busy_phy_map is currently global
2752          * while it should probably be per-ASIC...
2753          */
2754         dev->phy.gpcs_address = dev->gpcs_address;
2755         if (dev->phy.gpcs_address == 0xffffffff)
2756             dev->phy.address = dev->cell_index;
2757     }
2758
2759     emac_configure(dev);
2760
2761     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2762         int res = emac_dt_phy_probe(dev);
2763
2764         switch (res) {
2765         case 1:
2766             /* No phy-handle property configured.
2767              * Continue with the existing phy probe
2768              * and setup code.
2769              */
2770             break;
2771
2772         case 0:
2773             mutex_unlock(&emac_phy_map_lock);
2774             goto init_phy;
2775
2776         default:
2777             mutex_unlock(&emac_phy_map_lock);
2778             dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
2779                 res);
2780             return res;
2781         }
2782     }
2783
2784     if (dev->phy_address != 0xffffffff)
2785         phy_map = ~(1 << dev->phy_address);
2786
2787     for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2788         if (!(phy_map & 1)) {
2789             int r;
2790             busy_phy_map |= 1 << i;
2791
2792             /* Quick check if there is a PHY at the address */
2793             r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2794             if (r == 0xffff || r < 0)
2795                 continue;
2796             if (!emac_mii_phy_probe(&dev->phy, i))
2797                 break;
2798         }
2799
2800     /* Enable external clock source */
2801 #ifdef CONFIG_PPC_DCR_NATIVE
2802     if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2803         dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2804 #endif
2805     mutex_unlock(&emac_phy_map_lock);
2806     if (i == 0x20) {
2807         printk(KERN_WARNING "%pOF: can't find PHY!\n", np);
2808         return -ENXIO;
2809     }
2810
2811  init_phy:
2812     /* Init PHY */
2813     if (dev->phy.def->ops->init)
2814         dev->phy.def->ops->init(&dev->phy);
2815
2816     /* Disable any PHY features not supported by the platform */
2817     dev->phy.def->features &= ~dev->phy_feat_exc;
2818     dev->phy.features &= ~dev->phy_feat_exc;
2819
2820     /* Setup initial link parameters */
2821     if (dev->phy.features & SUPPORTED_Autoneg) {
2822         adv = dev->phy.features;
2823         if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2824             adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2825         /* Restart autonegotiation */
2826         dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2827     } else {
2828         u32 f = dev->phy.def->features;
2829         int speed = SPEED_10, fd = DUPLEX_HALF;
2830
2831         /* Select highest supported speed/duplex */
2832         if (f & SUPPORTED_1000baseT_Full) {
2833             speed = SPEED_1000;
2834             fd = DUPLEX_FULL;
2835         } else if (f & SUPPORTED_1000baseT_Half)
2836             speed = SPEED_1000;
2837         else if (f & SUPPORTED_100baseT_Full) {
2838             speed = SPEED_100;
2839             fd = DUPLEX_FULL;
2840         } else if (f & SUPPORTED_100baseT_Half)
2841             speed = SPEED_100;
2842         else if (f & SUPPORTED_10baseT_Full)
2843             fd = DUPLEX_FULL;
2844
2845         /* Force link parameters */
2846         dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2847     }
2848     return 0;
2849 }
2850
2851 static int emac_init_config(struct emac_instance *dev)
2852 {
2853     struct device_node *np = dev->ofdev->dev.of_node;
2854     int err;
2855
2856     /* Read config from device-tree */
2857     if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2858         return -ENXIO;
2859     if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2860         return -ENXIO;
2861     if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2862         return -ENXIO;
2863     if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2864         return -ENXIO;
2865     if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2866         dev->max_mtu = ETH_DATA_LEN;
2867     if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2868         dev->rx_fifo_size = 2048;
2869     if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2870         dev->tx_fifo_size = 2048;
2871     if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2872         dev->rx_fifo_size_gige = dev->rx_fifo_size;
2873     if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2874         dev->tx_fifo_size_gige = dev->tx_fifo_size;
2875     if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2876         dev->phy_address = 0xffffffff;
2877     if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2878         dev->phy_map = 0xffffffff;
2879     if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2880         dev->gpcs_address = 0xffffffff;
2881     if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2882         return -ENXIO;
2883     if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2884         dev->tah_ph = 0;
2885     if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2886         dev->tah_port = 0;
2887     if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2888         dev->mdio_ph = 0;
2889     if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2890         dev->zmii_ph = 0;
2891     if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2892         dev->zmii_port = 0xffffffff;
2893     if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2894         dev->rgmii_ph = 0;
2895     if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2896         dev->rgmii_port = 0xffffffff;
2897     if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2898         dev->fifo_entry_size = 16;
2899     if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2900         dev->mal_burst_size = 256;
2901
2902     /* PHY mode needs some decoding */
2903     err = of_get_phy_mode(np, &dev->phy_mode);
2904     if (err)
2905         dev->phy_mode = PHY_INTERFACE_MODE_NA;
2906
2907     /* Check EMAC version */
2908     if (of_device_is_compatible(np, "ibm,emac4sync")) {
2909         dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2910         if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2911             of_device_is_compatible(np, "ibm,emac-460gt"))
2912             dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2913         if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2914             of_device_is_compatible(np, "ibm,emac-405exr"))
2915             dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2916         if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2917             dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2918                       EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2919                       EMAC_FTR_460EX_PHY_CLK_FIX);
2920         }
2921     } else if (of_device_is_compatible(np, "ibm,emac4")) {
2922         dev->features |= EMAC_FTR_EMAC4;
2923         if (of_device_is_compatible(np, "ibm,emac-440gx"))
2924             dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2925     } else {
2926         if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2927             of_device_is_compatible(np, "ibm,emac-440gr"))
2928             dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2929         if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2930 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2931             dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2932 #else
2933             printk(KERN_ERR "%pOF: Flow control not disabled!\n",
2934                     np);
2935             return -ENXIO;
2936 #endif
2937         }
2938
2939     }
2940
2941     /* Fixup some feature bits based on the device tree */
2942     if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2943         dev->features |= EMAC_FTR_STACR_OC_INVERT;
2944     if (of_get_property(np, "has-new-stacr-staopc", NULL))
2945         dev->features |= EMAC_FTR_HAS_NEW_STACR;
2946
2947     /* CAB lacks the appropriate properties */
2948     if (of_device_is_compatible(np, "ibm,emac-axon"))
2949         dev->features |= EMAC_FTR_HAS_NEW_STACR |
2950             EMAC_FTR_STACR_OC_INVERT;
2951
2952     /* Enable TAH/ZMII/RGMII features as found */
2953     if (dev->tah_ph != 0) {
2954 #ifdef CONFIG_IBM_EMAC_TAH
2955         dev->features |= EMAC_FTR_HAS_TAH;
2956 #else
2957         printk(KERN_ERR "%pOF: TAH support not enabled !\n", np);
2958         return -ENXIO;
2959 #endif
2960     }
2961
2962     if (dev->zmii_ph != 0) {
2963 #ifdef CONFIG_IBM_EMAC_ZMII
2964         dev->features |= EMAC_FTR_HAS_ZMII;
2965 #else
2966         printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np);
2967         return -ENXIO;
2968 #endif
2969     }
2970
2971     if (dev->rgmii_ph != 0) {
2972 #ifdef CONFIG_IBM_EMAC_RGMII
2973         dev->features |= EMAC_FTR_HAS_RGMII;
2974 #else
2975         printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np);
2976         return -ENXIO;
2977 #endif
2978     }
2979
2980     /* Read MAC-address */
2981     err = of_get_ethdev_address(np, dev->ndev);
2982     if (err) {
2983         if (err != -EPROBE_DEFER)
2984             dev_err(&dev->ofdev->dev, "Can't get valid [local-]mac-address from OF !\n");
2985         return err;
2986     }
2987
2988     /* IAHT and GAHT filter parameterization */
2989     if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2990         dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2991         dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2992     } else {
2993         dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2994         dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2995     }
2996
2997     /* This should never happen */
2998     if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS))
2999         return -ENXIO;
3000
3001     DBG(dev, "features     : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
3002     DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
3003     DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
3004     DBG(dev, "max_mtu      : %d\n", dev->max_mtu);
3005     DBG(dev, "OPB freq     : %d\n", dev->opb_bus_freq);
3006
3007     return 0;
3008 }
3009
3010 static const struct net_device_ops emac_netdev_ops = {
3011     .ndo_open       = emac_open,
3012     .ndo_stop       = emac_close,
3013     .ndo_get_stats      = emac_stats,
3014     .ndo_set_rx_mode    = emac_set_multicast_list,
3015     .ndo_eth_ioctl      = emac_ioctl,
3016     .ndo_tx_timeout     = emac_tx_timeout,
3017     .ndo_validate_addr  = eth_validate_addr,
3018     .ndo_set_mac_address    = emac_set_mac_address,
3019     .ndo_start_xmit     = emac_start_xmit,
3020 };
3021
3022 static const struct net_device_ops emac_gige_netdev_ops = {
3023     .ndo_open       = emac_open,
3024     .ndo_stop       = emac_close,
3025     .ndo_get_stats      = emac_stats,
3026     .ndo_set_rx_mode    = emac_set_multicast_list,
3027     .ndo_eth_ioctl      = emac_ioctl,
3028     .ndo_tx_timeout     = emac_tx_timeout,
3029     .ndo_validate_addr  = eth_validate_addr,
3030     .ndo_set_mac_address    = emac_set_mac_address,
3031     .ndo_start_xmit     = emac_start_xmit_sg,
3032     .ndo_change_mtu     = emac_change_mtu,
3033 };
3034
3035 static int emac_probe(struct platform_device *ofdev)
3036 {
3037     struct net_device *ndev;
3038     struct emac_instance *dev;
3039     struct device_node *np = ofdev->dev.of_node;
3040     struct device_node **blist = NULL;
3041     int err, i;
3042
3043     /* Skip unused/unwired EMACS.  We leave the check for an unused
3044      * property here for now, but new flat device trees should set a
3045      * status property to "disabled" instead.
3046      */
3047     if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
3048         return -ENODEV;
3049
3050     /* Find ourselves in the bootlist if we are there */
3051     for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3052         if (emac_boot_list[i] == np)
3053             blist = &emac_boot_list[i];
3054
3055     /* Allocate our net_device structure */
3056     err = -ENOMEM;
3057     ndev = alloc_etherdev(sizeof(struct emac_instance));
3058     if (!ndev)
3059         goto err_gone;
3060
3061     dev = netdev_priv(ndev);
3062     dev->ndev = ndev;
3063     dev->ofdev = ofdev;
3064     dev->blist = blist;
3065     SET_NETDEV_DEV(ndev, &ofdev->dev);
3066
3067     /* Initialize some embedded data structures */
3068     mutex_init(&dev->mdio_lock);
3069     mutex_init(&dev->link_lock);
3070     spin_lock_init(&dev->lock);
3071     INIT_WORK(&dev->reset_work, emac_reset_work);
3072
3073     /* Init various config data based on device-tree */
3074     err = emac_init_config(dev);
3075     if (err)
3076         goto err_free;
3077
3078     /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
3079     dev->emac_irq = irq_of_parse_and_map(np, 0);
3080     dev->wol_irq = irq_of_parse_and_map(np, 1);
3081     if (!dev->emac_irq) {
3082         printk(KERN_ERR "%pOF: Can't map main interrupt\n", np);
3083         err = -ENODEV;
3084         goto err_free;
3085     }
3086     ndev->irq = dev->emac_irq;
3087
3088     /* Map EMAC regs */
3089     // TODO : platform_get_resource() and devm_ioremap_resource()
3090     dev->emacp = of_iomap(np, 0);
3091     if (dev->emacp == NULL) {
3092         printk(KERN_ERR "%pOF: Can't map device registers!\n", np);
3093         err = -ENOMEM;
3094         goto err_irq_unmap;
3095     }
3096
3097     /* Wait for dependent devices */
3098     err = emac_wait_deps(dev);
3099     if (err) {
3100         printk(KERN_ERR
3101                "%pOF: Timeout waiting for dependent devices\n", np);
3102         /*  display more info about what's missing ? */
3103         goto err_reg_unmap;
3104     }
3105     dev->mal = platform_get_drvdata(dev->mal_dev);
3106     if (dev->mdio_dev != NULL)
3107         dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
3108
3109     /* Register with MAL */
3110     dev->commac.ops = &emac_commac_ops;
3111     dev->commac.dev = dev;
3112     dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
3113     dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
3114     err = mal_register_commac(dev->mal, &dev->commac);
3115     if (err) {
3116         printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n",
3117                np, dev->mal_dev->dev.of_node);
3118         goto err_rel_deps;
3119     }
3120     dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
3121     dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
3122
3123     /* Get pointers to BD rings */
3124     dev->tx_desc =
3125         dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
3126     dev->rx_desc =
3127         dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
3128
3129     DBG(dev, "tx_desc %p" NL, dev->tx_desc);
3130     DBG(dev, "rx_desc %p" NL, dev->rx_desc);
3131
3132     /* Clean rings */
3133     memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
3134     memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
3135     memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
3136     memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
3137
3138     /* Attach to ZMII, if needed */
3139     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
3140         (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
3141         goto err_unreg_commac;
3142
3143     /* Attach to RGMII, if needed */
3144     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
3145         (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
3146         goto err_detach_zmii;
3147
3148     /* Attach to TAH, if needed */
3149     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
3150         (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
3151         goto err_detach_rgmii;
3152
3153     /* Set some link defaults before we can find out real parameters */
3154     dev->phy.speed = SPEED_100;
3155     dev->phy.duplex = DUPLEX_FULL;
3156     dev->phy.autoneg = AUTONEG_DISABLE;
3157     dev->phy.pause = dev->phy.asym_pause = 0;
3158     dev->stop_timeout = STOP_TIMEOUT_100;
3159     INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
3160
3161     /* Some SoCs like APM821xx does not support Half Duplex mode. */
3162     if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
3163         dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
3164                      SUPPORTED_100baseT_Half |
3165                      SUPPORTED_10baseT_Half);
3166     }
3167
3168     /* Find PHY if any */
3169     err = emac_init_phy(dev);
3170     if (err != 0)
3171         goto err_detach_tah;
3172
3173     if (dev->tah_dev) {
3174         ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
3175         ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
3176     }
3177     ndev->watchdog_timeo = 5 * HZ;
3178     if (emac_phy_supports_gige(dev->phy_mode)) {
3179         ndev->netdev_ops = &emac_gige_netdev_ops;
3180         dev->commac.ops = &emac_commac_sg_ops;
3181     } else
3182         ndev->netdev_ops = &emac_netdev_ops;
3183     ndev->ethtool_ops = &emac_ethtool_ops;
3184
3185     /* MTU range: 46 - 1500 or whatever is in OF */
3186     ndev->min_mtu = EMAC_MIN_MTU;
3187     ndev->max_mtu = dev->max_mtu;
3188
3189     netif_carrier_off(ndev);
3190
3191     err = register_netdev(ndev);
3192     if (err) {
3193         printk(KERN_ERR "%pOF: failed to register net device (%d)!\n",
3194                np, err);
3195         goto err_detach_tah;
3196     }
3197
3198     /* Set our drvdata last as we don't want them visible until we are
3199      * fully initialized
3200      */
3201     wmb();
3202     platform_set_drvdata(ofdev, dev);
3203
3204     /* There's a new kid in town ! Let's tell everybody */
3205     wake_up_all(&emac_probe_wait);
3206
3207
3208     printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n",
3209            ndev->name, dev->cell_index, np, ndev->dev_addr);
3210
3211     if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII)
3212         printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
3213
3214     if (dev->phy.address >= 0)
3215         printk("%s: found %s PHY (0x%02x)\n", ndev->name,
3216                dev->phy.def->name, dev->phy.address);
3217
3218     /* Life is good */
3219     return 0;
3220
3221     /* I have a bad feeling about this ... */
3222
3223  err_detach_tah:
3224     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3225         tah_detach(dev->tah_dev, dev->tah_port);
3226  err_detach_rgmii:
3227     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3228         rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3229  err_detach_zmii:
3230     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3231         zmii_detach(dev->zmii_dev, dev->zmii_port);
3232  err_unreg_commac:
3233     mal_unregister_commac(dev->mal, &dev->commac);
3234  err_rel_deps:
3235     emac_put_deps(dev);
3236  err_reg_unmap:
3237     iounmap(dev->emacp);
3238  err_irq_unmap:
3239     if (dev->wol_irq)
3240         irq_dispose_mapping(dev->wol_irq);
3241     if (dev->emac_irq)
3242         irq_dispose_mapping(dev->emac_irq);
3243  err_free:
3244     free_netdev(ndev);
3245  err_gone:
3246     /* if we were on the bootlist, remove us as we won't show up and
3247      * wake up all waiters to notify them in case they were waiting
3248      * on us
3249      */
3250     if (blist) {
3251         *blist = NULL;
3252         wake_up_all(&emac_probe_wait);
3253     }
3254     return err;
3255 }
3256
3257 static int emac_remove(struct platform_device *ofdev)
3258 {
3259     struct emac_instance *dev = platform_get_drvdata(ofdev);
3260
3261     DBG(dev, "remove" NL);
3262
3263     unregister_netdev(dev->ndev);
3264
3265     cancel_work_sync(&dev->reset_work);
3266
3267     if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3268         tah_detach(dev->tah_dev, dev->tah_port);
3269     if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3270         rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3271     if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3272         zmii_detach(dev->zmii_dev, dev->zmii_port);
3273
3274     if (dev->phy_dev)
3275         phy_disconnect(dev->phy_dev);
3276
3277     if (dev->mii_bus)
3278         mdiobus_unregister(dev->mii_bus);
3279
3280     busy_phy_map &= ~(1 << dev->phy.address);
3281     DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
3282
3283     mal_unregister_commac(dev->mal, &dev->commac);
3284     emac_put_deps(dev);
3285
3286     iounmap(dev->emacp);
3287
3288     if (dev->wol_irq)
3289         irq_dispose_mapping(dev->wol_irq);
3290     if (dev->emac_irq)
3291         irq_dispose_mapping(dev->emac_irq);
3292
3293     free_netdev(dev->ndev);
3294
3295     return 0;
3296 }
3297
3298 /* XXX Features in here should be replaced by properties... */
3299 static const struct of_device_id emac_match[] =
3300 {
3301     {
3302         .type       = "network",
3303         .compatible = "ibm,emac",
3304     },
3305     {
3306         .type       = "network",
3307         .compatible = "ibm,emac4",
3308     },
3309     {
3310         .type       = "network",
3311         .compatible = "ibm,emac4sync",
3312     },
3313     {},
3314 };
3315 MODULE_DEVICE_TABLE(of, emac_match);
3316
3317 static struct platform_driver emac_driver = {
3318     .driver = {
3319         .name = "emac",
3320         .of_match_table = emac_match,
3321     },
3322     .probe = emac_probe,
3323     .remove = emac_remove,
3324 };
3325
3326 static void __init emac_make_bootlist(void)
3327 {
3328     struct device_node *np = NULL;
3329     int j, max, i = 0;
3330     int cell_indices[EMAC_BOOT_LIST_SIZE];
3331
3332     /* Collect EMACs */
3333     while((np = of_find_all_nodes(np)) != NULL) {
3334         const u32 *idx;
3335
3336         if (of_match_node(emac_match, np) == NULL)
3337             continue;
3338         if (of_get_property(np, "unused", NULL))
3339             continue;
3340         idx = of_get_property(np, "cell-index", NULL);
3341         if (idx == NULL)
3342             continue;
3343         cell_indices[i] = *idx;
3344         emac_boot_list[i++] = of_node_get(np);
3345         if (i >= EMAC_BOOT_LIST_SIZE) {
3346             of_node_put(np);
3347             break;
3348         }
3349     }
3350     max = i;
3351
3352     /* Bubble sort them (doh, what a creative algorithm :-) */
3353     for (i = 0; max > 1 && (i < (max - 1)); i++)
3354         for (j = i; j < max; j++) {
3355             if (cell_indices[i] > cell_indices[j]) {
3356                 swap(emac_boot_list[i], emac_boot_list[j]);
3357                 swap(cell_indices[i], cell_indices[j]);
3358             }
3359         }
3360 }
3361
3362 static int __init emac_init(void)
3363 {
3364     int rc;
3365
3366     printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3367
3368     /* Build EMAC boot list */
3369     emac_make_bootlist();
3370
3371     /* Init submodules */
3372     rc = mal_init();
3373     if (rc)
3374         goto err;
3375     rc = zmii_init();
3376     if (rc)
3377         goto err_mal;
3378     rc = rgmii_init();
3379     if (rc)
3380         goto err_zmii;
3381     rc = tah_init();
3382     if (rc)
3383         goto err_rgmii;
3384     rc = platform_driver_register(&emac_driver);
3385     if (rc)
3386         goto err_tah;
3387
3388     return 0;
3389
3390  err_tah:
3391     tah_exit();
3392  err_rgmii:
3393     rgmii_exit();
3394  err_zmii:
3395     zmii_exit();
3396  err_mal:
3397     mal_exit();
3398  err:
3399     return rc;
3400 }
3401
3402 static void __exit emac_exit(void)
3403 {
3404     int i;
3405
3406     platform_driver_unregister(&emac_driver);
3407
3408     tah_exit();
3409     rgmii_exit();
3410     zmii_exit();
3411     mal_exit();
3412
3413     /* Destroy EMAC boot list */
3414     for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3415         of_node_put(emac_boot_list[i]);
3416 }
3417
3418 module_init(emac_init);
3419 module_exit(emac_exit);