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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/drivers/net/ethernet/ibm/ehea/ehea_hw.h
0004  *
0005  *  eHEA ethernet device driver for IBM eServer System p
0006  *
0007  *  (C) Copyright IBM Corp. 2006
0008  *
0009  *  Authors:
0010  *       Christoph Raisch <raisch@de.ibm.com>
0011  *       Jan-Bernd Themann <themann@de.ibm.com>
0012  *       Thomas Klein <tklein@de.ibm.com>
0013  */
0014 
0015 #ifndef __EHEA_HW_H__
0016 #define __EHEA_HW_H__
0017 
0018 #define QPX_SQA_VALUE   EHEA_BMASK_IBM(48, 63)
0019 #define QPX_RQ1A_VALUE  EHEA_BMASK_IBM(48, 63)
0020 #define QPX_RQ2A_VALUE  EHEA_BMASK_IBM(48, 63)
0021 #define QPX_RQ3A_VALUE  EHEA_BMASK_IBM(48, 63)
0022 
0023 #define QPTEMM_OFFSET(x) offsetof(struct ehea_qptemm, x)
0024 
0025 struct ehea_qptemm {
0026     u64 qpx_hcr;
0027     u64 qpx_c;
0028     u64 qpx_herr;
0029     u64 qpx_aer;
0030     u64 qpx_sqa;
0031     u64 qpx_sqc;
0032     u64 qpx_rq1a;
0033     u64 qpx_rq1c;
0034     u64 qpx_st;
0035     u64 qpx_aerr;
0036     u64 qpx_tenure;
0037     u64 qpx_reserved1[(0x098 - 0x058) / 8];
0038     u64 qpx_portp;
0039     u64 qpx_reserved2[(0x100 - 0x0A0) / 8];
0040     u64 qpx_t;
0041     u64 qpx_sqhp;
0042     u64 qpx_sqptp;
0043     u64 qpx_reserved3[(0x140 - 0x118) / 8];
0044     u64 qpx_sqwsize;
0045     u64 qpx_reserved4[(0x170 - 0x148) / 8];
0046     u64 qpx_sqsize;
0047     u64 qpx_reserved5[(0x1B0 - 0x178) / 8];
0048     u64 qpx_sigt;
0049     u64 qpx_wqecnt;
0050     u64 qpx_rq1hp;
0051     u64 qpx_rq1ptp;
0052     u64 qpx_rq1size;
0053     u64 qpx_reserved6[(0x220 - 0x1D8) / 8];
0054     u64 qpx_rq1wsize;
0055     u64 qpx_reserved7[(0x240 - 0x228) / 8];
0056     u64 qpx_pd;
0057     u64 qpx_scqn;
0058     u64 qpx_rcqn;
0059     u64 qpx_aeqn;
0060     u64 reserved49;
0061     u64 qpx_ram;
0062     u64 qpx_reserved8[(0x300 - 0x270) / 8];
0063     u64 qpx_rq2a;
0064     u64 qpx_rq2c;
0065     u64 qpx_rq2hp;
0066     u64 qpx_rq2ptp;
0067     u64 qpx_rq2size;
0068     u64 qpx_rq2wsize;
0069     u64 qpx_rq2th;
0070     u64 qpx_rq3a;
0071     u64 qpx_rq3c;
0072     u64 qpx_rq3hp;
0073     u64 qpx_rq3ptp;
0074     u64 qpx_rq3size;
0075     u64 qpx_rq3wsize;
0076     u64 qpx_rq3th;
0077     u64 qpx_lpn;
0078     u64 qpx_reserved9[(0x400 - 0x378) / 8];
0079     u64 reserved_ext[(0x500 - 0x400) / 8];
0080     u64 reserved2[(0x1000 - 0x500) / 8];
0081 };
0082 
0083 #define MRx_HCR_LPARID_VALID EHEA_BMASK_IBM(0, 0)
0084 
0085 #define MRMWMM_OFFSET(x) offsetof(struct ehea_mrmwmm, x)
0086 
0087 struct ehea_mrmwmm {
0088     u64 mrx_hcr;
0089     u64 mrx_c;
0090     u64 mrx_herr;
0091     u64 mrx_aer;
0092     u64 mrx_pp;
0093     u64 reserved1;
0094     u64 reserved2;
0095     u64 reserved3;
0096     u64 reserved4[(0x200 - 0x40) / 8];
0097     u64 mrx_ctl[64];
0098 };
0099 
0100 #define QPEDMM_OFFSET(x) offsetof(struct ehea_qpedmm, x)
0101 
0102 struct ehea_qpedmm {
0103 
0104     u64 reserved0[(0x400) / 8];
0105     u64 qpedx_phh;
0106     u64 qpedx_ppsgp;
0107     u64 qpedx_ppsgu;
0108     u64 qpedx_ppdgp;
0109     u64 qpedx_ppdgu;
0110     u64 qpedx_aph;
0111     u64 qpedx_apsgp;
0112     u64 qpedx_apsgu;
0113     u64 qpedx_apdgp;
0114     u64 qpedx_apdgu;
0115     u64 qpedx_apav;
0116     u64 qpedx_apsav;
0117     u64 qpedx_hcr;
0118     u64 reserved1[4];
0119     u64 qpedx_rrl0;
0120     u64 qpedx_rrrkey0;
0121     u64 qpedx_rrva0;
0122     u64 reserved2;
0123     u64 qpedx_rrl1;
0124     u64 qpedx_rrrkey1;
0125     u64 qpedx_rrva1;
0126     u64 reserved3;
0127     u64 qpedx_rrl2;
0128     u64 qpedx_rrrkey2;
0129     u64 qpedx_rrva2;
0130     u64 reserved4;
0131     u64 qpedx_rrl3;
0132     u64 qpedx_rrrkey3;
0133     u64 qpedx_rrva3;
0134 };
0135 
0136 #define CQX_FECADDER EHEA_BMASK_IBM(32, 63)
0137 #define CQX_FEC_CQE_CNT EHEA_BMASK_IBM(32, 63)
0138 #define CQX_N1_GENERATE_COMP_EVENT EHEA_BMASK_IBM(0, 0)
0139 #define CQX_EP_EVENT_PENDING EHEA_BMASK_IBM(0, 0)
0140 
0141 #define CQTEMM_OFFSET(x) offsetof(struct ehea_cqtemm, x)
0142 
0143 struct ehea_cqtemm {
0144     u64 cqx_hcr;
0145     u64 cqx_c;
0146     u64 cqx_herr;
0147     u64 cqx_aer;
0148     u64 cqx_ptp;
0149     u64 cqx_tp;
0150     u64 cqx_fec;
0151     u64 cqx_feca;
0152     u64 cqx_ep;
0153     u64 cqx_eq;
0154     u64 reserved1;
0155     u64 cqx_n0;
0156     u64 cqx_n1;
0157     u64 reserved2[(0x1000 - 0x60) / 8];
0158 };
0159 
0160 #define EQTEMM_OFFSET(x) offsetof(struct ehea_eqtemm, x)
0161 
0162 struct ehea_eqtemm {
0163     u64 eqx_hcr;
0164     u64 eqx_c;
0165     u64 eqx_herr;
0166     u64 eqx_aer;
0167     u64 eqx_ptp;
0168     u64 eqx_tp;
0169     u64 eqx_ssba;
0170     u64 eqx_psba;
0171     u64 eqx_cec;
0172     u64 eqx_meql;
0173     u64 eqx_xisbi;
0174     u64 eqx_xisc;
0175     u64 eqx_it;
0176 };
0177 
0178 /*
0179  * These access functions will be changed when the dissuccsion about
0180  * the new access methods for POWER has settled.
0181  */
0182 
0183 static inline u64 epa_load(struct h_epa epa, u32 offset)
0184 {
0185     return __raw_readq((void __iomem *)(epa.addr + offset));
0186 }
0187 
0188 static inline void epa_store(struct h_epa epa, u32 offset, u64 value)
0189 {
0190     __raw_writeq(value, (void __iomem *)(epa.addr + offset));
0191     epa_load(epa, offset);  /* synchronize explicitly to eHEA */
0192 }
0193 
0194 static inline void epa_store_acc(struct h_epa epa, u32 offset, u64 value)
0195 {
0196     __raw_writeq(value, (void __iomem *)(epa.addr + offset));
0197 }
0198 
0199 #define epa_store_cq(epa, offset, value)\
0200     epa_store(epa, CQTEMM_OFFSET(offset), value)
0201 #define epa_load_cq(epa, offset)\
0202     epa_load(epa, CQTEMM_OFFSET(offset))
0203 
0204 static inline void ehea_update_sqa(struct ehea_qp *qp, u16 nr_wqes)
0205 {
0206     struct h_epa epa = qp->epas.kernel;
0207     epa_store_acc(epa, QPTEMM_OFFSET(qpx_sqa),
0208               EHEA_BMASK_SET(QPX_SQA_VALUE, nr_wqes));
0209 }
0210 
0211 static inline void ehea_update_rq3a(struct ehea_qp *qp, u16 nr_wqes)
0212 {
0213     struct h_epa epa = qp->epas.kernel;
0214     epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq3a),
0215               EHEA_BMASK_SET(QPX_RQ1A_VALUE, nr_wqes));
0216 }
0217 
0218 static inline void ehea_update_rq2a(struct ehea_qp *qp, u16 nr_wqes)
0219 {
0220     struct h_epa epa = qp->epas.kernel;
0221     epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq2a),
0222               EHEA_BMASK_SET(QPX_RQ2A_VALUE, nr_wqes));
0223 }
0224 
0225 static inline void ehea_update_rq1a(struct ehea_qp *qp, u16 nr_wqes)
0226 {
0227     struct h_epa epa = qp->epas.kernel;
0228     epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq1a),
0229               EHEA_BMASK_SET(QPX_RQ3A_VALUE, nr_wqes));
0230 }
0231 
0232 static inline void ehea_update_feca(struct ehea_cq *cq, u32 nr_cqes)
0233 {
0234     struct h_epa epa = cq->epas.kernel;
0235     epa_store_acc(epa, CQTEMM_OFFSET(cqx_feca),
0236               EHEA_BMASK_SET(CQX_FECADDER, nr_cqes));
0237 }
0238 
0239 static inline void ehea_reset_cq_n1(struct ehea_cq *cq)
0240 {
0241     struct h_epa epa = cq->epas.kernel;
0242     epa_store_cq(epa, cqx_n1,
0243              EHEA_BMASK_SET(CQX_N1_GENERATE_COMP_EVENT, 1));
0244 }
0245 
0246 static inline void ehea_reset_cq_ep(struct ehea_cq *my_cq)
0247 {
0248     struct h_epa epa = my_cq->epas.kernel;
0249     epa_store_acc(epa, CQTEMM_OFFSET(cqx_ep),
0250               EHEA_BMASK_SET(CQX_EP_EVENT_PENDING, 0));
0251 }
0252 
0253 #endif  /* __EHEA_HW_H__ */
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