ibm/ehea/ehea.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/drivers/net/ethernet/ibm/ehea/ehea.h
0004  *
0005  *  eHEA ethernet device driver for IBM eServer System p
0006  *
0007  *  (C) Copyright IBM Corp. 2006
0008  *
0009  *  Authors:
0010  *       Christoph Raisch <raisch@de.ibm.com>
0011  *       Jan-Bernd Themann <themann@de.ibm.com>
0012  *       Thomas Klein <tklein@de.ibm.com>
0013  */
0014
0015 #ifndef __EHEA_H__
0016 #define __EHEA_H__
0017
0018 #include <linux/module.h>
0019 #include <linux/ethtool.h>
0020 #include <linux/vmalloc.h>
0021 #include <linux/if_vlan.h>
0022 #include <linux/platform_device.h>
0023
0024 #include <asm/ibmebus.h>
0025 #include <asm/io.h>
0026
0027 #define DRV_NAME    "ehea"
0028 #define DRV_VERSION "EHEA_0107"
0029
0030 /* eHEA capability flags */
0031 #define DLPAR_PORT_ADD_REM 1
0032 #define DLPAR_MEM_ADD      2
0033 #define DLPAR_MEM_REM      4
0034 #define EHEA_CAPABILITIES  (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)
0035
0036 #define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
0037     | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
0038
0039 #define EHEA_MAX_ENTRIES_RQ1 32767
0040 #define EHEA_MAX_ENTRIES_RQ2 16383
0041 #define EHEA_MAX_ENTRIES_RQ3 16383
0042 #define EHEA_MAX_ENTRIES_SQ  32767
0043 #define EHEA_MIN_ENTRIES_QP  127
0044
0045 #define EHEA_SMALL_QUEUES
0046
0047 #ifdef EHEA_SMALL_QUEUES
0048 #define EHEA_MAX_CQE_COUNT      1023
0049 #define EHEA_DEF_ENTRIES_SQ     1023
0050 #define EHEA_DEF_ENTRIES_RQ1    1023
0051 #define EHEA_DEF_ENTRIES_RQ2    1023
0052 #define EHEA_DEF_ENTRIES_RQ3    511
0053 #else
0054 #define EHEA_MAX_CQE_COUNT      4080
0055 #define EHEA_DEF_ENTRIES_SQ     4080
0056 #define EHEA_DEF_ENTRIES_RQ1    8160
0057 #define EHEA_DEF_ENTRIES_RQ2    2040
0058 #define EHEA_DEF_ENTRIES_RQ3    2040
0059 #endif
0060
0061 #define EHEA_MAX_ENTRIES_EQ 20
0062
0063 #define EHEA_SG_SQ  2
0064 #define EHEA_SG_RQ1 1
0065 #define EHEA_SG_RQ2 0
0066 #define EHEA_SG_RQ3 0
0067
0068 #define EHEA_MAX_PACKET_SIZE    9022    /* for jumbo frames */
0069 #define EHEA_RQ2_PKT_SIZE       2048
0070 #define EHEA_L_PKT_SIZE         256 /* low latency */
0071
0072 /* Send completion signaling */
0073
0074 /* Protection Domain Identifier */
0075 #define EHEA_PD_ID        0xaabcdeff
0076
0077 #define EHEA_RQ2_THRESHOLD     1
0078 #define EHEA_RQ3_THRESHOLD     4    /* use RQ3 threshold of 2048 bytes */
0079
0080 #define EHEA_SPEED_10G         10000
0081 #define EHEA_SPEED_1G           1000
0082 #define EHEA_SPEED_100M          100
0083 #define EHEA_SPEED_10M            10
0084 #define EHEA_SPEED_AUTONEG         0
0085
0086 /* Broadcast/Multicast registration types */
0087 #define EHEA_BCMC_SCOPE_ALL 0x08
0088 #define EHEA_BCMC_SCOPE_SINGLE  0x00
0089 #define EHEA_BCMC_MULTICAST 0x04
0090 #define EHEA_BCMC_BROADCAST 0x00
0091 #define EHEA_BCMC_UNTAGGED  0x02
0092 #define EHEA_BCMC_TAGGED    0x00
0093 #define EHEA_BCMC_VLANID_ALL    0x01
0094 #define EHEA_BCMC_VLANID_SINGLE 0x00
0095
0096 #define EHEA_CACHE_LINE          128
0097
0098 /* Memory Regions */
0099 #define EHEA_MR_ACC_CTRL       0x00800000
0100
0101 #define EHEA_BUSMAP_START      0x8000000000000000ULL
0102 #define EHEA_INVAL_ADDR        0xFFFFFFFFFFFFFFFFULL
0103 #define EHEA_DIR_INDEX_SHIFT 13                   /* 8k Entries in 64k block */
0104 #define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
0105 #define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
0106 #define EHEA_MAP_SIZE (0x10000)                   /* currently fixed map size */
0107 #define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)
0108
0109
0110 #define EHEA_WATCH_DOG_TIMEOUT 10*HZ
0111
0112 /* utility functions */
0113
0114 void ehea_dump(void *adr, int len, char *msg);
0115
0116 #define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
0117
0118 #define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
0119
0120 #define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
0121
0122 #define EHEA_BMASK_MASK(mask) \
0123     (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
0124
0125 #define EHEA_BMASK_SET(mask, value) \
0126     ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
0127
0128 #define EHEA_BMASK_GET(mask, value) \
0129     (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
0130
0131 /*
0132  * Generic ehea page
0133  */
0134 struct ehea_page {
0135     u8 entries[PAGE_SIZE];
0136 };
0137
0138 /*
0139  * Generic queue in linux kernel virtual memory
0140  */
0141 struct hw_queue {
0142     u64 current_q_offset;       /* current queue entry */
0143     struct ehea_page **queue_pages; /* array of pages belonging to queue */
0144     u32 qe_size;            /* queue entry size */
0145     u32 queue_length;           /* queue length allocated in bytes */
0146     u32 pagesize;
0147     u32 toggle_state;       /* toggle flag - per page */
0148     u32 reserved;           /* 64 bit alignment */
0149 };
0150
0151 /*
0152  * For pSeries this is a 64bit memory address where
0153  * I/O memory is mapped into CPU address space
0154  */
0155 struct h_epa {
0156     void __iomem *addr;
0157 };
0158
0159 struct h_epa_user {
0160     u64 addr;
0161 };
0162
0163 struct h_epas {
0164     struct h_epa kernel;    /* kernel space accessible resource,
0165                    set to 0 if unused */
0166     struct h_epa_user user; /* user space accessible resource
0167                    set to 0 if unused */
0168 };
0169
0170 /*
0171  * Memory map data structures
0172  */
0173 struct ehea_dir_bmap
0174 {
0175     u64 ent[EHEA_MAP_ENTRIES];
0176 };
0177 struct ehea_top_bmap
0178 {
0179     struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
0180 };
0181 struct ehea_bmap
0182 {
0183     struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
0184 };
0185
0186 struct ehea_qp;
0187 struct ehea_cq;
0188 struct ehea_eq;
0189 struct ehea_port;
0190 struct ehea_av;
0191
0192 /*
0193  * Queue attributes passed to ehea_create_qp()
0194  */
0195 struct ehea_qp_init_attr {
0196     /* input parameter */
0197     u32 qp_token;           /* queue token */
0198     u8 low_lat_rq1;
0199     u8 signalingtype;       /* cqe generation flag */
0200     u8 rq_count;            /* num of receive queues */
0201     u8 eqe_gen;             /* eqe generation flag */
0202     u16 max_nr_send_wqes;   /* max number of send wqes */
0203     u16 max_nr_rwqes_rq1;   /* max number of receive wqes */
0204     u16 max_nr_rwqes_rq2;
0205     u16 max_nr_rwqes_rq3;
0206     u8 wqe_size_enc_sq;
0207     u8 wqe_size_enc_rq1;
0208     u8 wqe_size_enc_rq2;
0209     u8 wqe_size_enc_rq3;
0210     u8 swqe_imm_data_len;   /* immediate data length for swqes */
0211     u16 port_nr;
0212     u16 rq2_threshold;
0213     u16 rq3_threshold;
0214     u64 send_cq_handle;
0215     u64 recv_cq_handle;
0216     u64 aff_eq_handle;
0217
0218     /* output parameter */
0219     u32 qp_nr;
0220     u16 act_nr_send_wqes;
0221     u16 act_nr_rwqes_rq1;
0222     u16 act_nr_rwqes_rq2;
0223     u16 act_nr_rwqes_rq3;
0224     u8 act_wqe_size_enc_sq;
0225     u8 act_wqe_size_enc_rq1;
0226     u8 act_wqe_size_enc_rq2;
0227     u8 act_wqe_size_enc_rq3;
0228     u32 nr_sq_pages;
0229     u32 nr_rq1_pages;
0230     u32 nr_rq2_pages;
0231     u32 nr_rq3_pages;
0232     u32 liobn_sq;
0233     u32 liobn_rq1;
0234     u32 liobn_rq2;
0235     u32 liobn_rq3;
0236 };
0237
0238 /*
0239  * Event Queue attributes, passed as parameter
0240  */
0241 struct ehea_eq_attr {
0242     u32 type;
0243     u32 max_nr_of_eqes;
0244     u8 eqe_gen;        /* generate eqe flag */
0245     u64 eq_handle;
0246     u32 act_nr_of_eqes;
0247     u32 nr_pages;
0248     u32 ist1;          /* Interrupt service token */
0249     u32 ist2;
0250     u32 ist3;
0251     u32 ist4;
0252 };
0253
0254
0255 /*
0256  * Event Queue
0257  */
0258 struct ehea_eq {
0259     struct ehea_adapter *adapter;
0260     struct hw_queue hw_queue;
0261     u64 fw_handle;
0262     struct h_epas epas;
0263     spinlock_t spinlock;
0264     struct ehea_eq_attr attr;
0265 };
0266
0267 /*
0268  * HEA Queues
0269  */
0270 struct ehea_qp {
0271     struct ehea_adapter *adapter;
0272     u64 fw_handle;          /* QP handle for firmware calls */
0273     struct hw_queue hw_squeue;
0274     struct hw_queue hw_rqueue1;
0275     struct hw_queue hw_rqueue2;
0276     struct hw_queue hw_rqueue3;
0277     struct h_epas epas;
0278     struct ehea_qp_init_attr init_attr;
0279 };
0280
0281 /*
0282  * Completion Queue attributes
0283  */
0284 struct ehea_cq_attr {
0285     /* input parameter */
0286     u32 max_nr_of_cqes;
0287     u32 cq_token;
0288     u64 eq_handle;
0289
0290     /* output parameter */
0291     u32 act_nr_of_cqes;
0292     u32 nr_pages;
0293 };
0294
0295 /*
0296  * Completion Queue
0297  */
0298 struct ehea_cq {
0299     struct ehea_adapter *adapter;
0300     u64 fw_handle;
0301     struct hw_queue hw_queue;
0302     struct h_epas epas;
0303     struct ehea_cq_attr attr;
0304 };
0305
0306 /*
0307  * Memory Region
0308  */
0309 struct ehea_mr {
0310     struct ehea_adapter *adapter;
0311     u64 handle;
0312     u64 vaddr;
0313     u32 lkey;
0314 };
0315
0316 /*
0317  * Port state information
0318  */
0319 struct port_stats {
0320     int poll_receive_errors;
0321     int queue_stopped;
0322     int err_tcp_cksum;
0323     int err_ip_cksum;
0324     int err_frame_crc;
0325 };
0326
0327 #define EHEA_IRQ_NAME_SIZE 20
0328
0329 /*
0330  * Queue SKB Array
0331  */
0332 struct ehea_q_skb_arr {
0333     struct sk_buff **arr;       /* skb array for queue */
0334     int len;                    /* array length */
0335     int index;          /* array index */
0336     int os_skbs;            /* rq2/rq3 only: outstanding skbs */
0337 };
0338
0339 /*
0340  * Port resources
0341  */
0342 struct ehea_port_res {
0343     struct napi_struct napi;
0344     struct port_stats p_stats;
0345     struct ehea_mr send_mr;         /* send memory region */
0346     struct ehea_mr recv_mr;         /* receive memory region */
0347     struct ehea_port *port;
0348     char int_recv_name[EHEA_IRQ_NAME_SIZE];
0349     char int_send_name[EHEA_IRQ_NAME_SIZE];
0350     struct ehea_qp *qp;
0351     struct ehea_cq *send_cq;
0352     struct ehea_cq *recv_cq;
0353     struct ehea_eq *eq;
0354     struct ehea_q_skb_arr rq1_skba;
0355     struct ehea_q_skb_arr rq2_skba;
0356     struct ehea_q_skb_arr rq3_skba;
0357     struct ehea_q_skb_arr sq_skba;
0358     int sq_skba_size;
0359     int swqe_refill_th;
0360     atomic_t swqe_avail;
0361     int swqe_ll_count;
0362     u32 swqe_id_counter;
0363     u64 tx_packets;
0364     u64 tx_bytes;
0365     u64 rx_packets;
0366     u64 rx_bytes;
0367     int sq_restart_flag;
0368 };
0369
0370
0371 #define EHEA_MAX_PORTS 16
0372
0373 #define EHEA_NUM_PORTRES_FW_HANDLES    6  /* QP handle, SendCQ handle,
0374                          RecvCQ handle, EQ handle,
0375                          SendMR handle, RecvMR handle */
0376 #define EHEA_NUM_PORT_FW_HANDLES       1  /* EQ handle */
0377 #define EHEA_NUM_ADAPTER_FW_HANDLES    2  /* MR handle, NEQ handle */
0378
0379 struct ehea_adapter {
0380     u64 handle;
0381     struct platform_device *ofdev;
0382     struct ehea_port *port[EHEA_MAX_PORTS];
0383     struct ehea_eq *neq;       /* notification event queue */
0384     struct tasklet_struct neq_tasklet;
0385     struct ehea_mr mr;
0386     u32 pd;                    /* protection domain */
0387     u64 max_mc_mac;            /* max number of multicast mac addresses */
0388     int active_ports;
0389     struct list_head list;
0390 };
0391
0392
0393 struct ehea_mc_list {
0394     struct list_head list;
0395     u64 macaddr;
0396 };
0397
0398 /* kdump support */
0399 struct ehea_fw_handle_entry {
0400     u64 adh;               /* Adapter Handle */
0401     u64 fwh;               /* Firmware Handle */
0402 };
0403
0404 struct ehea_fw_handle_array {
0405     struct ehea_fw_handle_entry *arr;
0406     int num_entries;
0407     struct mutex lock;
0408 };
0409
0410 struct ehea_bcmc_reg_entry {
0411     u64 adh;               /* Adapter Handle */
0412     u32 port_id;           /* Logical Port Id */
0413     u8 reg_type;           /* Registration Type */
0414     u64 macaddr;
0415 };
0416
0417 struct ehea_bcmc_reg_array {
0418     struct ehea_bcmc_reg_entry *arr;
0419     int num_entries;
0420     spinlock_t lock;
0421 };
0422
0423 #define EHEA_PORT_UP 1
0424 #define EHEA_PORT_DOWN 0
0425 #define EHEA_PHY_LINK_UP 1
0426 #define EHEA_PHY_LINK_DOWN 0
0427 #define EHEA_MAX_PORT_RES 16
0428 struct ehea_port {
0429     struct ehea_adapter *adapter;    /* adapter that owns this port */
0430     struct net_device *netdev;
0431     struct rtnl_link_stats64 stats;
0432     struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
0433     struct platform_device  ofdev; /* Open Firmware Device */
0434     struct ehea_mc_list *mc_list;    /* Multicast MAC addresses */
0435     struct ehea_eq *qp_eq;
0436     struct work_struct reset_task;
0437     struct delayed_work stats_work;
0438     struct mutex port_lock;
0439     char int_aff_name[EHEA_IRQ_NAME_SIZE];
0440     int allmulti;            /* Indicates IFF_ALLMULTI state */
0441     int promisc;             /* Indicates IFF_PROMISC state */
0442     int num_mcs;
0443     int resets;
0444     unsigned long flags;
0445     u64 mac_addr;
0446     u32 logical_port_id;
0447     u32 port_speed;
0448     u32 msg_enable;
0449     u32 sig_comp_iv;
0450     u32 state;
0451     u8 phy_link;
0452     u8 full_duplex;
0453     u8 autoneg;
0454     u8 num_def_qps;
0455     wait_queue_head_t swqe_avail_wq;
0456     wait_queue_head_t restart_wq;
0457 };
0458
0459 struct port_res_cfg {
0460     int max_entries_rcq;
0461     int max_entries_scq;
0462     int max_entries_sq;
0463     int max_entries_rq1;
0464     int max_entries_rq2;
0465     int max_entries_rq3;
0466 };
0467
0468 enum ehea_flag_bits {
0469     __EHEA_STOP_XFER,
0470     __EHEA_DISABLE_PORT_RESET
0471 };
0472
0473 void ehea_set_ethtool_ops(struct net_device *netdev);
0474 int ehea_sense_port_attr(struct ehea_port *port);
0475 int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
0476
0477 #endif  /* __EHEA_H__ */