hns3/hns3vf/hclgevf_main.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Copyright (c) 2016-2017 Hisilicon Limited. */
0003
0004 #ifndef __HCLGEVF_MAIN_H
0005 #define __HCLGEVF_MAIN_H
0006 #include <linux/fs.h>
0007 #include <linux/if_vlan.h>
0008 #include <linux/types.h>
0009 #include <net/devlink.h>
0010 #include "hclge_mbx.h"
0011 #include "hclgevf_cmd.h"
0012 #include "hnae3.h"
0013 #include "hclge_comm_rss.h"
0014 #include "hclge_comm_tqp_stats.h"
0015
0016 #define HCLGEVF_MOD_VERSION "1.0"
0017 #define HCLGEVF_DRIVER_NAME "hclgevf"
0018
0019 #define HCLGEVF_MAX_VLAN_ID 4095
0020 #define HCLGEVF_MISC_VECTOR_NUM     0
0021
0022 #define HCLGEVF_INVALID_VPORT       0xffff
0023 #define HCLGEVF_GENERAL_TASK_INTERVAL     5
0024 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL  2
0025
0026 /* This number in actual depends upon the total number of VFs
0027  * created by physical function. But the maximum number of
0028  * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
0029  */
0030 #define HCLGEVF_MAX_VF_VECTOR_NUM   (32 + 1)
0031
0032 #define HCLGEVF_VECTOR_REG_BASE     0x20000
0033 #define HCLGEVF_MISC_VECTOR_REG_BASE    0x20400
0034 #define HCLGEVF_VECTOR_REG_OFFSET   0x4
0035 #define HCLGEVF_VECTOR_VF_OFFSET        0x100000
0036
0037 /* bar registers for common func */
0038 #define HCLGEVF_GRO_EN_REG          0x28000
0039 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG       0x28008
0040
0041 /* bar registers for rcb */
0042 #define HCLGEVF_RING_RX_ADDR_L_REG      0x80000
0043 #define HCLGEVF_RING_RX_ADDR_H_REG      0x80004
0044 #define HCLGEVF_RING_RX_BD_NUM_REG      0x80008
0045 #define HCLGEVF_RING_RX_BD_LENGTH_REG       0x8000C
0046 #define HCLGEVF_RING_RX_MERGE_EN_REG        0x80014
0047 #define HCLGEVF_RING_RX_TAIL_REG        0x80018
0048 #define HCLGEVF_RING_RX_HEAD_REG        0x8001C
0049 #define HCLGEVF_RING_RX_FBD_NUM_REG     0x80020
0050 #define HCLGEVF_RING_RX_OFFSET_REG      0x80024
0051 #define HCLGEVF_RING_RX_FBD_OFFSET_REG      0x80028
0052 #define HCLGEVF_RING_RX_STASH_REG       0x80030
0053 #define HCLGEVF_RING_RX_BD_ERR_REG      0x80034
0054 #define HCLGEVF_RING_TX_ADDR_L_REG      0x80040
0055 #define HCLGEVF_RING_TX_ADDR_H_REG      0x80044
0056 #define HCLGEVF_RING_TX_BD_NUM_REG      0x80048
0057 #define HCLGEVF_RING_TX_PRIORITY_REG        0x8004C
0058 #define HCLGEVF_RING_TX_TC_REG          0x80050
0059 #define HCLGEVF_RING_TX_MERGE_EN_REG        0x80054
0060 #define HCLGEVF_RING_TX_TAIL_REG        0x80058
0061 #define HCLGEVF_RING_TX_HEAD_REG        0x8005C
0062 #define HCLGEVF_RING_TX_FBD_NUM_REG     0x80060
0063 #define HCLGEVF_RING_TX_OFFSET_REG      0x80064
0064 #define HCLGEVF_RING_TX_EBD_NUM_REG     0x80068
0065 #define HCLGEVF_RING_TX_EBD_OFFSET_REG      0x80070
0066 #define HCLGEVF_RING_TX_BD_ERR_REG      0x80074
0067 #define HCLGEVF_RING_EN_REG         0x80090
0068
0069 /* bar registers for tqp interrupt */
0070 #define HCLGEVF_TQP_INTR_CTRL_REG       0x20000
0071 #define HCLGEVF_TQP_INTR_GL0_REG        0x20100
0072 #define HCLGEVF_TQP_INTR_GL1_REG        0x20200
0073 #define HCLGEVF_TQP_INTR_GL2_REG        0x20300
0074 #define HCLGEVF_TQP_INTR_RL_REG         0x20900
0075
0076 /* CMDQ register bits for RX event(=MBX event) */
0077 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B   1
0078 /* RST register bits for RESET event */
0079 #define HCLGEVF_VECTOR0_RST_INT_B   2
0080
0081 #define HCLGEVF_TQP_RESET_TRY_TIMES 10
0082 /* Reset related Registers */
0083 #define HCLGEVF_RST_ING         0x20C00
0084 #define HCLGEVF_FUN_RST_ING_BIT     BIT(0)
0085 #define HCLGEVF_GLOBAL_RST_ING_BIT  BIT(5)
0086 #define HCLGEVF_CORE_RST_ING_BIT    BIT(6)
0087 #define HCLGEVF_IMP_RST_ING_BIT     BIT(7)
0088 #define HCLGEVF_RST_ING_BITS \
0089     (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
0090      HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
0091
0092 #define HCLGEVF_VF_RST_ING      0x07008
0093 #define HCLGEVF_VF_RST_ING_BIT      BIT(16)
0094
0095 #define HCLGEVF_WAIT_RESET_DONE     100
0096
0097 #define HCLGEVF_RSS_IND_TBL_SIZE        512
0098
0099 #define HCLGEVF_TQP_MEM_SIZE        0x10000
0100 #define HCLGEVF_MEM_BAR         4
0101 /* in the bar4, the first half is for roce, and the second half is for nic */
0102 #define HCLGEVF_NIC_MEM_OFFSET(hdev)    \
0103     (pci_resource_len((hdev)->pdev, HCLGEVF_MEM_BAR) >> 1)
0104 #define HCLGEVF_TQP_MEM_OFFSET(hdev, i)     \
0105     (HCLGEVF_NIC_MEM_OFFSET(hdev) + HCLGEVF_TQP_MEM_SIZE * (i))
0106
0107 #define HCLGEVF_MAC_MAX_FRAME       9728
0108
0109 #define HCLGEVF_STATS_TIMER_INTERVAL    36U
0110
0111 #define hclgevf_read_dev(a, reg) \
0112     hclge_comm_read_reg((a)->hw.io_base, reg)
0113 #define hclgevf_write_dev(a, reg, value) \
0114     hclge_comm_write_reg((a)->hw.io_base, reg, value)
0115
0116 enum hclgevf_evt_cause {
0117     HCLGEVF_VECTOR0_EVENT_RST,
0118     HCLGEVF_VECTOR0_EVENT_MBX,
0119     HCLGEVF_VECTOR0_EVENT_OTHER,
0120 };
0121
0122 /* states of hclgevf device & tasks */
0123 enum hclgevf_states {
0124     /* device states */
0125     HCLGEVF_STATE_DOWN,
0126     HCLGEVF_STATE_DISABLED,
0127     HCLGEVF_STATE_IRQ_INITED,
0128     HCLGEVF_STATE_REMOVING,
0129     HCLGEVF_STATE_NIC_REGISTERED,
0130     HCLGEVF_STATE_ROCE_REGISTERED,
0131     HCLGEVF_STATE_SERVICE_INITED,
0132     /* task states */
0133     HCLGEVF_STATE_RST_SERVICE_SCHED,
0134     HCLGEVF_STATE_RST_HANDLING,
0135     HCLGEVF_STATE_MBX_SERVICE_SCHED,
0136     HCLGEVF_STATE_MBX_HANDLING,
0137     HCLGEVF_STATE_LINK_UPDATING,
0138     HCLGEVF_STATE_PROMISC_CHANGED,
0139     HCLGEVF_STATE_RST_FAIL,
0140     HCLGEVF_STATE_PF_PUSH_LINK_STATUS,
0141 };
0142
0143 struct hclgevf_mac {
0144     u8 media_type;
0145     u8 module_type;
0146     u8 mac_addr[ETH_ALEN];
0147     int link;
0148     u8 duplex;
0149     u32 speed;
0150     u64 supported;
0151     u64 advertising;
0152 };
0153
0154 struct hclgevf_hw {
0155     struct hclge_comm_hw hw;
0156     int num_vec;
0157     struct hclgevf_mac mac;
0158 };
0159
0160 struct hclgevf_cfg {
0161     u8 tc_num;
0162     u16 tqp_desc_num;
0163     u16 rx_buf_len;
0164     u8 phy_addr;
0165     u8 media_type;
0166     u8 mac_addr[ETH_ALEN];
0167     u32 numa_node_map;
0168 };
0169
0170 struct hclgevf_misc_vector {
0171     u8 __iomem *addr;
0172     int vector_irq;
0173     char name[HNAE3_INT_NAME_LEN];
0174 };
0175
0176 struct hclgevf_rst_stats {
0177     u32 rst_cnt;            /* the number of reset */
0178     u32 vf_func_rst_cnt;        /* the number of VF function reset */
0179     u32 flr_rst_cnt;        /* the number of FLR */
0180     u32 vf_rst_cnt;         /* the number of VF reset */
0181     u32 rst_done_cnt;       /* the number of reset completed */
0182     u32 hw_rst_done_cnt;        /* the number of HW reset completed */
0183     u32 rst_fail_cnt;       /* the number of VF reset fail */
0184 };
0185
0186 enum HCLGEVF_MAC_ADDR_TYPE {
0187     HCLGEVF_MAC_ADDR_UC,
0188     HCLGEVF_MAC_ADDR_MC
0189 };
0190
0191 enum HCLGEVF_MAC_NODE_STATE {
0192     HCLGEVF_MAC_TO_ADD,
0193     HCLGEVF_MAC_TO_DEL,
0194     HCLGEVF_MAC_ACTIVE
0195 };
0196
0197 struct hclgevf_mac_addr_node {
0198     struct list_head node;
0199     enum HCLGEVF_MAC_NODE_STATE state;
0200     u8 mac_addr[ETH_ALEN];
0201 };
0202
0203 struct hclgevf_mac_table_cfg {
0204     spinlock_t mac_list_lock; /* protect mac address need to add/detele */
0205     struct list_head uc_mac_list;
0206     struct list_head mc_mac_list;
0207 };
0208
0209 struct hclgevf_dev {
0210     struct pci_dev *pdev;
0211     struct hnae3_ae_dev *ae_dev;
0212     struct hclgevf_hw hw;
0213     struct hclgevf_misc_vector misc_vector;
0214     struct hclge_comm_rss_cfg rss_cfg;
0215     unsigned long state;
0216     unsigned long flr_state;
0217     unsigned long default_reset_request;
0218     unsigned long last_reset_time;
0219     enum hnae3_reset_type reset_level;
0220     unsigned long reset_pending;
0221     enum hnae3_reset_type reset_type;
0222
0223 #define HCLGEVF_RESET_REQUESTED     0
0224 #define HCLGEVF_RESET_PENDING       1
0225     unsigned long reset_state;  /* requested, pending */
0226     struct hclgevf_rst_stats rst_stats;
0227     u32 reset_attempts;
0228     struct semaphore reset_sem; /* protect reset process */
0229
0230     u32 fw_version;
0231     u16 mbx_api_version;
0232     u16 num_tqps;       /* num task queue pairs of this VF */
0233
0234     u16 alloc_rss_size; /* allocated RSS task queue */
0235     u16 rss_size_max;   /* HW defined max RSS task queue */
0236
0237     u16 num_alloc_vport;    /* num vports this driver supports */
0238     u32 numa_node_mask;
0239     u16 rx_buf_len;
0240     u16 num_tx_desc;    /* desc num of per tx queue */
0241     u16 num_rx_desc;    /* desc num of per rx queue */
0242     u8 hw_tc_map;
0243     u8 has_pf_mac;
0244
0245     u16 num_msi;
0246     u16 num_msi_left;
0247     u16 num_msi_used;
0248     u16 num_nic_msix;   /* Num of nic vectors for this VF */
0249     u16 num_roce_msix;  /* Num of roce vectors for this VF */
0250     u16 roce_base_msix_offset;
0251     u16 *vector_status;
0252     int *vector_irq;
0253
0254     bool gro_en;
0255
0256     unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
0257
0258     struct hclgevf_mac_table_cfg mac_table;
0259
0260     struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
0261     struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
0262
0263     struct delayed_work service_task;
0264
0265     struct hclge_comm_tqp *htqp;
0266
0267     struct hnae3_handle nic;
0268     struct hnae3_handle roce;
0269
0270     struct hnae3_client *nic_client;
0271     struct hnae3_client *roce_client;
0272     u32 flag;
0273     unsigned long serv_processed_cnt;
0274     unsigned long last_serv_processed;
0275
0276     struct devlink *devlink;
0277 };
0278
0279 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
0280 {
0281     return !!hdev->reset_pending;
0282 }
0283
0284 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
0285              struct hclge_vf_to_pf_msg *send_msg, bool need_resp,
0286              u8 *resp_data, u16 resp_len);
0287 void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
0288 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
0289
0290 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
0291 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
0292                  u8 duplex);
0293 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
0294 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
0295 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
0296             struct hclge_mbx_port_base_vlan *port_base_vlan);
0297 #endif