hns3/hns3vf/hclgevf_cmd.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Copyright (c) 2016-2017 Hisilicon Limited. */
0003
0004 #ifndef __HCLGEVF_CMD_H
0005 #define __HCLGEVF_CMD_H
0006 #include <linux/io.h>
0007 #include <linux/types.h>
0008 #include "hnae3.h"
0009 #include "hclge_comm_cmd.h"
0010
0011 #define HCLGEVF_CMDQ_RX_INVLD_B     0
0012 #define HCLGEVF_CMDQ_RX_OUTVLD_B    1
0013
0014 struct hclgevf_hw;
0015 struct hclgevf_dev;
0016
0017 #define HCLGEVF_SYNC_RX_RING_HEAD_EN_B  4
0018
0019 #define HCLGEVF_TQP_REG_OFFSET      0x80000
0020 #define HCLGEVF_TQP_REG_SIZE        0x200
0021
0022 #define HCLGEVF_TQP_MAX_SIZE_DEV_V2 1024
0023 #define HCLGEVF_TQP_EXT_REG_OFFSET  0x100
0024
0025 struct hclgevf_tqp_map {
0026     __le16 tqp_id;  /* Absolute tqp id for in this pf */
0027     u8 tqp_vf; /* VF id */
0028 #define HCLGEVF_TQP_MAP_TYPE_PF     0
0029 #define HCLGEVF_TQP_MAP_TYPE_VF     1
0030 #define HCLGEVF_TQP_MAP_TYPE_B      0
0031 #define HCLGEVF_TQP_MAP_EN_B        1
0032     u8 tqp_flag;    /* Indicate it's pf or vf tqp */
0033     __le16 tqp_vid; /* Virtual id in this pf/vf */
0034     u8 rsv[18];
0035 };
0036
0037 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
0038
0039 enum hclgevf_int_type {
0040     HCLGEVF_INT_TX = 0,
0041     HCLGEVF_INT_RX,
0042     HCLGEVF_INT_EVENT,
0043 };
0044
0045 struct hclgevf_ctrl_vector_chain {
0046     u8 int_vector_id;
0047     u8 int_cause_num;
0048 #define HCLGEVF_INT_TYPE_S  0
0049 #define HCLGEVF_INT_TYPE_M  0x3
0050 #define HCLGEVF_TQP_ID_S    2
0051 #define HCLGEVF_TQP_ID_M    (0x3fff << HCLGEVF_TQP_ID_S)
0052     __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
0053     u8 vfid;
0054     u8 resv;
0055 };
0056
0057 #define HCLGEVF_MSIX_OFT_ROCEE_S       0
0058 #define HCLGEVF_MSIX_OFT_ROCEE_M       (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
0059 #define HCLGEVF_VEC_NUM_S              0
0060 #define HCLGEVF_VEC_NUM_M              (0xff << HCLGEVF_VEC_NUM_S)
0061 struct hclgevf_query_res_cmd {
0062     __le16 tqp_num;
0063     __le16 reserved;
0064     __le16 msixcap_localid_ba_nic;
0065     __le16 msixcap_localid_ba_rocee;
0066     __le16 vf_intr_vector_number;
0067     __le16 rsv[7];
0068 };
0069
0070 #define HCLGEVF_GRO_EN_B               0
0071 struct hclgevf_cfg_gro_status_cmd {
0072     u8 gro_en;
0073     u8 rsv[23];
0074 };
0075
0076 #define HCLGEVF_LINK_STS_B  0
0077 #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B)
0078 struct hclgevf_link_status_cmd {
0079     u8 status;
0080     u8 rsv[23];
0081 };
0082
0083 #define HCLGEVF_RING_ID_MASK    0x3ff
0084 #define HCLGEVF_TQP_ENABLE_B    0
0085
0086 struct hclgevf_cfg_com_tqp_queue_cmd {
0087     __le16 tqp_id;
0088     __le16 stream_id;
0089     u8 enable;
0090     u8 rsv[19];
0091 };
0092
0093 struct hclgevf_cfg_tx_queue_pointer_cmd {
0094     __le16 tqp_id;
0095     __le16 tx_tail;
0096     __le16 tx_head;
0097     __le16 fbd_num;
0098     __le16 ring_offset;
0099     u8 rsv[14];
0100 };
0101
0102 /* this bit indicates that the driver is ready for hardware reset */
0103 #define HCLGEVF_NIC_SW_RST_RDY_B    16
0104 #define HCLGEVF_NIC_SW_RST_RDY      BIT(HCLGEVF_NIC_SW_RST_RDY_B)
0105
0106 #define HCLGEVF_NIC_CMQ_DESC_NUM    1024
0107 #define HCLGEVF_NIC_CMQ_DESC_NUM_S  3
0108
0109 #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM      4
0110
0111 #define hclgevf_cmd_setup_basic_desc(desc, opcode, is_read) \
0112     hclge_comm_cmd_setup_basic_desc(desc, opcode, is_read)
0113
0114 struct hclgevf_dev_specs_0_cmd {
0115     __le32 rsv0;
0116     __le32 mac_entry_num;
0117     __le32 mng_entry_num;
0118     __le16 rss_ind_tbl_size;
0119     __le16 rss_key_size;
0120     __le16 int_ql_max;
0121     u8 max_non_tso_bd_num;
0122     u8 rsv1[5];
0123 };
0124
0125 #define HCLGEVF_DEF_MAX_INT_GL      0x1FE0U
0126
0127 struct hclgevf_dev_specs_1_cmd {
0128     __le16 max_frm_size;
0129     __le16 rsv0;
0130     __le16 max_int_gl;
0131     u8 rsv1[18];
0132 };
0133
0134 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num);
0135 void hclgevf_arq_init(struct hclgevf_dev *hdev);
0136 #endif