hns3/hns3pf/hclge_tm.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 // Copyright (c) 2016-2017 Hisilicon Limited.
0003
0004 #ifndef __HCLGE_TM_H
0005 #define __HCLGE_TM_H
0006
0007 #include <linux/types.h>
0008
0009 #include "hnae3.h"
0010
0011 struct hclge_dev;
0012 struct hclge_vport;
0013 enum hclge_opcode_type;
0014
0015 /* MAC Pause */
0016 #define HCLGE_TX_MAC_PAUSE_EN_MSK   BIT(0)
0017 #define HCLGE_RX_MAC_PAUSE_EN_MSK   BIT(1)
0018
0019 #define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0)
0020
0021 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP   0x7F
0022 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME  0xFFFF
0023
0024 /* SP or DWRR */
0025 #define HCLGE_TM_TX_SCHD_DWRR_MSK   BIT(0)
0026 #define HCLGE_TM_TX_SCHD_SP_MSK     0xFE
0027
0028 #define HCLGE_ETHER_MAX_RATE    100000
0029
0030 #define HCLGE_TM_PF_MAX_PRI_NUM     8
0031 #define HCLGE_TM_PF_MAX_QSET_NUM    8
0032
0033 struct hclge_pg_to_pri_link_cmd {
0034     u8 pg_id;
0035     u8 rsvd1[3];
0036     u8 pri_bit_map;
0037 };
0038
0039 struct hclge_qs_to_pri_link_cmd {
0040     __le16 qs_id;
0041     __le16 rsvd;
0042     u8 priority;
0043 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK    BIT(0)
0044     u8 link_vld;
0045 };
0046
0047 struct hclge_nq_to_qs_link_cmd {
0048     __le16 nq_id;
0049     __le16 rsvd;
0050 #define HCLGE_TM_Q_QS_LINK_VLD_MSK  BIT(10)
0051 #define HCLGE_TM_QS_ID_L_MSK        GENMASK(9, 0)
0052 #define HCLGE_TM_QS_ID_L_S      0
0053 #define HCLGE_TM_QS_ID_H_MSK        GENMASK(14, 10)
0054 #define HCLGE_TM_QS_ID_H_S      10
0055 #define HCLGE_TM_QS_ID_H_EXT_S      11
0056 #define HCLGE_TM_QS_ID_H_EXT_MSK    GENMASK(15, 11)
0057     __le16 qset_id;
0058 };
0059
0060 struct hclge_tqp_tx_queue_tc_cmd {
0061     __le16 queue_id;
0062     __le16 rsvd;
0063     u8 tc_id;
0064     u8 rev[3];
0065 };
0066
0067 struct hclge_pg_weight_cmd {
0068     u8 pg_id;
0069     u8 dwrr;
0070 };
0071
0072 struct hclge_priority_weight_cmd {
0073     u8 pri_id;
0074     u8 dwrr;
0075 };
0076
0077 struct hclge_pri_sch_mode_cfg_cmd {
0078     u8 pri_id;
0079     u8 rsvd[3];
0080     u8 sch_mode;
0081 };
0082
0083 struct hclge_qs_sch_mode_cfg_cmd {
0084     __le16 qs_id;
0085     u8 rsvd[2];
0086     u8 sch_mode;
0087 };
0088
0089 struct hclge_qs_weight_cmd {
0090     __le16 qs_id;
0091     u8 dwrr;
0092 };
0093
0094 struct hclge_ets_tc_weight_cmd {
0095     u8 tc_weight[HNAE3_MAX_TC];
0096     u8 weight_offset;
0097     u8 rsvd[15];
0098 };
0099
0100 #define HCLGE_TM_SHAP_IR_B_MSK  GENMASK(7, 0)
0101 #define HCLGE_TM_SHAP_IR_B_LSH  0
0102 #define HCLGE_TM_SHAP_IR_U_MSK  GENMASK(11, 8)
0103 #define HCLGE_TM_SHAP_IR_U_LSH  8
0104 #define HCLGE_TM_SHAP_IR_S_MSK  GENMASK(15, 12)
0105 #define HCLGE_TM_SHAP_IR_S_LSH  12
0106 #define HCLGE_TM_SHAP_BS_B_MSK  GENMASK(20, 16)
0107 #define HCLGE_TM_SHAP_BS_B_LSH  16
0108 #define HCLGE_TM_SHAP_BS_S_MSK  GENMASK(25, 21)
0109 #define HCLGE_TM_SHAP_BS_S_LSH  21
0110
0111 enum hclge_shap_bucket {
0112     HCLGE_TM_SHAP_C_BUCKET = 0,
0113     HCLGE_TM_SHAP_P_BUCKET,
0114 };
0115
0116 /* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */
0117 #define HCLGE_TM_RATE_VLD   0
0118
0119 struct hclge_pri_shapping_cmd {
0120     u8 pri_id;
0121     u8 rsvd[3];
0122     __le32 pri_shapping_para;
0123     u8 flag;
0124     u8 rsvd1[3];
0125     __le32 pri_rate;
0126 };
0127
0128 struct hclge_pg_shapping_cmd {
0129     u8 pg_id;
0130     u8 rsvd[3];
0131     __le32 pg_shapping_para;
0132     u8 flag;
0133     u8 rsvd1[3];
0134     __le32 pg_rate;
0135 };
0136
0137 struct hclge_qs_shapping_cmd {
0138     __le16 qs_id;
0139     u8 rsvd[2];
0140     __le32 qs_shapping_para;
0141     u8 flag;
0142     u8 rsvd1[3];
0143     __le32 qs_rate;
0144 };
0145
0146 #define HCLGE_BP_GRP_NUM        32
0147 #define HCLGE_BP_SUB_GRP_ID_S       0
0148 #define HCLGE_BP_SUB_GRP_ID_M       GENMASK(4, 0)
0149 #define HCLGE_BP_GRP_ID_S       5
0150 #define HCLGE_BP_GRP_ID_M       GENMASK(9, 5)
0151
0152 #define HCLGE_BP_EXT_GRP_NUM        40
0153 #define HCLGE_BP_EXT_GRP_ID_S       5
0154 #define HCLGE_BP_EXT_GRP_ID_M       GENMASK(10, 5)
0155
0156 struct hclge_bp_to_qs_map_cmd {
0157     u8 tc_id;
0158     u8 rsvd[2];
0159     u8 qs_group_id;
0160     __le32 qs_bit_map;
0161     u32 rsvd1;
0162 };
0163
0164 struct hclge_pfc_en_cmd {
0165     u8 tx_rx_en_bitmap;
0166     u8 pri_en_bitmap;
0167 };
0168
0169 struct hclge_cfg_pause_param_cmd {
0170     u8 mac_addr[ETH_ALEN];
0171     u8 pause_trans_gap;
0172     u8 rsvd;
0173     __le16 pause_trans_time;
0174     u8 rsvd1[6];
0175     /* extra mac address to do double check for pause frame */
0176     u8 mac_addr_extra[ETH_ALEN];
0177     u16 rsvd2;
0178 };
0179
0180 struct hclge_pfc_stats_cmd {
0181     __le64 pkt_num[3];
0182 };
0183
0184 struct hclge_port_shapping_cmd {
0185     __le32 port_shapping_para;
0186     u8 flag;
0187     u8 rsvd[3];
0188     __le32 port_rate;
0189 };
0190
0191 struct hclge_shaper_ir_para {
0192     u8 ir_b; /* IR_B parameter of IR shaper */
0193     u8 ir_u; /* IR_U parameter of IR shaper */
0194     u8 ir_s; /* IR_S parameter of IR shaper */
0195 };
0196
0197 struct hclge_tm_nodes_cmd {
0198     u8 pg_base_id;
0199     u8 pri_base_id;
0200     __le16 qset_base_id;
0201     __le16 queue_base_id;
0202     u8 pg_num;
0203     u8 pri_num;
0204     __le16 qset_num;
0205     __le16 queue_num;
0206 };
0207
0208 struct hclge_tm_shaper_para {
0209     u32 rate;
0210     u8 ir_b;
0211     u8 ir_u;
0212     u8 ir_s;
0213     u8 bs_b;
0214     u8 bs_s;
0215     u8 flag;
0216 };
0217
0218 #define hclge_tm_set_field(dest, string, val) \
0219                hnae3_set_field((dest), \
0220                (HCLGE_TM_SHAP_##string##_MSK), \
0221                (HCLGE_TM_SHAP_##string##_LSH), val)
0222 #define hclge_tm_get_field(src, string) \
0223             hnae3_get_field((src), HCLGE_TM_SHAP_##string##_MSK, \
0224                     HCLGE_TM_SHAP_##string##_LSH)
0225
0226 int hclge_tm_schd_init(struct hclge_dev *hdev);
0227 int hclge_tm_vport_map_update(struct hclge_dev *hdev);
0228 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init);
0229 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev);
0230 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
0231 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
0232 void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
0233 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
0234 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
0235 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
0236 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
0237 void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
0238 void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
0239 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
0240 int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev);
0241 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num);
0242 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num);
0243 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
0244                   u8 *link_vld);
0245 int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode);
0246 int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight);
0247 int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id,
0248                  struct hclge_tm_shaper_para *para);
0249 int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode);
0250 int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight);
0251 int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
0252                 enum hclge_opcode_type cmd,
0253                 struct hclge_tm_shaper_para *para);
0254 int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id);
0255 int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id);
0256 int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id,
0257                    u8 *pri_bit_map);
0258 int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight);
0259 int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode);
0260 int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id,
0261                enum hclge_opcode_type cmd,
0262                struct hclge_tm_shaper_para *para);
0263 int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
0264                  struct hclge_tm_shaper_para *para);
0265 #endif