hns3/hns3pf/hclge_ptp.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 // Copyright (c) 2021 Hisilicon Limited.
0003
0004 #ifndef __HCLGE_PTP_H
0005 #define __HCLGE_PTP_H
0006
0007 #include <linux/ptp_clock_kernel.h>
0008 #include <linux/net_tstamp.h>
0009 #include <linux/types.h>
0010
0011 struct hclge_dev;
0012 struct ifreq;
0013
0014 #define HCLGE_PTP_REG_OFFSET    0x29000
0015
0016 #define HCLGE_PTP_TX_TS_SEQID_REG   0x0
0017 #define HCLGE_PTP_TX_TS_NSEC_REG    0x4
0018 #define HCLGE_PTP_TX_TS_NSEC_MASK   GENMASK(29, 0)
0019 #define HCLGE_PTP_TX_TS_SEC_L_REG   0x8
0020 #define HCLGE_PTP_TX_TS_SEC_H_REG   0xC
0021 #define HCLGE_PTP_TX_TS_SEC_H_MASK  GENMASK(15, 0)
0022 #define HCLGE_PTP_TX_TS_CNT_REG     0x30
0023
0024 #define HCLGE_PTP_TIME_SEC_H_REG    0x50
0025 #define HCLGE_PTP_TIME_SEC_H_MASK   GENMASK(15, 0)
0026 #define HCLGE_PTP_TIME_SEC_L_REG    0x54
0027 #define HCLGE_PTP_TIME_NSEC_REG     0x58
0028 #define HCLGE_PTP_TIME_NSEC_MASK    GENMASK(29, 0)
0029 #define HCLGE_PTP_TIME_NSEC_NEG     BIT(31)
0030 #define HCLGE_PTP_TIME_SYNC_REG     0x5C
0031 #define HCLGE_PTP_TIME_SYNC_EN      BIT(0)
0032 #define HCLGE_PTP_TIME_ADJ_REG      0x60
0033 #define HCLGE_PTP_TIME_ADJ_EN       BIT(0)
0034 #define HCLGE_PTP_CYCLE_QUO_REG     0x64
0035 #define HCLGE_PTP_CYCLE_QUO_MASK    GENMASK(7, 0)
0036 #define HCLGE_PTP_CYCLE_DEN_REG     0x68
0037 #define HCLGE_PTP_CYCLE_NUM_REG     0x6C
0038 #define HCLGE_PTP_CYCLE_CFG_REG     0x70
0039 #define HCLGE_PTP_CYCLE_ADJ_EN      BIT(0)
0040 #define HCLGE_PTP_CUR_TIME_SEC_H_REG    0x74
0041 #define HCLGE_PTP_CUR_TIME_SEC_L_REG    0x78
0042 #define HCLGE_PTP_CUR_TIME_NSEC_REG 0x7C
0043
0044 #define HCLGE_PTP_CYCLE_ADJ_MAX     500000000
0045 #define HCLGE_PTP_SEC_H_OFFSET      32u
0046 #define HCLGE_PTP_SEC_L_MASK        GENMASK(31, 0)
0047
0048 #define HCLGE_PTP_FLAG_EN       0
0049 #define HCLGE_PTP_FLAG_TX_EN        1
0050 #define HCLGE_PTP_FLAG_RX_EN        2
0051
0052 struct hclge_ptp_cycle {
0053     u32 quo;
0054     u32 numer;
0055     u32 den;
0056 };
0057
0058 struct hclge_ptp {
0059     struct hclge_dev *hdev;
0060     struct ptp_clock *clock;
0061     struct sk_buff *tx_skb;
0062     unsigned long flags;
0063     void __iomem *io_base;
0064     struct ptp_clock_info info;
0065     struct hwtstamp_config ts_cfg;
0066     spinlock_t lock;    /* protects ptp registers */
0067     u32 ptp_cfg;
0068     u32 last_tx_seqid;
0069     struct hclge_ptp_cycle cycle;
0070     unsigned long tx_start;
0071     unsigned long tx_cnt;
0072     unsigned long tx_skipped;
0073     unsigned long tx_cleaned;
0074     unsigned long last_rx;
0075     unsigned long rx_cnt;
0076     unsigned long tx_timeout;
0077 };
0078
0079 struct hclge_ptp_int_cmd {
0080 #define HCLGE_PTP_INT_EN_B  BIT(0)
0081
0082     u8 int_en;
0083     u8 rsvd[23];
0084 };
0085
0086 enum hclge_ptp_udp_type {
0087     HCLGE_PTP_UDP_NOT_TYPE,
0088     HCLGE_PTP_UDP_P13F_TYPE,
0089     HCLGE_PTP_UDP_P140_TYPE,
0090     HCLGE_PTP_UDP_FULL_TYPE,
0091 };
0092
0093 enum hclge_ptp_msg_type {
0094     HCLGE_PTP_MSG_TYPE_V2_L2,
0095     HCLGE_PTP_MSG_TYPE_V2,
0096     HCLGE_PTP_MSG_TYPE_V2_EVENT,
0097 };
0098
0099 enum hclge_ptp_msg0_type {
0100     HCLGE_PTP_MSG0_V2_DELAY_REQ = 1,
0101     HCLGE_PTP_MSG0_V2_PDELAY_REQ,
0102     HCLGE_PTP_MSG0_V2_DELAY_RESP,
0103     HCLGE_PTP_MSG0_V2_EVENT = 0xF,
0104 };
0105
0106 #define HCLGE_PTP_MSG1_V2_DEFAULT   1
0107
0108 struct hclge_ptp_cfg_cmd {
0109 #define HCLGE_PTP_EN_B          BIT(0)
0110 #define HCLGE_PTP_TX_EN_B       BIT(1)
0111 #define HCLGE_PTP_RX_EN_B       BIT(2)
0112 #define HCLGE_PTP_UDP_EN_SHIFT      3
0113 #define HCLGE_PTP_UDP_EN_MASK       GENMASK(4, 3)
0114 #define HCLGE_PTP_MSG_TYPE_SHIFT    8
0115 #define HCLGE_PTP_MSG_TYPE_MASK     GENMASK(9, 8)
0116 #define HCLGE_PTP_MSG1_SHIFT        16
0117 #define HCLGE_PTP_MSG1_MASK     GENMASK(19, 16)
0118 #define HCLGE_PTP_MSG0_SHIFT        24
0119 #define HCLGE_PTP_MSG0_MASK     GENMASK(27, 24)
0120
0121     __le32 cfg;
0122     u8 rsvd[20];
0123 };
0124
0125 static inline struct hclge_dev *hclge_ptp_get_hdev(struct ptp_clock_info *info)
0126 {
0127     struct hclge_ptp *ptp = container_of(info, struct hclge_ptp, info);
0128
0129     return ptp->hdev;
0130 }
0131
0132 bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb);
0133 void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev);
0134 void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb,
0135                u32 nsec, u32 sec);
0136 int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr);
0137 int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr);
0138 int hclge_ptp_init(struct hclge_dev *hdev);
0139 void hclge_ptp_uninit(struct hclge_dev *hdev);
0140 int hclge_ptp_get_ts_info(struct hnae3_handle *handle,
0141               struct ethtool_ts_info *info);
0142 int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg);
0143 #endif