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0001 // SPDX-License-Identifier: GPL-2.0+
0002 // Copyright (c) 2016-2017 Hisilicon Limited.
0003 
0004 #include "hclge_main.h"
0005 #include "hclge_mbx.h"
0006 #include "hnae3.h"
0007 #include "hclge_comm_rss.h"
0008 
0009 #define CREATE_TRACE_POINTS
0010 #include "hclge_trace.h"
0011 
0012 static u16 hclge_errno_to_resp(int errno)
0013 {
0014     int resp = abs(errno);
0015 
0016     /* The status for pf to vf msg cmd is u16, constrainted by HW.
0017      * We need to keep the same type with it.
0018      * The intput errno is the stander error code, it's safely to
0019      * use a u16 to store the abs(errno).
0020      */
0021     return (u16)resp;
0022 }
0023 
0024 /* hclge_gen_resp_to_vf: used to generate a synchronous response to VF when PF
0025  * receives a mailbox message from VF.
0026  * @vport: pointer to struct hclge_vport
0027  * @vf_to_pf_req: pointer to hclge_mbx_vf_to_pf_cmd of the original mailbox
0028  *        message
0029  * @resp_status: indicate to VF whether its request success(0) or failed.
0030  */
0031 static int hclge_gen_resp_to_vf(struct hclge_vport *vport,
0032                 struct hclge_mbx_vf_to_pf_cmd *vf_to_pf_req,
0033                 struct hclge_respond_to_vf_msg *resp_msg)
0034 {
0035     struct hclge_mbx_pf_to_vf_cmd *resp_pf_to_vf;
0036     struct hclge_dev *hdev = vport->back;
0037     enum hclge_comm_cmd_status status;
0038     struct hclge_desc desc;
0039     u16 resp;
0040 
0041     resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data;
0042 
0043     if (resp_msg->len > HCLGE_MBX_MAX_RESP_DATA_SIZE) {
0044         dev_err(&hdev->pdev->dev,
0045             "PF fail to gen resp to VF len %u exceeds max len %u\n",
0046             resp_msg->len,
0047             HCLGE_MBX_MAX_RESP_DATA_SIZE);
0048         /* If resp_msg->len is too long, set the value to max length
0049          * and return the msg to VF
0050          */
0051         resp_msg->len = HCLGE_MBX_MAX_RESP_DATA_SIZE;
0052     }
0053 
0054     hclge_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_PF_TO_VF, false);
0055 
0056     resp_pf_to_vf->dest_vfid = vf_to_pf_req->mbx_src_vfid;
0057     resp_pf_to_vf->msg_len = vf_to_pf_req->msg_len;
0058     resp_pf_to_vf->match_id = vf_to_pf_req->match_id;
0059 
0060     resp_pf_to_vf->msg.code = cpu_to_le16(HCLGE_MBX_PF_VF_RESP);
0061     resp_pf_to_vf->msg.vf_mbx_msg_code =
0062                 cpu_to_le16(vf_to_pf_req->msg.code);
0063     resp_pf_to_vf->msg.vf_mbx_msg_subcode =
0064                 cpu_to_le16(vf_to_pf_req->msg.subcode);
0065     resp = hclge_errno_to_resp(resp_msg->status);
0066     if (resp < SHRT_MAX) {
0067         resp_pf_to_vf->msg.resp_status = cpu_to_le16(resp);
0068     } else {
0069         dev_warn(&hdev->pdev->dev,
0070              "failed to send response to VF, response status %u is out-of-bound\n",
0071              resp);
0072         resp_pf_to_vf->msg.resp_status = cpu_to_le16(EIO);
0073     }
0074 
0075     if (resp_msg->len > 0)
0076         memcpy(resp_pf_to_vf->msg.resp_data, resp_msg->data,
0077                resp_msg->len);
0078 
0079     trace_hclge_pf_mbx_send(hdev, resp_pf_to_vf);
0080 
0081     status = hclge_cmd_send(&hdev->hw, &desc, 1);
0082     if (status)
0083         dev_err(&hdev->pdev->dev,
0084             "failed to send response to VF, status: %d, vfid: %u, code: %u, subcode: %u.\n",
0085             status, vf_to_pf_req->mbx_src_vfid,
0086             vf_to_pf_req->msg.code, vf_to_pf_req->msg.subcode);
0087 
0088     return status;
0089 }
0090 
0091 static int hclge_send_mbx_msg(struct hclge_vport *vport, u8 *msg, u16 msg_len,
0092                   u16 mbx_opcode, u8 dest_vfid)
0093 {
0094     struct hclge_mbx_pf_to_vf_cmd *resp_pf_to_vf;
0095     struct hclge_dev *hdev = vport->back;
0096     enum hclge_comm_cmd_status status;
0097     struct hclge_desc desc;
0098 
0099     if (msg_len > HCLGE_MBX_MAX_MSG_SIZE) {
0100         dev_err(&hdev->pdev->dev,
0101             "msg data length(=%u) exceeds maximum(=%u)\n",
0102             msg_len, HCLGE_MBX_MAX_MSG_SIZE);
0103         return -EMSGSIZE;
0104     }
0105 
0106     resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data;
0107 
0108     hclge_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_PF_TO_VF, false);
0109 
0110     resp_pf_to_vf->dest_vfid = dest_vfid;
0111     resp_pf_to_vf->msg_len = msg_len;
0112     resp_pf_to_vf->msg.code = cpu_to_le16(mbx_opcode);
0113 
0114     memcpy(resp_pf_to_vf->msg.msg_data, msg, msg_len);
0115 
0116     trace_hclge_pf_mbx_send(hdev, resp_pf_to_vf);
0117 
0118     status = hclge_cmd_send(&hdev->hw, &desc, 1);
0119     if (status)
0120         dev_err(&hdev->pdev->dev,
0121             "failed to send mailbox to VF, status: %d, vfid: %u, opcode: %u\n",
0122             status, dest_vfid, mbx_opcode);
0123 
0124     return status;
0125 }
0126 
0127 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport)
0128 {
0129     struct hclge_dev *hdev = vport->back;
0130     __le16 msg_data;
0131     u16 reset_type;
0132     u8 dest_vfid;
0133 
0134     BUILD_BUG_ON(HNAE3_MAX_RESET > U16_MAX);
0135 
0136     dest_vfid = (u8)vport->vport_id;
0137 
0138     if (hdev->reset_type == HNAE3_FUNC_RESET)
0139         reset_type = HNAE3_VF_PF_FUNC_RESET;
0140     else if (hdev->reset_type == HNAE3_FLR_RESET)
0141         reset_type = HNAE3_VF_FULL_RESET;
0142     else
0143         reset_type = HNAE3_VF_FUNC_RESET;
0144 
0145     msg_data = cpu_to_le16(reset_type);
0146 
0147     /* send this requested info to VF */
0148     return hclge_send_mbx_msg(vport, (u8 *)&msg_data, sizeof(msg_data),
0149                   HCLGE_MBX_ASSERTING_RESET, dest_vfid);
0150 }
0151 
0152 static void hclge_free_vector_ring_chain(struct hnae3_ring_chain_node *head)
0153 {
0154     struct hnae3_ring_chain_node *chain_tmp, *chain;
0155 
0156     chain = head->next;
0157 
0158     while (chain) {
0159         chain_tmp = chain->next;
0160         kfree_sensitive(chain);
0161         chain = chain_tmp;
0162     }
0163 }
0164 
0165 /* hclge_get_ring_chain_from_mbx: get ring type & tqp id & int_gl idx
0166  * from mailbox message
0167  * msg[0]: opcode
0168  * msg[1]: <not relevant to this function>
0169  * msg[2]: ring_num
0170  * msg[3]: first ring type (TX|RX)
0171  * msg[4]: first tqp id
0172  * msg[5]: first int_gl idx
0173  * msg[6] ~ msg[14]: other ring type, tqp id and int_gl idx
0174  */
0175 static int hclge_get_ring_chain_from_mbx(
0176             struct hclge_mbx_vf_to_pf_cmd *req,
0177             struct hnae3_ring_chain_node *ring_chain,
0178             struct hclge_vport *vport)
0179 {
0180     struct hnae3_ring_chain_node *cur_chain, *new_chain;
0181     struct hclge_dev *hdev = vport->back;
0182     int ring_num;
0183     int i;
0184 
0185     ring_num = req->msg.ring_num;
0186 
0187     if (ring_num > HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM)
0188         return -EINVAL;
0189 
0190     for (i = 0; i < ring_num; i++) {
0191         if (req->msg.param[i].tqp_index >= vport->nic.kinfo.rss_size) {
0192             dev_err(&hdev->pdev->dev, "tqp index(%u) is out of range(0-%u)\n",
0193                 req->msg.param[i].tqp_index,
0194                 vport->nic.kinfo.rss_size - 1U);
0195             return -EINVAL;
0196         }
0197     }
0198 
0199     hnae3_set_bit(ring_chain->flag, HNAE3_RING_TYPE_B,
0200               req->msg.param[0].ring_type);
0201     ring_chain->tqp_index =
0202         hclge_get_queue_id(vport->nic.kinfo.tqp
0203                    [req->msg.param[0].tqp_index]);
0204     hnae3_set_field(ring_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
0205             HNAE3_RING_GL_IDX_S, req->msg.param[0].int_gl_index);
0206 
0207     cur_chain = ring_chain;
0208 
0209     for (i = 1; i < ring_num; i++) {
0210         new_chain = kzalloc(sizeof(*new_chain), GFP_KERNEL);
0211         if (!new_chain)
0212             goto err;
0213 
0214         hnae3_set_bit(new_chain->flag, HNAE3_RING_TYPE_B,
0215                   req->msg.param[i].ring_type);
0216 
0217         new_chain->tqp_index =
0218         hclge_get_queue_id(vport->nic.kinfo.tqp
0219             [req->msg.param[i].tqp_index]);
0220 
0221         hnae3_set_field(new_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
0222                 HNAE3_RING_GL_IDX_S,
0223                 req->msg.param[i].int_gl_index);
0224 
0225         cur_chain->next = new_chain;
0226         cur_chain = new_chain;
0227     }
0228 
0229     return 0;
0230 err:
0231     hclge_free_vector_ring_chain(ring_chain);
0232     return -ENOMEM;
0233 }
0234 
0235 static int hclge_map_unmap_ring_to_vf_vector(struct hclge_vport *vport, bool en,
0236                          struct hclge_mbx_vf_to_pf_cmd *req)
0237 {
0238     struct hnae3_ring_chain_node ring_chain;
0239     int vector_id = req->msg.vector_id;
0240     int ret;
0241 
0242     memset(&ring_chain, 0, sizeof(ring_chain));
0243     ret = hclge_get_ring_chain_from_mbx(req, &ring_chain, vport);
0244     if (ret)
0245         return ret;
0246 
0247     ret = hclge_bind_ring_with_vector(vport, vector_id, en, &ring_chain);
0248 
0249     hclge_free_vector_ring_chain(&ring_chain);
0250 
0251     return ret;
0252 }
0253 
0254 static int hclge_query_ring_vector_map(struct hclge_vport *vport,
0255                        struct hnae3_ring_chain_node *ring_chain,
0256                        struct hclge_desc *desc)
0257 {
0258     struct hclge_ctrl_vector_chain_cmd *req =
0259         (struct hclge_ctrl_vector_chain_cmd *)desc->data;
0260     struct hclge_dev *hdev = vport->back;
0261     u16 tqp_type_and_id;
0262     int status;
0263 
0264     hclge_cmd_setup_basic_desc(desc, HCLGE_OPC_ADD_RING_TO_VECTOR, true);
0265 
0266     tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[0]);
0267     hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
0268             hnae3_get_bit(ring_chain->flag, HNAE3_RING_TYPE_B));
0269     hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
0270             ring_chain->tqp_index);
0271     req->tqp_type_and_id[0] = cpu_to_le16(tqp_type_and_id);
0272     req->vfid = vport->vport_id;
0273 
0274     status = hclge_cmd_send(&hdev->hw, desc, 1);
0275     if (status)
0276         dev_err(&hdev->pdev->dev,
0277             "Get VF ring vector map info fail, status is %d.\n",
0278             status);
0279 
0280     return status;
0281 }
0282 
0283 static int hclge_get_vf_ring_vector_map(struct hclge_vport *vport,
0284                     struct hclge_mbx_vf_to_pf_cmd *req,
0285                     struct hclge_respond_to_vf_msg *resp)
0286 {
0287 #define HCLGE_LIMIT_RING_NUM            1
0288 #define HCLGE_RING_TYPE_OFFSET          0
0289 #define HCLGE_TQP_INDEX_OFFSET          1
0290 #define HCLGE_INT_GL_INDEX_OFFSET       2
0291 #define HCLGE_VECTOR_ID_OFFSET          3
0292 #define HCLGE_RING_VECTOR_MAP_INFO_LEN      4
0293     struct hnae3_ring_chain_node ring_chain;
0294     struct hclge_desc desc;
0295     struct hclge_ctrl_vector_chain_cmd *data =
0296         (struct hclge_ctrl_vector_chain_cmd *)desc.data;
0297     u16 tqp_type_and_id;
0298     u8 int_gl_index;
0299     int ret;
0300 
0301     req->msg.ring_num = HCLGE_LIMIT_RING_NUM;
0302 
0303     memset(&ring_chain, 0, sizeof(ring_chain));
0304     ret = hclge_get_ring_chain_from_mbx(req, &ring_chain, vport);
0305     if (ret)
0306         return ret;
0307 
0308     ret = hclge_query_ring_vector_map(vport, &ring_chain, &desc);
0309     if (ret) {
0310         hclge_free_vector_ring_chain(&ring_chain);
0311         return ret;
0312     }
0313 
0314     tqp_type_and_id = le16_to_cpu(data->tqp_type_and_id[0]);
0315     int_gl_index = hnae3_get_field(tqp_type_and_id,
0316                        HCLGE_INT_GL_IDX_M, HCLGE_INT_GL_IDX_S);
0317 
0318     resp->data[HCLGE_RING_TYPE_OFFSET] = req->msg.param[0].ring_type;
0319     resp->data[HCLGE_TQP_INDEX_OFFSET] = req->msg.param[0].tqp_index;
0320     resp->data[HCLGE_INT_GL_INDEX_OFFSET] = int_gl_index;
0321     resp->data[HCLGE_VECTOR_ID_OFFSET] = data->int_vector_id_l;
0322     resp->len = HCLGE_RING_VECTOR_MAP_INFO_LEN;
0323 
0324     hclge_free_vector_ring_chain(&ring_chain);
0325 
0326     return ret;
0327 }
0328 
0329 static void hclge_set_vf_promisc_mode(struct hclge_vport *vport,
0330                       struct hclge_mbx_vf_to_pf_cmd *req)
0331 {
0332     struct hnae3_handle *handle = &vport->nic;
0333     struct hclge_dev *hdev = vport->back;
0334 
0335     vport->vf_info.request_uc_en = req->msg.en_uc;
0336     vport->vf_info.request_mc_en = req->msg.en_mc;
0337     vport->vf_info.request_bc_en = req->msg.en_bc;
0338 
0339     if (req->msg.en_limit_promisc)
0340         set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags);
0341     else
0342         clear_bit(HNAE3_PFLAG_LIMIT_PROMISC,
0343               &handle->priv_flags);
0344 
0345     set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
0346     hclge_task_schedule(hdev, 0);
0347 }
0348 
0349 static int hclge_set_vf_uc_mac_addr(struct hclge_vport *vport,
0350                     struct hclge_mbx_vf_to_pf_cmd *mbx_req)
0351 {
0352 #define HCLGE_MBX_VF_OLD_MAC_ADDR_OFFSET    6
0353 
0354     const u8 *mac_addr = (const u8 *)(mbx_req->msg.data);
0355     struct hclge_dev *hdev = vport->back;
0356     int status;
0357 
0358     if (mbx_req->msg.subcode == HCLGE_MBX_MAC_VLAN_UC_MODIFY) {
0359         const u8 *old_addr = (const u8 *)
0360         (&mbx_req->msg.data[HCLGE_MBX_VF_OLD_MAC_ADDR_OFFSET]);
0361 
0362         /* If VF MAC has been configured by the host then it
0363          * cannot be overridden by the MAC specified by the VM.
0364          */
0365         if (!is_zero_ether_addr(vport->vf_info.mac) &&
0366             !ether_addr_equal(mac_addr, vport->vf_info.mac))
0367             return -EPERM;
0368 
0369         if (!is_valid_ether_addr(mac_addr))
0370             return -EINVAL;
0371 
0372         spin_lock_bh(&vport->mac_list_lock);
0373         status = hclge_update_mac_node_for_dev_addr(vport, old_addr,
0374                                 mac_addr);
0375         spin_unlock_bh(&vport->mac_list_lock);
0376         hclge_task_schedule(hdev, 0);
0377     } else if (mbx_req->msg.subcode == HCLGE_MBX_MAC_VLAN_UC_ADD) {
0378         status = hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD,
0379                            HCLGE_MAC_ADDR_UC, mac_addr);
0380     } else if (mbx_req->msg.subcode == HCLGE_MBX_MAC_VLAN_UC_REMOVE) {
0381         status = hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL,
0382                            HCLGE_MAC_ADDR_UC, mac_addr);
0383     } else {
0384         dev_err(&hdev->pdev->dev,
0385             "failed to set unicast mac addr, unknown subcode %u\n",
0386             mbx_req->msg.subcode);
0387         return -EIO;
0388     }
0389 
0390     return status;
0391 }
0392 
0393 static int hclge_set_vf_mc_mac_addr(struct hclge_vport *vport,
0394                     struct hclge_mbx_vf_to_pf_cmd *mbx_req)
0395 {
0396     const u8 *mac_addr = (const u8 *)(mbx_req->msg.data);
0397     struct hclge_dev *hdev = vport->back;
0398 
0399     if (mbx_req->msg.subcode == HCLGE_MBX_MAC_VLAN_MC_ADD) {
0400         hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD,
0401                       HCLGE_MAC_ADDR_MC, mac_addr);
0402     } else if (mbx_req->msg.subcode == HCLGE_MBX_MAC_VLAN_MC_REMOVE) {
0403         hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL,
0404                       HCLGE_MAC_ADDR_MC, mac_addr);
0405     } else {
0406         dev_err(&hdev->pdev->dev,
0407             "failed to set mcast mac addr, unknown subcode %u\n",
0408             mbx_req->msg.subcode);
0409         return -EIO;
0410     }
0411 
0412     return 0;
0413 }
0414 
0415 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
0416                       u16 state,
0417                       struct hclge_vlan_info *vlan_info)
0418 {
0419     struct hclge_mbx_port_base_vlan base_vlan;
0420 
0421     base_vlan.state = cpu_to_le16(state);
0422     base_vlan.vlan_proto = cpu_to_le16(vlan_info->vlan_proto);
0423     base_vlan.qos = cpu_to_le16(vlan_info->qos);
0424     base_vlan.vlan_tag = cpu_to_le16(vlan_info->vlan_tag);
0425 
0426     return hclge_send_mbx_msg(vport, (u8 *)&base_vlan, sizeof(base_vlan),
0427                   HCLGE_MBX_PUSH_VLAN_INFO, vfid);
0428 }
0429 
0430 static int hclge_set_vf_vlan_cfg(struct hclge_vport *vport,
0431                  struct hclge_mbx_vf_to_pf_cmd *mbx_req,
0432                  struct hclge_respond_to_vf_msg *resp_msg)
0433 {
0434 #define HCLGE_MBX_VLAN_STATE_OFFSET 0
0435 #define HCLGE_MBX_VLAN_INFO_OFFSET  2
0436 
0437     struct hnae3_handle *handle = &vport->nic;
0438     struct hclge_dev *hdev = vport->back;
0439     struct hclge_vf_vlan_cfg *msg_cmd;
0440     __be16 proto;
0441     u16 vlan_id;
0442 
0443     msg_cmd = (struct hclge_vf_vlan_cfg *)&mbx_req->msg;
0444     switch (msg_cmd->subcode) {
0445     case HCLGE_MBX_VLAN_FILTER:
0446         proto = cpu_to_be16(le16_to_cpu(msg_cmd->proto));
0447         vlan_id = le16_to_cpu(msg_cmd->vlan);
0448         return hclge_set_vlan_filter(handle, proto, vlan_id,
0449                          msg_cmd->is_kill);
0450     case HCLGE_MBX_VLAN_RX_OFF_CFG:
0451         return hclge_en_hw_strip_rxvtag(handle, msg_cmd->enable);
0452     case HCLGE_MBX_GET_PORT_BASE_VLAN_STATE:
0453         /* vf does not need to know about the port based VLAN state
0454          * on device HNAE3_DEVICE_VERSION_V3. So always return disable
0455          * on device HNAE3_DEVICE_VERSION_V3 if vf queries the port
0456          * based VLAN state.
0457          */
0458         resp_msg->data[0] =
0459             hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3 ?
0460             HNAE3_PORT_BASE_VLAN_DISABLE :
0461             vport->port_base_vlan_cfg.state;
0462         resp_msg->len = sizeof(u8);
0463         return 0;
0464     case HCLGE_MBX_ENABLE_VLAN_FILTER:
0465         return hclge_enable_vport_vlan_filter(vport, msg_cmd->enable);
0466     default:
0467         return 0;
0468     }
0469 }
0470 
0471 static int hclge_set_vf_alive(struct hclge_vport *vport,
0472                   struct hclge_mbx_vf_to_pf_cmd *mbx_req)
0473 {
0474     bool alive = !!mbx_req->msg.data[0];
0475     int ret = 0;
0476 
0477     if (alive)
0478         ret = hclge_vport_start(vport);
0479     else
0480         hclge_vport_stop(vport);
0481 
0482     return ret;
0483 }
0484 
0485 static void hclge_get_basic_info(struct hclge_vport *vport,
0486                  struct hclge_respond_to_vf_msg *resp_msg)
0487 {
0488     struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
0489     struct hnae3_ae_dev *ae_dev = vport->back->ae_dev;
0490     struct hclge_basic_info *basic_info;
0491     unsigned int i;
0492     u32 pf_caps;
0493 
0494     basic_info = (struct hclge_basic_info *)resp_msg->data;
0495     for (i = 0; i < kinfo->tc_info.num_tc; i++)
0496         basic_info->hw_tc_map |= BIT(i);
0497 
0498     pf_caps = le32_to_cpu(basic_info->pf_caps);
0499     if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
0500         hnae3_set_bit(pf_caps, HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, 1);
0501 
0502     basic_info->pf_caps = cpu_to_le32(pf_caps);
0503     resp_msg->len = HCLGE_MBX_MAX_RESP_DATA_SIZE;
0504 }
0505 
0506 static void hclge_get_vf_queue_info(struct hclge_vport *vport,
0507                     struct hclge_respond_to_vf_msg *resp_msg)
0508 {
0509 #define HCLGE_TQPS_RSS_INFO_LEN     6
0510 
0511     struct hclge_mbx_vf_queue_info *queue_info;
0512     struct hclge_dev *hdev = vport->back;
0513 
0514     /* get the queue related info */
0515     queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg->data;
0516     queue_info->num_tqps = cpu_to_le16(vport->alloc_tqps);
0517     queue_info->rss_size = cpu_to_le16(vport->nic.kinfo.rss_size);
0518     queue_info->rx_buf_len = cpu_to_le16(hdev->rx_buf_len);
0519     resp_msg->len = HCLGE_TQPS_RSS_INFO_LEN;
0520 }
0521 
0522 static void hclge_get_vf_mac_addr(struct hclge_vport *vport,
0523                   struct hclge_respond_to_vf_msg *resp_msg)
0524 {
0525     ether_addr_copy(resp_msg->data, vport->vf_info.mac);
0526     resp_msg->len = ETH_ALEN;
0527 }
0528 
0529 static void hclge_get_vf_queue_depth(struct hclge_vport *vport,
0530                      struct hclge_respond_to_vf_msg *resp_msg)
0531 {
0532 #define HCLGE_TQPS_DEPTH_INFO_LEN   4
0533 
0534     struct hclge_mbx_vf_queue_depth *queue_depth;
0535     struct hclge_dev *hdev = vport->back;
0536 
0537     /* get the queue depth info */
0538     queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg->data;
0539     queue_depth->num_tx_desc = cpu_to_le16(hdev->num_tx_desc);
0540     queue_depth->num_rx_desc = cpu_to_le16(hdev->num_rx_desc);
0541 
0542     resp_msg->len = HCLGE_TQPS_DEPTH_INFO_LEN;
0543 }
0544 
0545 static void hclge_get_vf_media_type(struct hclge_vport *vport,
0546                     struct hclge_respond_to_vf_msg *resp_msg)
0547 {
0548 #define HCLGE_VF_MEDIA_TYPE_OFFSET  0
0549 #define HCLGE_VF_MODULE_TYPE_OFFSET 1
0550 #define HCLGE_VF_MEDIA_TYPE_LENGTH  2
0551 
0552     struct hclge_dev *hdev = vport->back;
0553 
0554     resp_msg->data[HCLGE_VF_MEDIA_TYPE_OFFSET] =
0555         hdev->hw.mac.media_type;
0556     resp_msg->data[HCLGE_VF_MODULE_TYPE_OFFSET] =
0557         hdev->hw.mac.module_type;
0558     resp_msg->len = HCLGE_VF_MEDIA_TYPE_LENGTH;
0559 }
0560 
0561 int hclge_push_vf_link_status(struct hclge_vport *vport)
0562 {
0563 #define HCLGE_VF_LINK_STATE_UP      1U
0564 #define HCLGE_VF_LINK_STATE_DOWN    0U
0565 
0566     struct hclge_mbx_link_status link_info;
0567     struct hclge_dev *hdev = vport->back;
0568     u16 link_status;
0569 
0570     /* mac.link can only be 0 or 1 */
0571     switch (vport->vf_info.link_state) {
0572     case IFLA_VF_LINK_STATE_ENABLE:
0573         link_status = HCLGE_VF_LINK_STATE_UP;
0574         break;
0575     case IFLA_VF_LINK_STATE_DISABLE:
0576         link_status = HCLGE_VF_LINK_STATE_DOWN;
0577         break;
0578     case IFLA_VF_LINK_STATE_AUTO:
0579     default:
0580         link_status = (u16)hdev->hw.mac.link;
0581         break;
0582     }
0583 
0584     link_info.link_status = cpu_to_le16(link_status);
0585     link_info.speed = cpu_to_le32(hdev->hw.mac.speed);
0586     link_info.duplex = cpu_to_le16(hdev->hw.mac.duplex);
0587     link_info.flag = HCLGE_MBX_PUSH_LINK_STATUS_EN;
0588 
0589     /* send this requested info to VF */
0590     return hclge_send_mbx_msg(vport, (u8 *)&link_info, sizeof(link_info),
0591                   HCLGE_MBX_LINK_STAT_CHANGE, vport->vport_id);
0592 }
0593 
0594 static void hclge_get_link_mode(struct hclge_vport *vport,
0595                 struct hclge_mbx_vf_to_pf_cmd *mbx_req)
0596 {
0597 #define HCLGE_SUPPORTED   1
0598     struct hclge_mbx_link_mode link_mode;
0599     struct hclge_dev *hdev = vport->back;
0600     unsigned long advertising;
0601     unsigned long supported;
0602     unsigned long send_data;
0603     u8 dest_vfid;
0604 
0605     advertising = hdev->hw.mac.advertising[0];
0606     supported = hdev->hw.mac.supported[0];
0607     dest_vfid = mbx_req->mbx_src_vfid;
0608     send_data = mbx_req->msg.data[0] == HCLGE_SUPPORTED ? supported :
0609                                   advertising;
0610     link_mode.idx = cpu_to_le16((u16)mbx_req->msg.data[0]);
0611     link_mode.link_mode = cpu_to_le64(send_data);
0612 
0613     hclge_send_mbx_msg(vport, (u8 *)&link_mode, sizeof(link_mode),
0614                HCLGE_MBX_LINK_STAT_MODE, dest_vfid);
0615 }
0616 
0617 static int hclge_mbx_reset_vf_queue(struct hclge_vport *vport,
0618                     struct hclge_mbx_vf_to_pf_cmd *mbx_req,
0619                     struct hclge_respond_to_vf_msg *resp_msg)
0620 {
0621 #define HCLGE_RESET_ALL_QUEUE_DONE  1U
0622     struct hnae3_handle *handle = &vport->nic;
0623     struct hclge_dev *hdev = vport->back;
0624     u16 queue_id;
0625     int ret;
0626 
0627     queue_id = le16_to_cpu(*(__le16 *)mbx_req->msg.data);
0628     resp_msg->data[0] = HCLGE_RESET_ALL_QUEUE_DONE;
0629     resp_msg->len = sizeof(u8);
0630 
0631     /* pf will reset vf's all queues at a time. So it is unnecessary
0632      * to reset queues if queue_id > 0, just return success.
0633      */
0634     if (queue_id > 0)
0635         return 0;
0636 
0637     ret = hclge_reset_tqp(handle);
0638     if (ret)
0639         dev_err(&hdev->pdev->dev, "failed to reset vf %u queue, ret = %d\n",
0640             vport->vport_id - HCLGE_VF_VPORT_START_NUM, ret);
0641 
0642     return ret;
0643 }
0644 
0645 static int hclge_reset_vf(struct hclge_vport *vport)
0646 {
0647     struct hclge_dev *hdev = vport->back;
0648 
0649     dev_warn(&hdev->pdev->dev, "PF received VF reset request from VF %u!",
0650          vport->vport_id - HCLGE_VF_VPORT_START_NUM);
0651 
0652     return hclge_func_reset_cmd(hdev, vport->vport_id);
0653 }
0654 
0655 static void hclge_vf_keep_alive(struct hclge_vport *vport)
0656 {
0657     vport->last_active_jiffies = jiffies;
0658 }
0659 
0660 static int hclge_set_vf_mtu(struct hclge_vport *vport,
0661                 struct hclge_mbx_vf_to_pf_cmd *mbx_req)
0662 {
0663     struct hclge_mbx_mtu_info *mtu_info;
0664     u32 mtu;
0665 
0666     mtu_info = (struct hclge_mbx_mtu_info *)mbx_req->msg.data;
0667     mtu = le32_to_cpu(mtu_info->mtu);
0668 
0669     return hclge_set_vport_mtu(vport, mtu);
0670 }
0671 
0672 static int hclge_get_queue_id_in_pf(struct hclge_vport *vport,
0673                     struct hclge_mbx_vf_to_pf_cmd *mbx_req,
0674                     struct hclge_respond_to_vf_msg *resp_msg)
0675 {
0676     struct hnae3_handle *handle = &vport->nic;
0677     struct hclge_dev *hdev = vport->back;
0678     u16 queue_id, qid_in_pf;
0679 
0680     queue_id = le16_to_cpu(*(__le16 *)mbx_req->msg.data);
0681     if (queue_id >= handle->kinfo.num_tqps) {
0682         dev_err(&hdev->pdev->dev, "Invalid queue id(%u) from VF %u\n",
0683             queue_id, mbx_req->mbx_src_vfid);
0684         return -EINVAL;
0685     }
0686 
0687     qid_in_pf = hclge_covert_handle_qid_global(&vport->nic, queue_id);
0688     *(__le16 *)resp_msg->data = cpu_to_le16(qid_in_pf);
0689     resp_msg->len = sizeof(qid_in_pf);
0690     return 0;
0691 }
0692 
0693 static int hclge_get_rss_key(struct hclge_vport *vport,
0694                  struct hclge_mbx_vf_to_pf_cmd *mbx_req,
0695                  struct hclge_respond_to_vf_msg *resp_msg)
0696 {
0697 #define HCLGE_RSS_MBX_RESP_LEN  8
0698     struct hclge_dev *hdev = vport->back;
0699     struct hclge_comm_rss_cfg *rss_cfg;
0700     u8 index;
0701 
0702     index = mbx_req->msg.data[0];
0703     rss_cfg = &hdev->rss_cfg;
0704 
0705     /* Check the query index of rss_hash_key from VF, make sure no
0706      * more than the size of rss_hash_key.
0707      */
0708     if (((index + 1) * HCLGE_RSS_MBX_RESP_LEN) >
0709           sizeof(rss_cfg->rss_hash_key)) {
0710         dev_warn(&hdev->pdev->dev,
0711              "failed to get the rss hash key, the index(%u) invalid !\n",
0712              index);
0713         return -EINVAL;
0714     }
0715 
0716     memcpy(resp_msg->data,
0717            &rss_cfg->rss_hash_key[index * HCLGE_RSS_MBX_RESP_LEN],
0718            HCLGE_RSS_MBX_RESP_LEN);
0719     resp_msg->len = HCLGE_RSS_MBX_RESP_LEN;
0720     return 0;
0721 }
0722 
0723 static void hclge_link_fail_parse(struct hclge_dev *hdev, u8 link_fail_code)
0724 {
0725     switch (link_fail_code) {
0726     case HCLGE_LF_REF_CLOCK_LOST:
0727         dev_warn(&hdev->pdev->dev, "Reference clock lost!\n");
0728         break;
0729     case HCLGE_LF_XSFP_TX_DISABLE:
0730         dev_warn(&hdev->pdev->dev, "SFP tx is disabled!\n");
0731         break;
0732     case HCLGE_LF_XSFP_ABSENT:
0733         dev_warn(&hdev->pdev->dev, "SFP is absent!\n");
0734         break;
0735     default:
0736         break;
0737     }
0738 }
0739 
0740 static void hclge_handle_link_change_event(struct hclge_dev *hdev,
0741                        struct hclge_mbx_vf_to_pf_cmd *req)
0742 {
0743     hclge_task_schedule(hdev, 0);
0744 
0745     if (!req->msg.subcode)
0746         hclge_link_fail_parse(hdev, req->msg.data[0]);
0747 }
0748 
0749 static bool hclge_cmd_crq_empty(struct hclge_hw *hw)
0750 {
0751     u32 tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
0752 
0753     return tail == hw->hw.cmq.crq.next_to_use;
0754 }
0755 
0756 static void hclge_handle_ncsi_error(struct hclge_dev *hdev)
0757 {
0758     struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
0759 
0760     ae_dev->ops->set_default_reset_request(ae_dev, HNAE3_GLOBAL_RESET);
0761     dev_warn(&hdev->pdev->dev, "requesting reset due to NCSI error\n");
0762     ae_dev->ops->reset_event(hdev->pdev, NULL);
0763 }
0764 
0765 static void hclge_handle_vf_tbl(struct hclge_vport *vport,
0766                 struct hclge_mbx_vf_to_pf_cmd *mbx_req)
0767 {
0768     struct hclge_dev *hdev = vport->back;
0769     struct hclge_vf_vlan_cfg *msg_cmd;
0770 
0771     msg_cmd = (struct hclge_vf_vlan_cfg *)&mbx_req->msg;
0772     if (msg_cmd->subcode == HCLGE_MBX_VPORT_LIST_CLEAR) {
0773         hclge_rm_vport_all_mac_table(vport, true, HCLGE_MAC_ADDR_UC);
0774         hclge_rm_vport_all_mac_table(vport, true, HCLGE_MAC_ADDR_MC);
0775         hclge_rm_vport_all_vlan_table(vport, true);
0776     } else {
0777         dev_warn(&hdev->pdev->dev, "Invalid cmd(%u)\n",
0778              msg_cmd->subcode);
0779     }
0780 }
0781 
0782 void hclge_mbx_handler(struct hclge_dev *hdev)
0783 {
0784     struct hclge_comm_cmq_ring *crq = &hdev->hw.hw.cmq.crq;
0785     struct hclge_respond_to_vf_msg resp_msg;
0786     struct hclge_mbx_vf_to_pf_cmd *req;
0787     struct hclge_vport *vport;
0788     struct hclge_desc *desc;
0789     bool is_del = false;
0790     unsigned int flag;
0791     int ret = 0;
0792 
0793     /* handle all the mailbox requests in the queue */
0794     while (!hclge_cmd_crq_empty(&hdev->hw)) {
0795         if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE,
0796                  &hdev->hw.hw.comm_state)) {
0797             dev_warn(&hdev->pdev->dev,
0798                  "command queue needs re-initializing\n");
0799             return;
0800         }
0801 
0802         desc = &crq->desc[crq->next_to_use];
0803         req = (struct hclge_mbx_vf_to_pf_cmd *)desc->data;
0804 
0805         flag = le16_to_cpu(crq->desc[crq->next_to_use].flag);
0806         if (unlikely(!hnae3_get_bit(flag, HCLGE_CMDQ_RX_OUTVLD_B))) {
0807             dev_warn(&hdev->pdev->dev,
0808                  "dropped invalid mailbox message, code = %u\n",
0809                  req->msg.code);
0810 
0811             /* dropping/not processing this invalid message */
0812             crq->desc[crq->next_to_use].flag = 0;
0813             hclge_mbx_ring_ptr_move_crq(crq);
0814             continue;
0815         }
0816 
0817         vport = &hdev->vport[req->mbx_src_vfid];
0818 
0819         trace_hclge_pf_mbx_get(hdev, req);
0820 
0821         /* clear the resp_msg before processing every mailbox message */
0822         memset(&resp_msg, 0, sizeof(resp_msg));
0823 
0824         switch (req->msg.code) {
0825         case HCLGE_MBX_MAP_RING_TO_VECTOR:
0826             ret = hclge_map_unmap_ring_to_vf_vector(vport, true,
0827                                 req);
0828             break;
0829         case HCLGE_MBX_UNMAP_RING_TO_VECTOR:
0830             ret = hclge_map_unmap_ring_to_vf_vector(vport, false,
0831                                 req);
0832             break;
0833         case HCLGE_MBX_GET_RING_VECTOR_MAP:
0834             ret = hclge_get_vf_ring_vector_map(vport, req,
0835                                &resp_msg);
0836             if (ret)
0837                 dev_err(&hdev->pdev->dev,
0838                     "PF fail(%d) to get VF ring vector map\n",
0839                     ret);
0840             break;
0841         case HCLGE_MBX_SET_PROMISC_MODE:
0842             hclge_set_vf_promisc_mode(vport, req);
0843             break;
0844         case HCLGE_MBX_SET_UNICAST:
0845             ret = hclge_set_vf_uc_mac_addr(vport, req);
0846             if (ret)
0847                 dev_err(&hdev->pdev->dev,
0848                     "PF fail(%d) to set VF UC MAC Addr\n",
0849                     ret);
0850             break;
0851         case HCLGE_MBX_SET_MULTICAST:
0852             ret = hclge_set_vf_mc_mac_addr(vport, req);
0853             if (ret)
0854                 dev_err(&hdev->pdev->dev,
0855                     "PF fail(%d) to set VF MC MAC Addr\n",
0856                     ret);
0857             break;
0858         case HCLGE_MBX_SET_VLAN:
0859             ret = hclge_set_vf_vlan_cfg(vport, req, &resp_msg);
0860             if (ret)
0861                 dev_err(&hdev->pdev->dev,
0862                     "PF failed(%d) to config VF's VLAN\n",
0863                     ret);
0864             break;
0865         case HCLGE_MBX_SET_ALIVE:
0866             ret = hclge_set_vf_alive(vport, req);
0867             if (ret)
0868                 dev_err(&hdev->pdev->dev,
0869                     "PF failed(%d) to set VF's ALIVE\n",
0870                     ret);
0871             break;
0872         case HCLGE_MBX_GET_QINFO:
0873             hclge_get_vf_queue_info(vport, &resp_msg);
0874             break;
0875         case HCLGE_MBX_GET_QDEPTH:
0876             hclge_get_vf_queue_depth(vport, &resp_msg);
0877             break;
0878         case HCLGE_MBX_GET_BASIC_INFO:
0879             hclge_get_basic_info(vport, &resp_msg);
0880             break;
0881         case HCLGE_MBX_GET_LINK_STATUS:
0882             ret = hclge_push_vf_link_status(vport);
0883             if (ret)
0884                 dev_err(&hdev->pdev->dev,
0885                     "failed to inform link stat to VF, ret = %d\n",
0886                     ret);
0887             break;
0888         case HCLGE_MBX_QUEUE_RESET:
0889             ret = hclge_mbx_reset_vf_queue(vport, req, &resp_msg);
0890             break;
0891         case HCLGE_MBX_RESET:
0892             ret = hclge_reset_vf(vport);
0893             break;
0894         case HCLGE_MBX_KEEP_ALIVE:
0895             hclge_vf_keep_alive(vport);
0896             break;
0897         case HCLGE_MBX_SET_MTU:
0898             ret = hclge_set_vf_mtu(vport, req);
0899             if (ret)
0900                 dev_err(&hdev->pdev->dev,
0901                     "VF fail(%d) to set mtu\n", ret);
0902             break;
0903         case HCLGE_MBX_GET_QID_IN_PF:
0904             ret = hclge_get_queue_id_in_pf(vport, req, &resp_msg);
0905             break;
0906         case HCLGE_MBX_GET_RSS_KEY:
0907             ret = hclge_get_rss_key(vport, req, &resp_msg);
0908             break;
0909         case HCLGE_MBX_GET_LINK_MODE:
0910             hclge_get_link_mode(vport, req);
0911             break;
0912         case HCLGE_MBX_GET_VF_FLR_STATUS:
0913         case HCLGE_MBX_VF_UNINIT:
0914             is_del = req->msg.code == HCLGE_MBX_VF_UNINIT;
0915             hclge_rm_vport_all_mac_table(vport, is_del,
0916                              HCLGE_MAC_ADDR_UC);
0917             hclge_rm_vport_all_mac_table(vport, is_del,
0918                              HCLGE_MAC_ADDR_MC);
0919             hclge_rm_vport_all_vlan_table(vport, is_del);
0920             break;
0921         case HCLGE_MBX_GET_MEDIA_TYPE:
0922             hclge_get_vf_media_type(vport, &resp_msg);
0923             break;
0924         case HCLGE_MBX_PUSH_LINK_STATUS:
0925             hclge_handle_link_change_event(hdev, req);
0926             break;
0927         case HCLGE_MBX_GET_MAC_ADDR:
0928             hclge_get_vf_mac_addr(vport, &resp_msg);
0929             break;
0930         case HCLGE_MBX_NCSI_ERROR:
0931             hclge_handle_ncsi_error(hdev);
0932             break;
0933         case HCLGE_MBX_HANDLE_VF_TBL:
0934             hclge_handle_vf_tbl(vport, req);
0935             break;
0936         default:
0937             dev_err(&hdev->pdev->dev,
0938                 "un-supported mailbox message, code = %u\n",
0939                 req->msg.code);
0940             break;
0941         }
0942 
0943         /* PF driver should not reply IMP */
0944         if (hnae3_get_bit(req->mbx_need_resp, HCLGE_MBX_NEED_RESP_B) &&
0945             req->msg.code < HCLGE_MBX_GET_VF_FLR_STATUS) {
0946             resp_msg.status = ret;
0947             if (time_is_before_jiffies(hdev->last_mbx_scheduled +
0948                            HCLGE_MBX_SCHED_TIMEOUT))
0949                 dev_warn(&hdev->pdev->dev,
0950                      "resp vport%u mbx(%u,%u) late\n",
0951                      req->mbx_src_vfid,
0952                      req->msg.code,
0953                      req->msg.subcode);
0954 
0955             hclge_gen_resp_to_vf(vport, req, &resp_msg);
0956         }
0957 
0958         crq->desc[crq->next_to_use].flag = 0;
0959         hclge_mbx_ring_ptr_move_crq(crq);
0960 
0961         /* reinitialize ret after complete the mbx message processing */
0962         ret = 0;
0963     }
0964 
0965     /* Write back CMDQ_RQ header pointer, M7 need this pointer */
0966     hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CRQ_HEAD_REG,
0967             crq->next_to_use);
0968 }
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