0001
0002
0003
0004 #ifndef __HCLGE_ERR_H
0005 #define __HCLGE_ERR_H
0006
0007 #include "hclge_main.h"
0008 #include "hnae3.h"
0009
0010 #define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10
0011 #define HCLGE_PF_RAS_INT_MIN_BD_NUM 4
0012 #define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 10
0013 #define HCLGE_PF_MSIX_INT_MIN_BD_NUM 4
0014
0015 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
0016 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
0017 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
0018 #define HCLGE_RAS_REG_ERR_MASK \
0019 (HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK)
0020
0021 #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
0022
0023 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
0024 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
0025 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
0026 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
0027 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
0028 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
0029 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
0030 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
0031 #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
0032 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
0033 #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
0034 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
0035 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
0036 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
0037 #define HCLGE_IGU_ERR_INT_EN 0x0000000F
0038 #define HCLGE_IGU_ERR_INT_TYPE 0x00000660
0039 #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
0040 #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
0041 #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
0042 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
0043 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
0044 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
0045 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
0046 #define HCLGE_PPP_PF_ERR_INT_EN 0x0003
0047 #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
0048 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
0049 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
0050 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
0051 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
0052 #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
0053 #define HCLGE_TM_QCN_ERR_INT_TYPE 0x29
0054 #define HCLGE_TM_QCN_FIFO_INT_EN 0xFFFF00
0055 #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
0056 #define HCLGE_NCSI_ERR_INT_EN 0x3
0057 #define HCLGE_NCSI_ERR_INT_TYPE 0x9
0058 #define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
0059 #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
0060 #define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
0061 #define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
0062 #define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
0063 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
0064 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
0065 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
0066 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
0067 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
0068 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
0069 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
0070 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
0071 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
0072 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
0073 #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
0074 #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
0075 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
0076 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
0077 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
0078 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
0079 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
0080 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
0081 #define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
0082 #define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
0083 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
0084 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
0085 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
0086 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
0087
0088 #define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
0089 #define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
0090 #define HCLGE_IGU_INT_MASK GENMASK(3, 0)
0091 #define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
0092 #define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
0093 #define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
0094 #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29)
0095 #define HCLGE_PPU_PF_INT_RAS_MASK 0x18
0096 #define HCLGE_PPU_PF_INT_MSIX_MASK 0x26
0097 #define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01
0098 #define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
0099 #define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
0100 #define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
0101
0102 #define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
0103 #define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
0104 #define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
0105 #define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
0106 #define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
0107 #define HCLGE_ROCEE_BERR_INT_MASK BIT(1)
0108 #define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)
0109 #define HCLGE_ROCEE_ECC_INT_MASK BIT(2)
0110 #define HCLGE_ROCEE_OVF_INT_MASK BIT(3)
0111 #define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
0112 #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
0113
0114 #define HCLGE_DESC_DATA_MAX 8
0115 #define HCLGE_REG_NUM_MAX 256
0116 #define HCLGE_DESC_NO_DATA_LEN 8
0117
0118 enum hclge_err_int_type {
0119 HCLGE_ERR_INT_MSIX = 0,
0120 HCLGE_ERR_INT_RAS_CE = 1,
0121 HCLGE_ERR_INT_RAS_NFE = 2,
0122 HCLGE_ERR_INT_RAS_FE = 3,
0123 };
0124
0125 enum hclge_mod_name_list {
0126 MODULE_NONE = 0,
0127 MODULE_BIOS_COMMON = 1,
0128 MODULE_GE = 2,
0129 MODULE_IGU_EGU = 3,
0130 MODULE_LGE = 4,
0131 MODULE_NCSI = 5,
0132 MODULE_PPP = 6,
0133 MODULE_QCN = 7,
0134 MODULE_RCB_RX = 8,
0135 MODULE_RTC = 9,
0136 MODULE_SSU = 10,
0137 MODULE_TM = 11,
0138 MODULE_RCB_TX = 12,
0139 MODULE_TXDMA = 13,
0140 MODULE_MASTER = 14,
0141 MODULE_HIMAC = 15,
0142
0143 MODULE_ROCEE_TOP = 40,
0144 MODULE_ROCEE_TIMER = 41,
0145 MODULE_ROCEE_MDB = 42,
0146 MODULE_ROCEE_TSP = 43,
0147 MODULE_ROCEE_TRP = 44,
0148 MODULE_ROCEE_SCC = 45,
0149 MODULE_ROCEE_CAEP = 46,
0150 MODULE_ROCEE_GEN_AC = 47,
0151 MODULE_ROCEE_QMM = 48,
0152 MODULE_ROCEE_LSAN = 49,
0153
0154 };
0155
0156 enum hclge_err_type_list {
0157 NONE_ERROR = 0,
0158 FIFO_ERROR = 1,
0159 MEMORY_ERROR = 2,
0160 POISON_ERROR = 3,
0161 MSIX_ECC_ERROR = 4,
0162 TQP_INT_ECC_ERROR = 5,
0163 PF_ABNORMAL_INT_ERROR = 6,
0164 MPF_ABNORMAL_INT_ERROR = 7,
0165 COMMON_ERROR = 8,
0166 PORT_ERROR = 9,
0167 ETS_ERROR = 10,
0168 NCSI_ERROR = 11,
0169 GLB_ERROR = 12,
0170 LINK_ERROR = 13,
0171 PTP_ERROR = 14,
0172
0173 ROCEE_NORMAL_ERR = 40,
0174 ROCEE_OVF_ERR = 41,
0175 ROCEE_BUS_ERR = 42,
0176
0177 };
0178
0179 struct hclge_hw_blk {
0180 u32 msk;
0181 const char *name;
0182 int (*config_err_int)(struct hclge_dev *hdev, bool en);
0183 };
0184
0185 struct hclge_hw_error {
0186 u32 int_msk;
0187 const char *msg;
0188 enum hnae3_reset_type reset_level;
0189 };
0190
0191 struct hclge_hw_module_id {
0192 enum hclge_mod_name_list module_id;
0193 const char *msg;
0194 };
0195
0196 struct hclge_hw_type_id {
0197 enum hclge_err_type_list type_id;
0198 const char *msg;
0199 };
0200
0201 struct hclge_sum_err_info {
0202 u8 reset_type;
0203 u8 mod_num;
0204 u8 rsv[2];
0205 };
0206
0207 struct hclge_mod_err_info {
0208 u8 mod_id;
0209 u8 err_num;
0210 u8 rsv[2];
0211 };
0212
0213 struct hclge_type_reg_err_info {
0214 u8 type_id;
0215 u8 reg_num;
0216 u8 rsv[2];
0217 u32 hclge_reg[HCLGE_REG_NUM_MAX];
0218 };
0219
0220 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
0221 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
0222 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
0223 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
0224 bool hclge_find_error_source(struct hclge_dev *hdev);
0225 void hclge_handle_occurred_error(struct hclge_dev *hdev);
0226 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
0227 int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
0228 unsigned long *reset_requests);
0229 int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
0230 int hclge_handle_mac_tnl(struct hclge_dev *hdev);
0231 #endif
