0001
0002
0003
0004 #ifndef __HCLGE_DEBUGFS_H
0005 #define __HCLGE_DEBUGFS_H
0006
0007 #include <linux/etherdevice.h>
0008 #include "hclge_cmd.h"
0009
0010 #define HCLGE_DBG_MNG_TBL_MAX 64
0011
0012 #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0)
0013 #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1)
0014 #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2)
0015 #define HCLGE_DBG_MNG_E_TYPE_B BIT(11)
0016 #define HCLGE_DBG_MNG_DROP_B BIT(13)
0017 #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF
0018 #define HCLGE_DBG_MNG_PF_ID 0x0007
0019 #define HCLGE_DBG_MNG_VF_ID 0x00FF
0020
0021
0022 #define HCLGE_DBG_DFX_BIOS_OFFSET 1
0023 #define HCLGE_DBG_DFX_SSU_0_OFFSET 2
0024 #define HCLGE_DBG_DFX_SSU_1_OFFSET 3
0025 #define HCLGE_DBG_DFX_IGU_OFFSET 4
0026 #define HCLGE_DBG_DFX_RPU_0_OFFSET 5
0027
0028 #define HCLGE_DBG_DFX_RPU_1_OFFSET 6
0029 #define HCLGE_DBG_DFX_NCSI_OFFSET 7
0030 #define HCLGE_DBG_DFX_RTC_OFFSET 8
0031 #define HCLGE_DBG_DFX_PPP_OFFSET 9
0032 #define HCLGE_DBG_DFX_RCB_OFFSET 10
0033 #define HCLGE_DBG_DFX_TQP_OFFSET 11
0034
0035 #define HCLGE_DBG_DFX_SSU_2_OFFSET 12
0036
0037 struct hclge_qos_pri_map_cmd {
0038 u8 pri0_tc : 4,
0039 pri1_tc : 4;
0040 u8 pri2_tc : 4,
0041 pri3_tc : 4;
0042 u8 pri4_tc : 4,
0043 pri5_tc : 4;
0044 u8 pri6_tc : 4,
0045 pri7_tc : 4;
0046 u8 vlan_pri : 4,
0047 rev : 4;
0048 };
0049
0050 struct hclge_dbg_bitmap_cmd {
0051 union {
0052 u8 bitmap;
0053 struct {
0054 u8 bit0 : 1,
0055 bit1 : 1,
0056 bit2 : 1,
0057 bit3 : 1,
0058 bit4 : 1,
0059 bit5 : 1,
0060 bit6 : 1,
0061 bit7 : 1;
0062 };
0063 };
0064 };
0065
0066 struct hclge_dbg_reg_common_msg {
0067 int msg_num;
0068 int offset;
0069 enum hclge_opcode_type cmd;
0070 };
0071
0072 struct hclge_dbg_tcam_msg {
0073 u8 stage;
0074 u32 loc;
0075 };
0076
0077 #define HCLGE_DBG_MAX_DFX_MSG_LEN 60
0078 struct hclge_dbg_dfx_message {
0079 int flag;
0080 char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
0081 };
0082
0083 #define HCLGE_DBG_MAC_REG_TYPE_LEN 32
0084 struct hclge_dbg_reg_type_info {
0085 enum hnae3_dbg_cmd cmd;
0086 const struct hclge_dbg_dfx_message *dfx_msg;
0087 struct hclge_dbg_reg_common_msg reg_msg;
0088 };
0089
0090 struct hclge_dbg_func {
0091 enum hnae3_dbg_cmd cmd;
0092 int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len);
0093 int (*dbg_dump_reg)(struct hclge_dev *hdev, enum hnae3_dbg_cmd cmd,
0094 char *buf, int len);
0095 };
0096
0097 struct hclge_dbg_status_dfx_info {
0098 u32 offset;
0099 char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
0100 };
0101
0102 static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {
0103 {false, "Reserved"},
0104 {true, "BP_CPU_STATE"},
0105 {true, "DFX_MSIX_INFO_NIC_0"},
0106 {true, "DFX_MSIX_INFO_NIC_1"},
0107 {true, "DFX_MSIX_INFO_NIC_2"},
0108 {true, "DFX_MSIX_INFO_NIC_3"},
0109
0110 {true, "DFX_MSIX_INFO_ROC_0"},
0111 {true, "DFX_MSIX_INFO_ROC_1"},
0112 {true, "DFX_MSIX_INFO_ROC_2"},
0113 {true, "DFX_MSIX_INFO_ROC_3"},
0114 {false, "Reserved"},
0115 {false, "Reserved"},
0116 };
0117
0118 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = {
0119 {false, "Reserved"},
0120 {true, "SSU_ETS_PORT_STATUS"},
0121 {true, "SSU_ETS_TCG_STATUS"},
0122 {false, "Reserved"},
0123 {false, "Reserved"},
0124 {true, "SSU_BP_STATUS_0"},
0125
0126 {true, "SSU_BP_STATUS_1"},
0127 {true, "SSU_BP_STATUS_2"},
0128 {true, "SSU_BP_STATUS_3"},
0129 {true, "SSU_BP_STATUS_4"},
0130 {true, "SSU_BP_STATUS_5"},
0131 {true, "SSU_MAC_TX_PFC_IND"},
0132
0133 {true, "MAC_SSU_RX_PFC_IND"},
0134 {true, "BTMP_AGEING_ST_B0"},
0135 {true, "BTMP_AGEING_ST_B1"},
0136 {true, "BTMP_AGEING_ST_B2"},
0137 {false, "Reserved"},
0138 {false, "Reserved"},
0139
0140 {true, "FULL_DROP_NUM"},
0141 {true, "PART_DROP_NUM"},
0142 {true, "PPP_KEY_DROP_NUM"},
0143 {true, "PPP_RLT_DROP_NUM"},
0144 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"},
0145 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"},
0146
0147 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"},
0148 {true, "NCSI_PACKET_CURR_BUFFER_CNT"},
0149 {true, "BTMP_AGEING_RLS_CNT_BANK0"},
0150 {true, "BTMP_AGEING_RLS_CNT_BANK1"},
0151 {true, "BTMP_AGEING_RLS_CNT_BANK2"},
0152 {true, "SSU_MB_RD_RLT_DROP_CNT"},
0153
0154 {true, "SSU_PPP_MAC_KEY_NUM_L"},
0155 {true, "SSU_PPP_MAC_KEY_NUM_H"},
0156 {true, "SSU_PPP_HOST_KEY_NUM_L"},
0157 {true, "SSU_PPP_HOST_KEY_NUM_H"},
0158 {true, "PPP_SSU_MAC_RLT_NUM_L"},
0159 {true, "PPP_SSU_MAC_RLT_NUM_H"},
0160
0161 {true, "PPP_SSU_HOST_RLT_NUM_L"},
0162 {true, "PPP_SSU_HOST_RLT_NUM_H"},
0163 {true, "NCSI_RX_PACKET_IN_CNT_L"},
0164 {true, "NCSI_RX_PACKET_IN_CNT_H"},
0165 {true, "NCSI_TX_PACKET_OUT_CNT_L"},
0166 {true, "NCSI_TX_PACKET_OUT_CNT_H"},
0167
0168 {true, "SSU_KEY_DROP_NUM"},
0169 {true, "MB_UNCOPY_NUM"},
0170 {true, "RX_OQ_DROP_PKT_CNT"},
0171 {true, "TX_OQ_DROP_PKT_CNT"},
0172 {true, "BANK_UNBALANCE_DROP_CNT"},
0173 {true, "BANK_UNBALANCE_RX_DROP_CNT"},
0174
0175 {true, "NIC_L2_ERR_DROP_PKT_CNT"},
0176 {true, "ROC_L2_ERR_DROP_PKT_CNT"},
0177 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"},
0178 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"},
0179 {true, "RX_OQ_GLB_DROP_PKT_CNT"},
0180 {false, "Reserved"},
0181
0182 {true, "LO_PRI_UNICAST_CUR_CNT"},
0183 {true, "HI_PRI_MULTICAST_CUR_CNT"},
0184 {true, "LO_PRI_MULTICAST_CUR_CNT"},
0185 {false, "Reserved"},
0186 {false, "Reserved"},
0187 {false, "Reserved"},
0188 };
0189
0190 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = {
0191 {true, "prt_id"},
0192 {true, "PACKET_TC_CURR_BUFFER_CNT_0"},
0193 {true, "PACKET_TC_CURR_BUFFER_CNT_1"},
0194 {true, "PACKET_TC_CURR_BUFFER_CNT_2"},
0195 {true, "PACKET_TC_CURR_BUFFER_CNT_3"},
0196 {true, "PACKET_TC_CURR_BUFFER_CNT_4"},
0197
0198 {true, "PACKET_TC_CURR_BUFFER_CNT_5"},
0199 {true, "PACKET_TC_CURR_BUFFER_CNT_6"},
0200 {true, "PACKET_TC_CURR_BUFFER_CNT_7"},
0201 {true, "PACKET_CURR_BUFFER_CNT"},
0202 {false, "Reserved"},
0203 {false, "Reserved"},
0204
0205 {true, "RX_PACKET_IN_CNT_L"},
0206 {true, "RX_PACKET_IN_CNT_H"},
0207 {true, "RX_PACKET_OUT_CNT_L"},
0208 {true, "RX_PACKET_OUT_CNT_H"},
0209 {true, "TX_PACKET_IN_CNT_L"},
0210 {true, "TX_PACKET_IN_CNT_H"},
0211
0212 {true, "TX_PACKET_OUT_CNT_L"},
0213 {true, "TX_PACKET_OUT_CNT_H"},
0214 {true, "ROC_RX_PACKET_IN_CNT_L"},
0215 {true, "ROC_RX_PACKET_IN_CNT_H"},
0216 {true, "ROC_TX_PACKET_OUT_CNT_L"},
0217 {true, "ROC_TX_PACKET_OUT_CNT_H"},
0218
0219 {true, "RX_PACKET_TC_IN_CNT_0_L"},
0220 {true, "RX_PACKET_TC_IN_CNT_0_H"},
0221 {true, "RX_PACKET_TC_IN_CNT_1_L"},
0222 {true, "RX_PACKET_TC_IN_CNT_1_H"},
0223 {true, "RX_PACKET_TC_IN_CNT_2_L"},
0224 {true, "RX_PACKET_TC_IN_CNT_2_H"},
0225
0226 {true, "RX_PACKET_TC_IN_CNT_3_L"},
0227 {true, "RX_PACKET_TC_IN_CNT_3_H"},
0228 {true, "RX_PACKET_TC_IN_CNT_4_L"},
0229 {true, "RX_PACKET_TC_IN_CNT_4_H"},
0230 {true, "RX_PACKET_TC_IN_CNT_5_L"},
0231 {true, "RX_PACKET_TC_IN_CNT_5_H"},
0232
0233 {true, "RX_PACKET_TC_IN_CNT_6_L"},
0234 {true, "RX_PACKET_TC_IN_CNT_6_H"},
0235 {true, "RX_PACKET_TC_IN_CNT_7_L"},
0236 {true, "RX_PACKET_TC_IN_CNT_7_H"},
0237 {true, "RX_PACKET_TC_OUT_CNT_0_L"},
0238 {true, "RX_PACKET_TC_OUT_CNT_0_H"},
0239
0240 {true, "RX_PACKET_TC_OUT_CNT_1_L"},
0241 {true, "RX_PACKET_TC_OUT_CNT_1_H"},
0242 {true, "RX_PACKET_TC_OUT_CNT_2_L"},
0243 {true, "RX_PACKET_TC_OUT_CNT_2_H"},
0244 {true, "RX_PACKET_TC_OUT_CNT_3_L"},
0245 {true, "RX_PACKET_TC_OUT_CNT_3_H"},
0246
0247 {true, "RX_PACKET_TC_OUT_CNT_4_L"},
0248 {true, "RX_PACKET_TC_OUT_CNT_4_H"},
0249 {true, "RX_PACKET_TC_OUT_CNT_5_L"},
0250 {true, "RX_PACKET_TC_OUT_CNT_5_H"},
0251 {true, "RX_PACKET_TC_OUT_CNT_6_L"},
0252 {true, "RX_PACKET_TC_OUT_CNT_6_H"},
0253
0254 {true, "RX_PACKET_TC_OUT_CNT_7_L"},
0255 {true, "RX_PACKET_TC_OUT_CNT_7_H"},
0256 {true, "TX_PACKET_TC_IN_CNT_0_L"},
0257 {true, "TX_PACKET_TC_IN_CNT_0_H"},
0258 {true, "TX_PACKET_TC_IN_CNT_1_L"},
0259 {true, "TX_PACKET_TC_IN_CNT_1_H"},
0260
0261 {true, "TX_PACKET_TC_IN_CNT_2_L"},
0262 {true, "TX_PACKET_TC_IN_CNT_2_H"},
0263 {true, "TX_PACKET_TC_IN_CNT_3_L"},
0264 {true, "TX_PACKET_TC_IN_CNT_3_H"},
0265 {true, "TX_PACKET_TC_IN_CNT_4_L"},
0266 {true, "TX_PACKET_TC_IN_CNT_4_H"},
0267
0268 {true, "TX_PACKET_TC_IN_CNT_5_L"},
0269 {true, "TX_PACKET_TC_IN_CNT_5_H"},
0270 {true, "TX_PACKET_TC_IN_CNT_6_L"},
0271 {true, "TX_PACKET_TC_IN_CNT_6_H"},
0272 {true, "TX_PACKET_TC_IN_CNT_7_L"},
0273 {true, "TX_PACKET_TC_IN_CNT_7_H"},
0274
0275 {true, "TX_PACKET_TC_OUT_CNT_0_L"},
0276 {true, "TX_PACKET_TC_OUT_CNT_0_H"},
0277 {true, "TX_PACKET_TC_OUT_CNT_1_L"},
0278 {true, "TX_PACKET_TC_OUT_CNT_1_H"},
0279 {true, "TX_PACKET_TC_OUT_CNT_2_L"},
0280 {true, "TX_PACKET_TC_OUT_CNT_2_H"},
0281
0282 {true, "TX_PACKET_TC_OUT_CNT_3_L"},
0283 {true, "TX_PACKET_TC_OUT_CNT_3_H"},
0284 {true, "TX_PACKET_TC_OUT_CNT_4_L"},
0285 {true, "TX_PACKET_TC_OUT_CNT_4_H"},
0286 {true, "TX_PACKET_TC_OUT_CNT_5_L"},
0287 {true, "TX_PACKET_TC_OUT_CNT_5_H"},
0288
0289 {true, "TX_PACKET_TC_OUT_CNT_6_L"},
0290 {true, "TX_PACKET_TC_OUT_CNT_6_H"},
0291 {true, "TX_PACKET_TC_OUT_CNT_7_L"},
0292 {true, "TX_PACKET_TC_OUT_CNT_7_H"},
0293 {false, "Reserved"},
0294 {false, "Reserved"},
0295 };
0296
0297 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = {
0298 {true, "OQ_INDEX"},
0299 {true, "QUEUE_CNT"},
0300 {false, "Reserved"},
0301 {false, "Reserved"},
0302 {false, "Reserved"},
0303 {false, "Reserved"},
0304 };
0305
0306 static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = {
0307 {true, "prt_id"},
0308 {true, "IGU_RX_ERR_PKT"},
0309 {true, "IGU_RX_NO_SOF_PKT"},
0310 {true, "EGU_TX_1588_SHORT_PKT"},
0311 {true, "EGU_TX_1588_PKT"},
0312 {true, "EGU_TX_ERR_PKT"},
0313
0314 {true, "IGU_RX_OUT_L2_PKT"},
0315 {true, "IGU_RX_OUT_L3_PKT"},
0316 {true, "IGU_RX_OUT_L4_PKT"},
0317 {true, "IGU_RX_IN_L2_PKT"},
0318 {true, "IGU_RX_IN_L3_PKT"},
0319 {true, "IGU_RX_IN_L4_PKT"},
0320
0321 {true, "IGU_RX_EL3E_PKT"},
0322 {true, "IGU_RX_EL4E_PKT"},
0323 {true, "IGU_RX_L3E_PKT"},
0324 {true, "IGU_RX_L4E_PKT"},
0325 {true, "IGU_RX_ROCEE_PKT"},
0326 {true, "IGU_RX_OUT_UDP0_PKT"},
0327
0328 {true, "IGU_RX_IN_UDP0_PKT"},
0329 {true, "IGU_MC_CAR_DROP_PKT_L"},
0330 {true, "IGU_MC_CAR_DROP_PKT_H"},
0331 {true, "IGU_BC_CAR_DROP_PKT_L"},
0332 {true, "IGU_BC_CAR_DROP_PKT_H"},
0333 {false, "Reserved"},
0334
0335 {true, "IGU_RX_OVERSIZE_PKT_L"},
0336 {true, "IGU_RX_OVERSIZE_PKT_H"},
0337 {true, "IGU_RX_UNDERSIZE_PKT_L"},
0338 {true, "IGU_RX_UNDERSIZE_PKT_H"},
0339 {true, "IGU_RX_OUT_ALL_PKT_L"},
0340 {true, "IGU_RX_OUT_ALL_PKT_H"},
0341
0342 {true, "IGU_TX_OUT_ALL_PKT_L"},
0343 {true, "IGU_TX_OUT_ALL_PKT_H"},
0344 {true, "IGU_RX_UNI_PKT_L"},
0345 {true, "IGU_RX_UNI_PKT_H"},
0346 {true, "IGU_RX_MULTI_PKT_L"},
0347 {true, "IGU_RX_MULTI_PKT_H"},
0348
0349 {true, "IGU_RX_BROAD_PKT_L"},
0350 {true, "IGU_RX_BROAD_PKT_H"},
0351 {true, "EGU_TX_OUT_ALL_PKT_L"},
0352 {true, "EGU_TX_OUT_ALL_PKT_H"},
0353 {true, "EGU_TX_UNI_PKT_L"},
0354 {true, "EGU_TX_UNI_PKT_H"},
0355
0356 {true, "EGU_TX_MULTI_PKT_L"},
0357 {true, "EGU_TX_MULTI_PKT_H"},
0358 {true, "EGU_TX_BROAD_PKT_L"},
0359 {true, "EGU_TX_BROAD_PKT_H"},
0360 {true, "IGU_TX_KEY_NUM_L"},
0361 {true, "IGU_TX_KEY_NUM_H"},
0362
0363 {true, "IGU_RX_NON_TUN_PKT_L"},
0364 {true, "IGU_RX_NON_TUN_PKT_H"},
0365 {true, "IGU_RX_TUN_PKT_L"},
0366 {true, "IGU_RX_TUN_PKT_H"},
0367 {false, "Reserved"},
0368 {false, "Reserved"},
0369 };
0370
0371 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = {
0372 {true, "tc_queue_num"},
0373 {true, "FSM_DFX_ST0"},
0374 {true, "FSM_DFX_ST1"},
0375 {true, "RPU_RX_PKT_DROP_CNT"},
0376 {true, "BUF_WAIT_TIMEOUT"},
0377 {true, "BUF_WAIT_TIMEOUT_QID"},
0378 };
0379
0380 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = {
0381 {false, "Reserved"},
0382 {true, "FIFO_DFX_ST0"},
0383 {true, "FIFO_DFX_ST1"},
0384 {true, "FIFO_DFX_ST2"},
0385 {true, "FIFO_DFX_ST3"},
0386 {true, "FIFO_DFX_ST4"},
0387
0388 {true, "FIFO_DFX_ST5"},
0389 {false, "Reserved"},
0390 {false, "Reserved"},
0391 {false, "Reserved"},
0392 {false, "Reserved"},
0393 {false, "Reserved"},
0394 };
0395
0396 static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = {
0397 {false, "Reserved"},
0398 {true, "NCSI_EGU_TX_FIFO_STS"},
0399 {true, "NCSI_PAUSE_STATUS"},
0400 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"},
0401 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"},
0402 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"},
0403
0404 {true, "NCSI_RX_CTRL_PKT_CNT"},
0405 {true, "NCSI_RX_PT_DMAC_ERR_CNT"},
0406 {true, "NCSI_RX_PT_SMAC_ERR_CNT"},
0407 {true, "NCSI_RX_PT_PKT_CNT"},
0408 {true, "NCSI_RX_FCS_ERR_CNT"},
0409 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"},
0410
0411 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"},
0412 {true, "NCSI_TX_CTRL_PKT_CNT"},
0413 {true, "NCSI_TX_PT_DMAC_ERR_CNT"},
0414 {true, "NCSI_TX_PT_SMAC_ERR_CNT"},
0415 {true, "NCSI_TX_PT_PKT_CNT"},
0416 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"},
0417
0418 {true, "NCSI_TX_PT_PKT_ERR_CNT"},
0419 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"},
0420 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"},
0421 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"},
0422 {false, "Reserved"},
0423 {false, "Reserved"},
0424
0425 {true, "NCSI_MAC_RX_OCTETS_OK"},
0426 {true, "NCSI_MAC_RX_OCTETS_BAD"},
0427 {true, "NCSI_MAC_RX_UC_PKTS"},
0428 {true, "NCSI_MAC_RX_MC_PKTS"},
0429 {true, "NCSI_MAC_RX_BC_PKTS"},
0430 {true, "NCSI_MAC_RX_PKTS_64OCTETS"},
0431
0432 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"},
0433 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"},
0434 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"},
0435 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"},
0436 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"},
0437 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"},
0438
0439 {true, "NCSI_MAC_RX_FCS_ERRORS"},
0440 {true, "NCSI_MAC_RX_LONG_ERRORS"},
0441 {true, "NCSI_MAC_RX_JABBER_ERRORS"},
0442 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"},
0443 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"},
0444 {true, "NCSI_MAC_RX_FILT_PKT_CNT"},
0445
0446 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"},
0447 {true, "NCSI_MAC_TX_OCTETS_OK"},
0448 {true, "NCSI_MAC_TX_OCTETS_BAD"},
0449 {true, "NCSI_MAC_TX_UC_PKTS"},
0450 {true, "NCSI_MAC_TX_MC_PKTS"},
0451 {true, "NCSI_MAC_TX_BC_PKTS"},
0452
0453 {true, "NCSI_MAC_TX_PKTS_64OCTETS"},
0454 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"},
0455 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"},
0456 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"},
0457 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"},
0458 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"},
0459
0460 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"},
0461 {true, "NCSI_MAC_TX_UNDERRUN"},
0462 {true, "NCSI_MAC_TX_CRC_ERROR"},
0463 {true, "NCSI_MAC_TX_PAUSE_FRAMES"},
0464 {true, "NCSI_MAC_RX_PAD_PKTS"},
0465 {true, "NCSI_MAC_RX_PAUSE_FRAMES"},
0466 };
0467
0468 static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = {
0469 {false, "Reserved"},
0470 {true, "LGE_IGU_AFIFO_DFX_0"},
0471 {true, "LGE_IGU_AFIFO_DFX_1"},
0472 {true, "LGE_IGU_AFIFO_DFX_2"},
0473 {true, "LGE_IGU_AFIFO_DFX_3"},
0474 {true, "LGE_IGU_AFIFO_DFX_4"},
0475
0476 {true, "LGE_IGU_AFIFO_DFX_5"},
0477 {true, "LGE_IGU_AFIFO_DFX_6"},
0478 {true, "LGE_IGU_AFIFO_DFX_7"},
0479 {true, "LGE_EGU_AFIFO_DFX_0"},
0480 {true, "LGE_EGU_AFIFO_DFX_1"},
0481 {true, "LGE_EGU_AFIFO_DFX_2"},
0482
0483 {true, "LGE_EGU_AFIFO_DFX_3"},
0484 {true, "LGE_EGU_AFIFO_DFX_4"},
0485 {true, "LGE_EGU_AFIFO_DFX_5"},
0486 {true, "LGE_EGU_AFIFO_DFX_6"},
0487 {true, "LGE_EGU_AFIFO_DFX_7"},
0488 {true, "CGE_IGU_AFIFO_DFX_0"},
0489
0490 {true, "CGE_IGU_AFIFO_DFX_1"},
0491 {true, "CGE_EGU_AFIFO_DFX_0"},
0492 {true, "CGE_EGU_AFIFO_DFX_1"},
0493 {false, "Reserved"},
0494 {false, "Reserved"},
0495 {false, "Reserved"},
0496 };
0497
0498 static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = {
0499 {false, "Reserved"},
0500 {true, "DROP_FROM_PRT_PKT_CNT"},
0501 {true, "DROP_FROM_HOST_PKT_CNT"},
0502 {true, "DROP_TX_VLAN_PROC_CNT"},
0503 {true, "DROP_MNG_CNT"},
0504 {true, "DROP_FD_CNT"},
0505
0506 {true, "DROP_NO_DST_CNT"},
0507 {true, "DROP_MC_MBID_FULL_CNT"},
0508 {true, "DROP_SC_FILTERED"},
0509 {true, "PPP_MC_DROP_PKT_CNT"},
0510 {true, "DROP_PT_CNT"},
0511 {true, "DROP_MAC_ANTI_SPOOF_CNT"},
0512
0513 {true, "DROP_IG_VFV_CNT"},
0514 {true, "DROP_IG_PRTV_CNT"},
0515 {true, "DROP_CNM_PFC_PAUSE_CNT"},
0516 {true, "DROP_TORUS_TC_CNT"},
0517 {true, "DROP_TORUS_LPBK_CNT"},
0518 {true, "PPP_HFS_STS"},
0519
0520 {true, "PPP_MC_RSLT_STS"},
0521 {true, "PPP_P3U_STS"},
0522 {true, "PPP_RSLT_DESCR_STS"},
0523 {true, "PPP_UMV_STS_0"},
0524 {true, "PPP_UMV_STS_1"},
0525 {true, "PPP_VFV_STS"},
0526
0527 {true, "PPP_GRO_KEY_CNT"},
0528 {true, "PPP_GRO_INFO_CNT"},
0529 {true, "PPP_GRO_DROP_CNT"},
0530 {true, "PPP_GRO_OUT_CNT"},
0531 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"},
0532 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"},
0533
0534 {true, "PPP_GRO_INFO_MATCH_CNT"},
0535 {true, "PPP_GRO_FREE_ENTRY_CNT"},
0536 {true, "PPP_GRO_INNER_DFX_SIGNAL"},
0537 {false, "Reserved"},
0538 {false, "Reserved"},
0539 {false, "Reserved"},
0540
0541 {true, "GET_RX_PKT_CNT_L"},
0542 {true, "GET_RX_PKT_CNT_H"},
0543 {true, "GET_TX_PKT_CNT_L"},
0544 {true, "GET_TX_PKT_CNT_H"},
0545 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"},
0546 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"},
0547
0548 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"},
0549 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"},
0550 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"},
0551 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"},
0552 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"},
0553 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"},
0554
0555 {true, "SEND_MC_FROM_PRT_CNT_L"},
0556 {true, "SEND_MC_FROM_PRT_CNT_H"},
0557 {true, "SEND_MC_FROM_HOST_CNT_L"},
0558 {true, "SEND_MC_FROM_HOST_CNT_H"},
0559 {true, "SSU_MC_RD_CNT_L"},
0560 {true, "SSU_MC_RD_CNT_H"},
0561
0562 {true, "SSU_MC_DROP_CNT_L"},
0563 {true, "SSU_MC_DROP_CNT_H"},
0564 {true, "SSU_MC_RD_PKT_CNT_L"},
0565 {true, "SSU_MC_RD_PKT_CNT_H"},
0566 {true, "PPP_MC_2HOST_PKT_CNT_L"},
0567 {true, "PPP_MC_2HOST_PKT_CNT_H"},
0568
0569 {true, "PPP_MC_2PRT_PKT_CNT_L"},
0570 {true, "PPP_MC_2PRT_PKT_CNT_H"},
0571 {true, "NTSNOS_PKT_CNT_L"},
0572 {true, "NTSNOS_PKT_CNT_H"},
0573 {true, "NTUP_PKT_CNT_L"},
0574 {true, "NTUP_PKT_CNT_H"},
0575
0576 {true, "NTLCL_PKT_CNT_L"},
0577 {true, "NTLCL_PKT_CNT_H"},
0578 {true, "NTTGT_PKT_CNT_L"},
0579 {true, "NTTGT_PKT_CNT_H"},
0580 {true, "RTNS_PKT_CNT_L"},
0581 {true, "RTNS_PKT_CNT_H"},
0582
0583 {true, "RTLPBK_PKT_CNT_L"},
0584 {true, "RTLPBK_PKT_CNT_H"},
0585 {true, "NR_PKT_CNT_L"},
0586 {true, "NR_PKT_CNT_H"},
0587 {true, "RR_PKT_CNT_L"},
0588 {true, "RR_PKT_CNT_H"},
0589
0590 {true, "MNG_TBL_HIT_CNT_L"},
0591 {true, "MNG_TBL_HIT_CNT_H"},
0592 {true, "FD_TBL_HIT_CNT_L"},
0593 {true, "FD_TBL_HIT_CNT_H"},
0594 {true, "FD_LKUP_CNT_L"},
0595 {true, "FD_LKUP_CNT_H"},
0596
0597 {true, "BC_HIT_CNT_L"},
0598 {true, "BC_HIT_CNT_H"},
0599 {true, "UM_TBL_UC_HIT_CNT_L"},
0600 {true, "UM_TBL_UC_HIT_CNT_H"},
0601 {true, "UM_TBL_MC_HIT_CNT_L"},
0602 {true, "UM_TBL_MC_HIT_CNT_H"},
0603
0604 {true, "UM_TBL_VMDQ1_HIT_CNT_L"},
0605 {true, "UM_TBL_VMDQ1_HIT_CNT_H"},
0606 {true, "MTA_TBL_HIT_CNT_L"},
0607 {true, "MTA_TBL_HIT_CNT_H"},
0608 {true, "FWD_BONDING_HIT_CNT_L"},
0609 {true, "FWD_BONDING_HIT_CNT_H"},
0610
0611 {true, "PROMIS_TBL_HIT_CNT_L"},
0612 {true, "PROMIS_TBL_HIT_CNT_H"},
0613 {true, "GET_TUNL_PKT_CNT_L"},
0614 {true, "GET_TUNL_PKT_CNT_H"},
0615 {true, "GET_BMC_PKT_CNT_L"},
0616 {true, "GET_BMC_PKT_CNT_H"},
0617
0618 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"},
0619 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"},
0620 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"},
0621 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"},
0622 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"},
0623 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"},
0624
0625 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"},
0626 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"},
0627 {true, "PPP_MC_2BMC_PKT_CNT_L"},
0628 {true, "PPP_MC_2BMC_PKT_CNT_H"},
0629 {true, "VLAN_MIRR_CNT_L"},
0630 {true, "VLAN_MIRR_CNT_H"},
0631
0632 {true, "IG_MIRR_CNT_L"},
0633 {true, "IG_MIRR_CNT_H"},
0634 {true, "EG_MIRR_CNT_L"},
0635 {true, "EG_MIRR_CNT_H"},
0636 {true, "RX_DEFAULT_HOST_HIT_CNT_L"},
0637 {true, "RX_DEFAULT_HOST_HIT_CNT_H"},
0638
0639 {true, "LAN_PAIR_CNT_L"},
0640 {true, "LAN_PAIR_CNT_H"},
0641 {true, "UM_TBL_MC_HIT_PKT_CNT_L"},
0642 {true, "UM_TBL_MC_HIT_PKT_CNT_H"},
0643 {true, "MTA_TBL_HIT_PKT_CNT_L"},
0644 {true, "MTA_TBL_HIT_PKT_CNT_H"},
0645
0646 {true, "PROMIS_TBL_HIT_PKT_CNT_L"},
0647 {true, "PROMIS_TBL_HIT_PKT_CNT_H"},
0648 {false, "Reserved"},
0649 {false, "Reserved"},
0650 {false, "Reserved"},
0651 {false, "Reserved"},
0652 };
0653
0654 static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = {
0655 {false, "Reserved"},
0656 {true, "FSM_DFX_ST0"},
0657 {true, "FSM_DFX_ST1"},
0658 {true, "FSM_DFX_ST2"},
0659 {true, "FIFO_DFX_ST0"},
0660 {true, "FIFO_DFX_ST1"},
0661
0662 {true, "FIFO_DFX_ST2"},
0663 {true, "FIFO_DFX_ST3"},
0664 {true, "FIFO_DFX_ST4"},
0665 {true, "FIFO_DFX_ST5"},
0666 {true, "FIFO_DFX_ST6"},
0667 {true, "FIFO_DFX_ST7"},
0668
0669 {true, "FIFO_DFX_ST8"},
0670 {true, "FIFO_DFX_ST9"},
0671 {true, "FIFO_DFX_ST10"},
0672 {true, "FIFO_DFX_ST11"},
0673 {true, "Q_CREDIT_VLD_0"},
0674 {true, "Q_CREDIT_VLD_1"},
0675
0676 {true, "Q_CREDIT_VLD_2"},
0677 {true, "Q_CREDIT_VLD_3"},
0678 {true, "Q_CREDIT_VLD_4"},
0679 {true, "Q_CREDIT_VLD_5"},
0680 {true, "Q_CREDIT_VLD_6"},
0681 {true, "Q_CREDIT_VLD_7"},
0682
0683 {true, "Q_CREDIT_VLD_8"},
0684 {true, "Q_CREDIT_VLD_9"},
0685 {true, "Q_CREDIT_VLD_10"},
0686 {true, "Q_CREDIT_VLD_11"},
0687 {true, "Q_CREDIT_VLD_12"},
0688 {true, "Q_CREDIT_VLD_13"},
0689
0690 {true, "Q_CREDIT_VLD_14"},
0691 {true, "Q_CREDIT_VLD_15"},
0692 {true, "Q_CREDIT_VLD_16"},
0693 {true, "Q_CREDIT_VLD_17"},
0694 {true, "Q_CREDIT_VLD_18"},
0695 {true, "Q_CREDIT_VLD_19"},
0696
0697 {true, "Q_CREDIT_VLD_20"},
0698 {true, "Q_CREDIT_VLD_21"},
0699 {true, "Q_CREDIT_VLD_22"},
0700 {true, "Q_CREDIT_VLD_23"},
0701 {true, "Q_CREDIT_VLD_24"},
0702 {true, "Q_CREDIT_VLD_25"},
0703
0704 {true, "Q_CREDIT_VLD_26"},
0705 {true, "Q_CREDIT_VLD_27"},
0706 {true, "Q_CREDIT_VLD_28"},
0707 {true, "Q_CREDIT_VLD_29"},
0708 {true, "Q_CREDIT_VLD_30"},
0709 {true, "Q_CREDIT_VLD_31"},
0710
0711 {true, "GRO_BD_SERR_CNT"},
0712 {true, "GRO_CONTEXT_SERR_CNT"},
0713 {true, "RX_STASH_CFG_SERR_CNT"},
0714 {true, "AXI_RD_FBD_SERR_CNT"},
0715 {true, "GRO_BD_MERR_CNT"},
0716 {true, "GRO_CONTEXT_MERR_CNT"},
0717
0718 {true, "RX_STASH_CFG_MERR_CNT"},
0719 {true, "AXI_RD_FBD_MERR_CNT"},
0720 {false, "Reserved"},
0721 {false, "Reserved"},
0722 {false, "Reserved"},
0723 {false, "Reserved"},
0724 };
0725
0726 static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = {
0727 {true, "q_num"},
0728 {true, "RCB_CFG_RX_RING_TAIL"},
0729 {true, "RCB_CFG_RX_RING_HEAD"},
0730 {true, "RCB_CFG_RX_RING_FBDNUM"},
0731 {true, "RCB_CFG_RX_RING_OFFSET"},
0732 {true, "RCB_CFG_RX_RING_FBDOFFSET"},
0733
0734 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"},
0735 {true, "RCB_CFG_TX_RING_TAIL"},
0736 {true, "RCB_CFG_TX_RING_HEAD"},
0737 {true, "RCB_CFG_TX_RING_FBDNUM"},
0738 {true, "RCB_CFG_TX_RING_OFFSET"},
0739 {true, "RCB_CFG_TX_RING_EBDNUM"},
0740 };
0741
0742 #define HCLGE_DBG_INFO_LEN 256
0743 #define HCLGE_DBG_VLAN_FLTR_INFO_LEN 256
0744 #define HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN 512
0745 #define HCLGE_DBG_ID_LEN 16
0746 #define HCLGE_DBG_ITEM_NAME_LEN 32
0747 #define HCLGE_DBG_DATA_STR_LEN 32
0748 #define HCLGE_DBG_TM_INFO_LEN 256
0749
0750 #define HCLGE_BILLION_NANO_SECONDS 1000000000
0751
0752 struct hclge_dbg_item {
0753 char name[HCLGE_DBG_ITEM_NAME_LEN];
0754 u16 interval;
0755 };
0756
0757 struct hclge_dbg_vlan_cfg {
0758 u16 pvid;
0759 u8 accept_tag1;
0760 u8 accept_tag2;
0761 u8 accept_untag1;
0762 u8 accept_untag2;
0763 u8 insert_tag1;
0764 u8 insert_tag2;
0765 u8 shift_tag;
0766 u8 strip_tag1;
0767 u8 strip_tag2;
0768 u8 drop_tag1;
0769 u8 drop_tag2;
0770 u8 pri_only1;
0771 u8 pri_only2;
0772 };
0773
0774 #endif
