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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Copyright (c) 2018-2019 Hisilicon Limited. */
0003 
0004 #include <linux/debugfs.h>
0005 #include <linux/device.h>
0006 
0007 #include "hnae3.h"
0008 #include "hns3_debugfs.h"
0009 #include "hns3_enet.h"
0010 
0011 static struct dentry *hns3_dbgfs_root;
0012 
0013 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = {
0014     {
0015         .name = "tm"
0016     },
0017     {
0018         .name = "tx_bd_info"
0019     },
0020     {
0021         .name = "rx_bd_info"
0022     },
0023     {
0024         .name = "mac_list"
0025     },
0026     {
0027         .name = "reg"
0028     },
0029     {
0030         .name = "queue"
0031     },
0032     {
0033         .name = "fd"
0034     },
0035     /* keep common at the bottom and add new directory above */
0036     {
0037         .name = "common"
0038     },
0039 };
0040 
0041 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd);
0042 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd);
0043 
0044 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
0045     {
0046         .name = "tm_nodes",
0047         .cmd = HNAE3_DBG_CMD_TM_NODES,
0048         .dentry = HNS3_DBG_DENTRY_TM,
0049         .buf_len = HNS3_DBG_READ_LEN,
0050         .init = hns3_dbg_common_file_init,
0051     },
0052     {
0053         .name = "tm_priority",
0054         .cmd = HNAE3_DBG_CMD_TM_PRI,
0055         .dentry = HNS3_DBG_DENTRY_TM,
0056         .buf_len = HNS3_DBG_READ_LEN,
0057         .init = hns3_dbg_common_file_init,
0058     },
0059     {
0060         .name = "tm_qset",
0061         .cmd = HNAE3_DBG_CMD_TM_QSET,
0062         .dentry = HNS3_DBG_DENTRY_TM,
0063         .buf_len = HNS3_DBG_READ_LEN,
0064         .init = hns3_dbg_common_file_init,
0065     },
0066     {
0067         .name = "tm_map",
0068         .cmd = HNAE3_DBG_CMD_TM_MAP,
0069         .dentry = HNS3_DBG_DENTRY_TM,
0070         .buf_len = HNS3_DBG_READ_LEN_1MB,
0071         .init = hns3_dbg_common_file_init,
0072     },
0073     {
0074         .name = "tm_pg",
0075         .cmd = HNAE3_DBG_CMD_TM_PG,
0076         .dentry = HNS3_DBG_DENTRY_TM,
0077         .buf_len = HNS3_DBG_READ_LEN,
0078         .init = hns3_dbg_common_file_init,
0079     },
0080     {
0081         .name = "tm_port",
0082         .cmd = HNAE3_DBG_CMD_TM_PORT,
0083         .dentry = HNS3_DBG_DENTRY_TM,
0084         .buf_len = HNS3_DBG_READ_LEN,
0085         .init = hns3_dbg_common_file_init,
0086     },
0087     {
0088         .name = "tc_sch_info",
0089         .cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
0090         .dentry = HNS3_DBG_DENTRY_TM,
0091         .buf_len = HNS3_DBG_READ_LEN,
0092         .init = hns3_dbg_common_file_init,
0093     },
0094     {
0095         .name = "qos_pause_cfg",
0096         .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
0097         .dentry = HNS3_DBG_DENTRY_TM,
0098         .buf_len = HNS3_DBG_READ_LEN,
0099         .init = hns3_dbg_common_file_init,
0100     },
0101     {
0102         .name = "qos_pri_map",
0103         .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
0104         .dentry = HNS3_DBG_DENTRY_TM,
0105         .buf_len = HNS3_DBG_READ_LEN,
0106         .init = hns3_dbg_common_file_init,
0107     },
0108     {
0109         .name = "qos_buf_cfg",
0110         .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
0111         .dentry = HNS3_DBG_DENTRY_TM,
0112         .buf_len = HNS3_DBG_READ_LEN,
0113         .init = hns3_dbg_common_file_init,
0114     },
0115     {
0116         .name = "dev_info",
0117         .cmd = HNAE3_DBG_CMD_DEV_INFO,
0118         .dentry = HNS3_DBG_DENTRY_COMMON,
0119         .buf_len = HNS3_DBG_READ_LEN,
0120         .init = hns3_dbg_common_file_init,
0121     },
0122     {
0123         .name = "tx_bd_queue",
0124         .cmd = HNAE3_DBG_CMD_TX_BD,
0125         .dentry = HNS3_DBG_DENTRY_TX_BD,
0126         .buf_len = HNS3_DBG_READ_LEN_4MB,
0127         .init = hns3_dbg_bd_file_init,
0128     },
0129     {
0130         .name = "rx_bd_queue",
0131         .cmd = HNAE3_DBG_CMD_RX_BD,
0132         .dentry = HNS3_DBG_DENTRY_RX_BD,
0133         .buf_len = HNS3_DBG_READ_LEN_4MB,
0134         .init = hns3_dbg_bd_file_init,
0135     },
0136     {
0137         .name = "uc",
0138         .cmd = HNAE3_DBG_CMD_MAC_UC,
0139         .dentry = HNS3_DBG_DENTRY_MAC,
0140         .buf_len = HNS3_DBG_READ_LEN_128KB,
0141         .init = hns3_dbg_common_file_init,
0142     },
0143     {
0144         .name = "mc",
0145         .cmd = HNAE3_DBG_CMD_MAC_MC,
0146         .dentry = HNS3_DBG_DENTRY_MAC,
0147         .buf_len = HNS3_DBG_READ_LEN,
0148         .init = hns3_dbg_common_file_init,
0149     },
0150     {
0151         .name = "mng_tbl",
0152         .cmd = HNAE3_DBG_CMD_MNG_TBL,
0153         .dentry = HNS3_DBG_DENTRY_COMMON,
0154         .buf_len = HNS3_DBG_READ_LEN,
0155         .init = hns3_dbg_common_file_init,
0156     },
0157     {
0158         .name = "loopback",
0159         .cmd = HNAE3_DBG_CMD_LOOPBACK,
0160         .dentry = HNS3_DBG_DENTRY_COMMON,
0161         .buf_len = HNS3_DBG_READ_LEN,
0162         .init = hns3_dbg_common_file_init,
0163     },
0164     {
0165         .name = "interrupt_info",
0166         .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO,
0167         .dentry = HNS3_DBG_DENTRY_COMMON,
0168         .buf_len = HNS3_DBG_READ_LEN,
0169         .init = hns3_dbg_common_file_init,
0170     },
0171     {
0172         .name = "reset_info",
0173         .cmd = HNAE3_DBG_CMD_RESET_INFO,
0174         .dentry = HNS3_DBG_DENTRY_COMMON,
0175         .buf_len = HNS3_DBG_READ_LEN,
0176         .init = hns3_dbg_common_file_init,
0177     },
0178     {
0179         .name = "imp_info",
0180         .cmd = HNAE3_DBG_CMD_IMP_INFO,
0181         .dentry = HNS3_DBG_DENTRY_COMMON,
0182         .buf_len = HNS3_DBG_READ_LEN,
0183         .init = hns3_dbg_common_file_init,
0184     },
0185     {
0186         .name = "ncl_config",
0187         .cmd = HNAE3_DBG_CMD_NCL_CONFIG,
0188         .dentry = HNS3_DBG_DENTRY_COMMON,
0189         .buf_len = HNS3_DBG_READ_LEN_128KB,
0190         .init = hns3_dbg_common_file_init,
0191     },
0192     {
0193         .name = "mac_tnl_status",
0194         .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
0195         .dentry = HNS3_DBG_DENTRY_COMMON,
0196         .buf_len = HNS3_DBG_READ_LEN,
0197         .init = hns3_dbg_common_file_init,
0198     },
0199     {
0200         .name = "bios_common",
0201         .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
0202         .dentry = HNS3_DBG_DENTRY_REG,
0203         .buf_len = HNS3_DBG_READ_LEN,
0204         .init = hns3_dbg_common_file_init,
0205     },
0206     {
0207         .name = "ssu",
0208         .cmd = HNAE3_DBG_CMD_REG_SSU,
0209         .dentry = HNS3_DBG_DENTRY_REG,
0210         .buf_len = HNS3_DBG_READ_LEN,
0211         .init = hns3_dbg_common_file_init,
0212     },
0213     {
0214         .name = "igu_egu",
0215         .cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
0216         .dentry = HNS3_DBG_DENTRY_REG,
0217         .buf_len = HNS3_DBG_READ_LEN,
0218         .init = hns3_dbg_common_file_init,
0219     },
0220     {
0221         .name = "rpu",
0222         .cmd = HNAE3_DBG_CMD_REG_RPU,
0223         .dentry = HNS3_DBG_DENTRY_REG,
0224         .buf_len = HNS3_DBG_READ_LEN,
0225         .init = hns3_dbg_common_file_init,
0226     },
0227     {
0228         .name = "ncsi",
0229         .cmd = HNAE3_DBG_CMD_REG_NCSI,
0230         .dentry = HNS3_DBG_DENTRY_REG,
0231         .buf_len = HNS3_DBG_READ_LEN,
0232         .init = hns3_dbg_common_file_init,
0233     },
0234     {
0235         .name = "rtc",
0236         .cmd = HNAE3_DBG_CMD_REG_RTC,
0237         .dentry = HNS3_DBG_DENTRY_REG,
0238         .buf_len = HNS3_DBG_READ_LEN,
0239         .init = hns3_dbg_common_file_init,
0240     },
0241     {
0242         .name = "ppp",
0243         .cmd = HNAE3_DBG_CMD_REG_PPP,
0244         .dentry = HNS3_DBG_DENTRY_REG,
0245         .buf_len = HNS3_DBG_READ_LEN,
0246         .init = hns3_dbg_common_file_init,
0247     },
0248     {
0249         .name = "rcb",
0250         .cmd = HNAE3_DBG_CMD_REG_RCB,
0251         .dentry = HNS3_DBG_DENTRY_REG,
0252         .buf_len = HNS3_DBG_READ_LEN,
0253         .init = hns3_dbg_common_file_init,
0254     },
0255     {
0256         .name = "tqp",
0257         .cmd = HNAE3_DBG_CMD_REG_TQP,
0258         .dentry = HNS3_DBG_DENTRY_REG,
0259         .buf_len = HNS3_DBG_READ_LEN_128KB,
0260         .init = hns3_dbg_common_file_init,
0261     },
0262     {
0263         .name = "mac",
0264         .cmd = HNAE3_DBG_CMD_REG_MAC,
0265         .dentry = HNS3_DBG_DENTRY_REG,
0266         .buf_len = HNS3_DBG_READ_LEN,
0267         .init = hns3_dbg_common_file_init,
0268     },
0269     {
0270         .name = "dcb",
0271         .cmd = HNAE3_DBG_CMD_REG_DCB,
0272         .dentry = HNS3_DBG_DENTRY_REG,
0273         .buf_len = HNS3_DBG_READ_LEN,
0274         .init = hns3_dbg_common_file_init,
0275     },
0276     {
0277         .name = "queue_map",
0278         .cmd = HNAE3_DBG_CMD_QUEUE_MAP,
0279         .dentry = HNS3_DBG_DENTRY_QUEUE,
0280         .buf_len = HNS3_DBG_READ_LEN,
0281         .init = hns3_dbg_common_file_init,
0282     },
0283     {
0284         .name = "rx_queue_info",
0285         .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
0286         .dentry = HNS3_DBG_DENTRY_QUEUE,
0287         .buf_len = HNS3_DBG_READ_LEN_1MB,
0288         .init = hns3_dbg_common_file_init,
0289     },
0290     {
0291         .name = "tx_queue_info",
0292         .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
0293         .dentry = HNS3_DBG_DENTRY_QUEUE,
0294         .buf_len = HNS3_DBG_READ_LEN_1MB,
0295         .init = hns3_dbg_common_file_init,
0296     },
0297     {
0298         .name = "fd_tcam",
0299         .cmd = HNAE3_DBG_CMD_FD_TCAM,
0300         .dentry = HNS3_DBG_DENTRY_FD,
0301         .buf_len = HNS3_DBG_READ_LEN_1MB,
0302         .init = hns3_dbg_common_file_init,
0303     },
0304     {
0305         .name = "service_task_info",
0306         .cmd = HNAE3_DBG_CMD_SERV_INFO,
0307         .dentry = HNS3_DBG_DENTRY_COMMON,
0308         .buf_len = HNS3_DBG_READ_LEN,
0309         .init = hns3_dbg_common_file_init,
0310     },
0311     {
0312         .name = "vlan_config",
0313         .cmd = HNAE3_DBG_CMD_VLAN_CONFIG,
0314         .dentry = HNS3_DBG_DENTRY_COMMON,
0315         .buf_len = HNS3_DBG_READ_LEN,
0316         .init = hns3_dbg_common_file_init,
0317     },
0318     {
0319         .name = "ptp_info",
0320         .cmd = HNAE3_DBG_CMD_PTP_INFO,
0321         .dentry = HNS3_DBG_DENTRY_COMMON,
0322         .buf_len = HNS3_DBG_READ_LEN,
0323         .init = hns3_dbg_common_file_init,
0324     },
0325     {
0326         .name = "fd_counter",
0327         .cmd = HNAE3_DBG_CMD_FD_COUNTER,
0328         .dentry = HNS3_DBG_DENTRY_FD,
0329         .buf_len = HNS3_DBG_READ_LEN,
0330         .init = hns3_dbg_common_file_init,
0331     },
0332     {
0333         .name = "umv_info",
0334         .cmd = HNAE3_DBG_CMD_UMV_INFO,
0335         .dentry = HNS3_DBG_DENTRY_COMMON,
0336         .buf_len = HNS3_DBG_READ_LEN,
0337         .init = hns3_dbg_common_file_init,
0338     },
0339     {
0340         .name = "page_pool_info",
0341         .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO,
0342         .dentry = HNS3_DBG_DENTRY_COMMON,
0343         .buf_len = HNS3_DBG_READ_LEN,
0344         .init = hns3_dbg_common_file_init,
0345     },
0346     {
0347         .name = "coalesce_info",
0348         .cmd = HNAE3_DBG_CMD_COAL_INFO,
0349         .dentry = HNS3_DBG_DENTRY_COMMON,
0350         .buf_len = HNS3_DBG_READ_LEN_1MB,
0351         .init = hns3_dbg_common_file_init,
0352     },
0353 };
0354 
0355 static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
0356     {
0357         .name = "support FD",
0358         .cap_bit = HNAE3_DEV_SUPPORT_FD_B,
0359     }, {
0360         .name = "support GRO",
0361         .cap_bit = HNAE3_DEV_SUPPORT_GRO_B,
0362     }, {
0363         .name = "support FEC",
0364         .cap_bit = HNAE3_DEV_SUPPORT_FEC_B,
0365     }, {
0366         .name = "support UDP GSO",
0367         .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B,
0368     }, {
0369         .name = "support PTP",
0370         .cap_bit = HNAE3_DEV_SUPPORT_PTP_B,
0371     }, {
0372         .name = "support INT QL",
0373         .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B,
0374     }, {
0375         .name = "support HW TX csum",
0376         .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
0377     }, {
0378         .name = "support UDP tunnel csum",
0379         .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
0380     }, {
0381         .name = "support TX push",
0382         .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B,
0383     }, {
0384         .name = "support imp-controlled PHY",
0385         .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,
0386     }, {
0387         .name = "support imp-controlled RAS",
0388         .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B,
0389     }, {
0390         .name = "support rxd advanced layout",
0391         .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
0392     }, {
0393         .name = "support port vlan bypass",
0394         .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
0395     }, {
0396         .name = "support modify vlan filter state",
0397         .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
0398     }
0399 };
0400 
0401 static const struct hns3_dbg_item coal_info_items[] = {
0402     { "VEC_ID", 2 },
0403     { "ALGO_STATE", 2 },
0404     { "PROFILE_ID", 2 },
0405     { "CQE_MODE", 2 },
0406     { "TUNE_STATE", 2 },
0407     { "STEPS_LEFT", 2 },
0408     { "STEPS_RIGHT", 2 },
0409     { "TIRED", 2 },
0410     { "SW_GL", 2 },
0411     { "SW_QL", 2 },
0412     { "HW_GL", 2 },
0413     { "HW_QL", 2 },
0414 };
0415 
0416 static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" };
0417 static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" };
0418 static const char * const
0419 dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" };
0420 
0421 static void hns3_dbg_fill_content(char *content, u16 len,
0422                   const struct hns3_dbg_item *items,
0423                   const char **result, u16 size)
0424 {
0425     char *pos = content;
0426     u16 i;
0427 
0428     memset(content, ' ', len);
0429     for (i = 0; i < size; i++) {
0430         if (result)
0431             strncpy(pos, result[i], strlen(result[i]));
0432         else
0433             strncpy(pos, items[i].name, strlen(items[i].name));
0434 
0435         pos += strlen(items[i].name) + items[i].interval;
0436     }
0437 
0438     *pos++ = '\n';
0439     *pos++ = '\0';
0440 }
0441 
0442 static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector,
0443                    char **result, int i, bool is_tx)
0444 {
0445     unsigned int gl_offset, ql_offset;
0446     struct hns3_enet_coalesce *coal;
0447     unsigned int reg_val;
0448     unsigned int j = 0;
0449     struct dim *dim;
0450     bool ql_enable;
0451 
0452     if (is_tx) {
0453         coal = &tqp_vector->tx_group.coal;
0454         dim = &tqp_vector->tx_group.dim;
0455         gl_offset = HNS3_VECTOR_GL1_OFFSET;
0456         ql_offset = HNS3_VECTOR_TX_QL_OFFSET;
0457         ql_enable = tqp_vector->tx_group.coal.ql_enable;
0458     } else {
0459         coal = &tqp_vector->rx_group.coal;
0460         dim = &tqp_vector->rx_group.dim;
0461         gl_offset = HNS3_VECTOR_GL0_OFFSET;
0462         ql_offset = HNS3_VECTOR_RX_QL_OFFSET;
0463         ql_enable = tqp_vector->rx_group.coal.ql_enable;
0464     }
0465 
0466     sprintf(result[j++], "%d", i);
0467     sprintf(result[j++], "%s", dim_state_str[dim->state]);
0468     sprintf(result[j++], "%u", dim->profile_ix);
0469     sprintf(result[j++], "%s", dim_cqe_mode_str[dim->mode]);
0470     sprintf(result[j++], "%s",
0471         dim_tune_stat_str[dim->tune_state]);
0472     sprintf(result[j++], "%u", dim->steps_left);
0473     sprintf(result[j++], "%u", dim->steps_right);
0474     sprintf(result[j++], "%u", dim->tired);
0475     sprintf(result[j++], "%u", coal->int_gl);
0476     sprintf(result[j++], "%u", coal->int_ql);
0477     reg_val = readl(tqp_vector->mask_addr + gl_offset) &
0478           HNS3_VECTOR_GL_MASK;
0479     sprintf(result[j++], "%u", reg_val);
0480     if (ql_enable) {
0481         reg_val = readl(tqp_vector->mask_addr + ql_offset) &
0482               HNS3_VECTOR_QL_MASK;
0483         sprintf(result[j++], "%u", reg_val);
0484     } else {
0485         sprintf(result[j++], "NA");
0486     }
0487 }
0488 
0489 static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len,
0490                 int *pos, bool is_tx)
0491 {
0492     char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN];
0493     char *result[ARRAY_SIZE(coal_info_items)];
0494     struct hns3_enet_tqp_vector *tqp_vector;
0495     struct hns3_nic_priv *priv = h->priv;
0496     char content[HNS3_DBG_INFO_LEN];
0497     unsigned int i;
0498 
0499     for (i = 0; i < ARRAY_SIZE(coal_info_items); i++)
0500         result[i] = &data_str[i][0];
0501 
0502     *pos += scnprintf(buf + *pos, len - *pos,
0503               "%s interrupt coalesce info:\n",
0504               is_tx ? "tx" : "rx");
0505     hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
0506                   NULL, ARRAY_SIZE(coal_info_items));
0507     *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
0508 
0509     for (i = 0; i < priv->vector_num; i++) {
0510         tqp_vector = &priv->tqp_vector[i];
0511         hns3_get_coal_info(tqp_vector, result, i, is_tx);
0512         hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
0513                       (const char **)result,
0514                       ARRAY_SIZE(coal_info_items));
0515         *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
0516     }
0517 }
0518 
0519 static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len)
0520 {
0521     int pos = 0;
0522 
0523     hns3_dump_coal_info(h, buf, len, &pos, true);
0524     pos += scnprintf(buf + pos, len - pos, "\n");
0525     hns3_dump_coal_info(h, buf, len, &pos, false);
0526 
0527     return 0;
0528 }
0529 
0530 static const struct hns3_dbg_item tx_spare_info_items[] = {
0531     { "QUEUE_ID", 2 },
0532     { "COPYBREAK", 2 },
0533     { "LEN", 7 },
0534     { "NTU", 4 },
0535     { "NTC", 4 },
0536     { "LTC", 4 },
0537     { "DMA", 17 },
0538 };
0539 
0540 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf,
0541                    int len, u32 ring_num, int *pos)
0542 {
0543     char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN];
0544     struct hns3_tx_spare *tx_spare = ring->tx_spare;
0545     char *result[ARRAY_SIZE(tx_spare_info_items)];
0546     char content[HNS3_DBG_INFO_LEN];
0547     u32 i, j;
0548 
0549     if (!tx_spare) {
0550         *pos += scnprintf(buf + *pos, len - *pos,
0551                   "tx spare buffer is not enabled\n");
0552         return;
0553     }
0554 
0555     for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++)
0556         result[i] = &data_str[i][0];
0557 
0558     *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n");
0559     hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items,
0560                   NULL, ARRAY_SIZE(tx_spare_info_items));
0561     *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
0562 
0563     for (i = 0; i < ring_num; i++) {
0564         j = 0;
0565         sprintf(result[j++], "%u", i);
0566         sprintf(result[j++], "%u", ring->tx_copybreak);
0567         sprintf(result[j++], "%u", tx_spare->len);
0568         sprintf(result[j++], "%u", tx_spare->next_to_use);
0569         sprintf(result[j++], "%u", tx_spare->next_to_clean);
0570         sprintf(result[j++], "%u", tx_spare->last_to_clean);
0571         sprintf(result[j++], "%pad", &tx_spare->dma);
0572         hns3_dbg_fill_content(content, sizeof(content),
0573                       tx_spare_info_items,
0574                       (const char **)result,
0575                       ARRAY_SIZE(tx_spare_info_items));
0576         *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
0577     }
0578 }
0579 
0580 static const struct hns3_dbg_item rx_queue_info_items[] = {
0581     { "QUEUE_ID", 2 },
0582     { "BD_NUM", 2 },
0583     { "BD_LEN", 2 },
0584     { "TAIL", 2 },
0585     { "HEAD", 2 },
0586     { "FBDNUM", 2 },
0587     { "PKTNUM", 5 },
0588     { "COPYBREAK", 2 },
0589     { "RING_EN", 2 },
0590     { "RX_RING_EN", 2 },
0591     { "BASE_ADDR", 10 },
0592 };
0593 
0594 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring,
0595                     struct hnae3_ae_dev *ae_dev, char **result,
0596                     u32 index)
0597 {
0598     u32 base_add_l, base_add_h;
0599     u32 j = 0;
0600 
0601     sprintf(result[j++], "%u", index);
0602 
0603     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0604         HNS3_RING_RX_RING_BD_NUM_REG));
0605 
0606     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0607         HNS3_RING_RX_RING_BD_LEN_REG));
0608 
0609     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0610         HNS3_RING_RX_RING_TAIL_REG));
0611 
0612     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0613         HNS3_RING_RX_RING_HEAD_REG));
0614 
0615     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0616         HNS3_RING_RX_RING_FBDNUM_REG));
0617 
0618     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0619         HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
0620     sprintf(result[j++], "%u", ring->rx_copybreak);
0621 
0622     sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
0623         HNS3_RING_EN_REG) ? "on" : "off");
0624 
0625     if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
0626         sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
0627             HNS3_RING_RX_EN_REG) ? "on" : "off");
0628     else
0629         sprintf(result[j++], "%s", "NA");
0630 
0631     base_add_h = readl_relaxed(ring->tqp->io_base +
0632                     HNS3_RING_RX_RING_BASEADDR_H_REG);
0633     base_add_l = readl_relaxed(ring->tqp->io_base +
0634                     HNS3_RING_RX_RING_BASEADDR_L_REG);
0635     sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
0636 }
0637 
0638 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h,
0639                   char *buf, int len)
0640 {
0641     char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
0642     struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
0643     char *result[ARRAY_SIZE(rx_queue_info_items)];
0644     struct hns3_nic_priv *priv = h->priv;
0645     char content[HNS3_DBG_INFO_LEN];
0646     struct hns3_enet_ring *ring;
0647     int pos = 0;
0648     u32 i;
0649 
0650     if (!priv->ring) {
0651         dev_err(&h->pdev->dev, "priv->ring is NULL\n");
0652         return -EFAULT;
0653     }
0654 
0655     for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++)
0656         result[i] = &data_str[i][0];
0657 
0658     hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items,
0659                   NULL, ARRAY_SIZE(rx_queue_info_items));
0660     pos += scnprintf(buf + pos, len - pos, "%s", content);
0661     for (i = 0; i < h->kinfo.num_tqps; i++) {
0662         /* Each cycle needs to determine whether the instance is reset,
0663          * to prevent reference to invalid memory. And need to ensure
0664          * that the following code is executed within 100ms.
0665          */
0666         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
0667             test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
0668             return -EPERM;
0669 
0670         ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
0671         hns3_dump_rx_queue_info(ring, ae_dev, result, i);
0672         hns3_dbg_fill_content(content, sizeof(content),
0673                       rx_queue_info_items,
0674                       (const char **)result,
0675                       ARRAY_SIZE(rx_queue_info_items));
0676         pos += scnprintf(buf + pos, len - pos, "%s", content);
0677     }
0678 
0679     return 0;
0680 }
0681 
0682 static const struct hns3_dbg_item tx_queue_info_items[] = {
0683     { "QUEUE_ID", 2 },
0684     { "BD_NUM", 2 },
0685     { "TC", 2 },
0686     { "TAIL", 2 },
0687     { "HEAD", 2 },
0688     { "FBDNUM", 2 },
0689     { "OFFSET", 2 },
0690     { "PKTNUM", 5 },
0691     { "RING_EN", 2 },
0692     { "TX_RING_EN", 2 },
0693     { "BASE_ADDR", 10 },
0694 };
0695 
0696 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring,
0697                     struct hnae3_ae_dev *ae_dev, char **result,
0698                     u32 index)
0699 {
0700     u32 base_add_l, base_add_h;
0701     u32 j = 0;
0702 
0703     sprintf(result[j++], "%u", index);
0704     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0705         HNS3_RING_TX_RING_BD_NUM_REG));
0706 
0707     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0708         HNS3_RING_TX_RING_TC_REG));
0709 
0710     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0711         HNS3_RING_TX_RING_TAIL_REG));
0712 
0713     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0714         HNS3_RING_TX_RING_HEAD_REG));
0715 
0716     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0717         HNS3_RING_TX_RING_FBDNUM_REG));
0718 
0719     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0720         HNS3_RING_TX_RING_OFFSET_REG));
0721 
0722     sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
0723         HNS3_RING_TX_RING_PKTNUM_RECORD_REG));
0724 
0725     sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
0726         HNS3_RING_EN_REG) ? "on" : "off");
0727 
0728     if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
0729         sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
0730             HNS3_RING_TX_EN_REG) ? "on" : "off");
0731     else
0732         sprintf(result[j++], "%s", "NA");
0733 
0734     base_add_h = readl_relaxed(ring->tqp->io_base +
0735                     HNS3_RING_TX_RING_BASEADDR_H_REG);
0736     base_add_l = readl_relaxed(ring->tqp->io_base +
0737                     HNS3_RING_TX_RING_BASEADDR_L_REG);
0738     sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
0739 }
0740 
0741 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
0742                   char *buf, int len)
0743 {
0744     char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
0745     struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
0746     char *result[ARRAY_SIZE(tx_queue_info_items)];
0747     struct hns3_nic_priv *priv = h->priv;
0748     char content[HNS3_DBG_INFO_LEN];
0749     struct hns3_enet_ring *ring;
0750     int pos = 0;
0751     u32 i;
0752 
0753     if (!priv->ring) {
0754         dev_err(&h->pdev->dev, "priv->ring is NULL\n");
0755         return -EFAULT;
0756     }
0757 
0758     for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++)
0759         result[i] = &data_str[i][0];
0760 
0761     hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items,
0762                   NULL, ARRAY_SIZE(tx_queue_info_items));
0763     pos += scnprintf(buf + pos, len - pos, "%s", content);
0764 
0765     for (i = 0; i < h->kinfo.num_tqps; i++) {
0766         /* Each cycle needs to determine whether the instance is reset,
0767          * to prevent reference to invalid memory. And need to ensure
0768          * that the following code is executed within 100ms.
0769          */
0770         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
0771             test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
0772             return -EPERM;
0773 
0774         ring = &priv->ring[i];
0775         hns3_dump_tx_queue_info(ring, ae_dev, result, i);
0776         hns3_dbg_fill_content(content, sizeof(content),
0777                       tx_queue_info_items,
0778                       (const char **)result,
0779                       ARRAY_SIZE(tx_queue_info_items));
0780         pos += scnprintf(buf + pos, len - pos, "%s", content);
0781     }
0782 
0783     hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos);
0784 
0785     return 0;
0786 }
0787 
0788 static const struct hns3_dbg_item queue_map_items[] = {
0789     { "local_queue_id", 2 },
0790     { "global_queue_id", 2 },
0791     { "vector_id", 2 },
0792 };
0793 
0794 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len)
0795 {
0796     char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN];
0797     char *result[ARRAY_SIZE(queue_map_items)];
0798     struct hns3_nic_priv *priv = h->priv;
0799     char content[HNS3_DBG_INFO_LEN];
0800     int pos = 0;
0801     int j;
0802     u32 i;
0803 
0804     if (!h->ae_algo->ops->get_global_queue_id)
0805         return -EOPNOTSUPP;
0806 
0807     for (i = 0; i < ARRAY_SIZE(queue_map_items); i++)
0808         result[i] = &data_str[i][0];
0809 
0810     hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
0811                   NULL, ARRAY_SIZE(queue_map_items));
0812     pos += scnprintf(buf + pos, len - pos, "%s", content);
0813     for (i = 0; i < h->kinfo.num_tqps; i++) {
0814         if (!priv->ring || !priv->ring[i].tqp_vector)
0815             continue;
0816         j = 0;
0817         sprintf(result[j++], "%u", i);
0818         sprintf(result[j++], "%u",
0819             h->ae_algo->ops->get_global_queue_id(h, i));
0820         sprintf(result[j++], "%d",
0821             priv->ring[i].tqp_vector->vector_irq);
0822         hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
0823                       (const char **)result,
0824                       ARRAY_SIZE(queue_map_items));
0825         pos += scnprintf(buf + pos, len - pos, "%s", content);
0826     }
0827 
0828     return 0;
0829 }
0830 
0831 static const struct hns3_dbg_item rx_bd_info_items[] = {
0832     { "BD_IDX", 3 },
0833     { "L234_INFO", 2 },
0834     { "PKT_LEN", 3 },
0835     { "SIZE", 4 },
0836     { "RSS_HASH", 4 },
0837     { "FD_ID", 2 },
0838     { "VLAN_TAG", 2 },
0839     { "O_DM_VLAN_ID_FB", 2 },
0840     { "OT_VLAN_TAG", 2 },
0841     { "BD_BASE_INFO", 2 },
0842     { "PTYPE", 2 },
0843     { "HW_CSUM", 2 },
0844 };
0845 
0846 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv,
0847                  struct hns3_desc *desc, char **result, int idx)
0848 {
0849     unsigned int j = 0;
0850 
0851     sprintf(result[j++], "%d", idx);
0852     sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info));
0853     sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len));
0854     sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size));
0855     sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash));
0856     sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id));
0857     sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag));
0858     sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb));
0859     sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag));
0860     sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info));
0861     if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
0862         u32 ol_info = le32_to_cpu(desc->rx.ol_info);
0863 
0864         sprintf(result[j++], "%5lu", hnae3_get_field(ol_info,
0865                                  HNS3_RXD_PTYPE_M,
0866                                  HNS3_RXD_PTYPE_S));
0867         sprintf(result[j++], "%7u", le16_to_cpu(desc->csum));
0868     } else {
0869         sprintf(result[j++], "NA");
0870         sprintf(result[j++], "NA");
0871     }
0872 }
0873 
0874 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
0875 {
0876     char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
0877     struct hns3_nic_priv *priv = d->handle->priv;
0878     char *result[ARRAY_SIZE(rx_bd_info_items)];
0879     char content[HNS3_DBG_INFO_LEN];
0880     struct hns3_enet_ring *ring;
0881     struct hns3_desc *desc;
0882     unsigned int i;
0883     int pos = 0;
0884 
0885     if (d->qid >= d->handle->kinfo.num_tqps) {
0886         dev_err(&d->handle->pdev->dev,
0887             "queue%u is not in use\n", d->qid);
0888         return -EINVAL;
0889     }
0890 
0891     for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++)
0892         result[i] = &data_str[i][0];
0893 
0894     pos += scnprintf(buf + pos, len - pos,
0895               "Queue %u rx bd info:\n", d->qid);
0896     hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items,
0897                   NULL, ARRAY_SIZE(rx_bd_info_items));
0898     pos += scnprintf(buf + pos, len - pos, "%s", content);
0899 
0900     ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps];
0901     for (i = 0; i < ring->desc_num; i++) {
0902         desc = &ring->desc[i];
0903 
0904         hns3_dump_rx_bd_info(priv, desc, result, i);
0905         hns3_dbg_fill_content(content, sizeof(content),
0906                       rx_bd_info_items, (const char **)result,
0907                       ARRAY_SIZE(rx_bd_info_items));
0908         pos += scnprintf(buf + pos, len - pos, "%s", content);
0909     }
0910 
0911     return 0;
0912 }
0913 
0914 static const struct hns3_dbg_item tx_bd_info_items[] = {
0915     { "BD_IDX", 2 },
0916     { "ADDRESS", 13 },
0917     { "VLAN_TAG", 2 },
0918     { "SIZE", 2 },
0919     { "T_CS_VLAN_TSO", 2 },
0920     { "OT_VLAN_TAG", 3 },
0921     { "TV", 5 },
0922     { "OLT_VLAN_LEN", 2 },
0923     { "PAYLEN_OL4CS", 2 },
0924     { "BD_FE_SC_VLD", 2 },
0925     { "MSS_HW_CSUM", 0 },
0926 };
0927 
0928 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv,
0929                  struct hns3_desc *desc, char **result, int idx)
0930 {
0931     unsigned int j = 0;
0932 
0933     sprintf(result[j++], "%d", idx);
0934     sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr));
0935     sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag));
0936     sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size));
0937     sprintf(result[j++], "%#x",
0938         le32_to_cpu(desc->tx.type_cs_vlan_tso_len));
0939     sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag));
0940     sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv));
0941     sprintf(result[j++], "%u",
0942         le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
0943     sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs));
0944     sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
0945     sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum));
0946 }
0947 
0948 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
0949 {
0950     char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
0951     struct hns3_nic_priv *priv = d->handle->priv;
0952     char *result[ARRAY_SIZE(tx_bd_info_items)];
0953     char content[HNS3_DBG_INFO_LEN];
0954     struct hns3_enet_ring *ring;
0955     struct hns3_desc *desc;
0956     unsigned int i;
0957     int pos = 0;
0958 
0959     if (d->qid >= d->handle->kinfo.num_tqps) {
0960         dev_err(&d->handle->pdev->dev,
0961             "queue%u is not in use\n", d->qid);
0962         return -EINVAL;
0963     }
0964 
0965     for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++)
0966         result[i] = &data_str[i][0];
0967 
0968     pos += scnprintf(buf + pos, len - pos,
0969               "Queue %u tx bd info:\n", d->qid);
0970     hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items,
0971                   NULL, ARRAY_SIZE(tx_bd_info_items));
0972     pos += scnprintf(buf + pos, len - pos, "%s", content);
0973 
0974     ring = &priv->ring[d->qid];
0975     for (i = 0; i < ring->desc_num; i++) {
0976         desc = &ring->desc[i];
0977 
0978         hns3_dump_tx_bd_info(priv, desc, result, i);
0979         hns3_dbg_fill_content(content, sizeof(content),
0980                       tx_bd_info_items, (const char **)result,
0981                       ARRAY_SIZE(tx_bd_info_items));
0982         pos += scnprintf(buf + pos, len - pos, "%s", content);
0983     }
0984 
0985     return 0;
0986 }
0987 
0988 static void
0989 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
0990 {
0991     struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
0992     const char * const str[] = {"no", "yes"};
0993     unsigned long *caps = ae_dev->caps;
0994     u32 i, state;
0995 
0996     *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n");
0997 
0998     for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) {
0999         state = test_bit(hns3_dbg_cap[i].cap_bit, caps);
1000         *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n",
1001                   hns3_dbg_cap[i].name, str[state]);
1002     }
1003 
1004     *pos += scnprintf(buf + *pos, len - *pos, "\n");
1005 }
1006 
1007 static void
1008 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
1009 {
1010     struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1011     struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs;
1012     struct hnae3_knic_private_info *kinfo = &h->kinfo;
1013 
1014     *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n");
1015     *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n",
1016               dev_specs->mac_entry_num);
1017     *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n",
1018               dev_specs->mng_entry_num);
1019     *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n",
1020               dev_specs->max_non_tso_bd_num);
1021     *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n",
1022               dev_specs->rss_ind_tbl_size);
1023     *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n",
1024               dev_specs->rss_key_size);
1025     *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n",
1026               kinfo->rss_size);
1027     *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n",
1028               kinfo->req_rss_size);
1029     *pos += scnprintf(buf + *pos, len - *pos,
1030               "Task queue pairs numbers: %u\n",
1031               kinfo->num_tqps);
1032     *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n",
1033               kinfo->rx_buf_len);
1034     *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n",
1035               kinfo->num_tx_desc);
1036     *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n",
1037               kinfo->num_rx_desc);
1038     *pos += scnprintf(buf + *pos, len - *pos,
1039               "Total number of enabled TCs: %u\n",
1040               kinfo->tc_info.num_tc);
1041     *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n",
1042               dev_specs->int_ql_max);
1043     *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n",
1044               dev_specs->max_int_gl);
1045     *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n",
1046               dev_specs->max_tm_rate);
1047     *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
1048               dev_specs->max_qset_num);
1049     *pos += scnprintf(buf + *pos, len - *pos, "umv size: %u\n",
1050               dev_specs->umv_size);
1051     *pos += scnprintf(buf + *pos, len - *pos, "mc mac size: %u\n",
1052               dev_specs->mc_mac_size);
1053     *pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n",
1054               dev_specs->mac_stats_num);
1055 }
1056 
1057 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
1058 {
1059     int pos = 0;
1060 
1061     hns3_dbg_dev_caps(h, buf, len, &pos);
1062 
1063     hns3_dbg_dev_specs(h, buf, len, &pos);
1064 
1065     return 0;
1066 }
1067 
1068 static const struct hns3_dbg_item page_pool_info_items[] = {
1069     { "QUEUE_ID", 2 },
1070     { "ALLOCATE_CNT", 2 },
1071     { "FREE_CNT", 6 },
1072     { "POOL_SIZE(PAGE_NUM)", 2 },
1073     { "ORDER", 2 },
1074     { "NUMA_ID", 2 },
1075     { "MAX_LEN", 2 },
1076 };
1077 
1078 static void hns3_dump_page_pool_info(struct hns3_enet_ring *ring,
1079                      char **result, u32 index)
1080 {
1081     u32 j = 0;
1082 
1083     sprintf(result[j++], "%u", index);
1084     sprintf(result[j++], "%u",
1085         READ_ONCE(ring->page_pool->pages_state_hold_cnt));
1086     sprintf(result[j++], "%d",
1087         atomic_read(&ring->page_pool->pages_state_release_cnt));
1088     sprintf(result[j++], "%u", ring->page_pool->p.pool_size);
1089     sprintf(result[j++], "%u", ring->page_pool->p.order);
1090     sprintf(result[j++], "%d", ring->page_pool->p.nid);
1091     sprintf(result[j++], "%uK", ring->page_pool->p.max_len / 1024);
1092 }
1093 
1094 static int
1095 hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len)
1096 {
1097     char data_str[ARRAY_SIZE(page_pool_info_items)][HNS3_DBG_DATA_STR_LEN];
1098     char *result[ARRAY_SIZE(page_pool_info_items)];
1099     struct hns3_nic_priv *priv = h->priv;
1100     char content[HNS3_DBG_INFO_LEN];
1101     struct hns3_enet_ring *ring;
1102     int pos = 0;
1103     u32 i;
1104 
1105     if (!priv->ring) {
1106         dev_err(&h->pdev->dev, "priv->ring is NULL\n");
1107         return -EFAULT;
1108     }
1109 
1110     if (!priv->ring[h->kinfo.num_tqps].page_pool) {
1111         dev_err(&h->pdev->dev, "page pool is not initialized\n");
1112         return -EFAULT;
1113     }
1114 
1115     for (i = 0; i < ARRAY_SIZE(page_pool_info_items); i++)
1116         result[i] = &data_str[i][0];
1117 
1118     hns3_dbg_fill_content(content, sizeof(content), page_pool_info_items,
1119                   NULL, ARRAY_SIZE(page_pool_info_items));
1120     pos += scnprintf(buf + pos, len - pos, "%s", content);
1121     for (i = 0; i < h->kinfo.num_tqps; i++) {
1122         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1123             test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
1124             return -EPERM;
1125         ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
1126         hns3_dump_page_pool_info(ring, result, i);
1127         hns3_dbg_fill_content(content, sizeof(content),
1128                       page_pool_info_items,
1129                       (const char **)result,
1130                       ARRAY_SIZE(page_pool_info_items));
1131         pos += scnprintf(buf + pos, len - pos, "%s", content);
1132     }
1133 
1134     return 0;
1135 }
1136 
1137 static int hns3_dbg_get_cmd_index(struct hns3_dbg_data *dbg_data, u32 *index)
1138 {
1139     u32 i;
1140 
1141     for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1142         if (hns3_dbg_cmd[i].cmd == dbg_data->cmd) {
1143             *index = i;
1144             return 0;
1145         }
1146     }
1147 
1148     dev_err(&dbg_data->handle->pdev->dev, "unknown command(%d)\n",
1149         dbg_data->cmd);
1150     return -EINVAL;
1151 }
1152 
1153 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
1154     {
1155         .cmd = HNAE3_DBG_CMD_QUEUE_MAP,
1156         .dbg_dump = hns3_dbg_queue_map,
1157     },
1158     {
1159         .cmd = HNAE3_DBG_CMD_DEV_INFO,
1160         .dbg_dump = hns3_dbg_dev_info,
1161     },
1162     {
1163         .cmd = HNAE3_DBG_CMD_TX_BD,
1164         .dbg_dump_bd = hns3_dbg_tx_bd_info,
1165     },
1166     {
1167         .cmd = HNAE3_DBG_CMD_RX_BD,
1168         .dbg_dump_bd = hns3_dbg_rx_bd_info,
1169     },
1170     {
1171         .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
1172         .dbg_dump = hns3_dbg_rx_queue_info,
1173     },
1174     {
1175         .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
1176         .dbg_dump = hns3_dbg_tx_queue_info,
1177     },
1178     {
1179         .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO,
1180         .dbg_dump = hns3_dbg_page_pool_info,
1181     },
1182     {
1183         .cmd = HNAE3_DBG_CMD_COAL_INFO,
1184         .dbg_dump = hns3_dbg_coal_info,
1185     },
1186 };
1187 
1188 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
1189                  enum hnae3_dbg_cmd cmd, char *buf, int len)
1190 {
1191     const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops;
1192     const struct hns3_dbg_func *cmd_func;
1193     u32 i;
1194 
1195     for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) {
1196         if (cmd == hns3_dbg_cmd_func[i].cmd) {
1197             cmd_func = &hns3_dbg_cmd_func[i];
1198             if (cmd_func->dbg_dump)
1199                 return cmd_func->dbg_dump(dbg_data->handle, buf,
1200                               len);
1201             else
1202                 return cmd_func->dbg_dump_bd(dbg_data, buf,
1203                                  len);
1204         }
1205     }
1206 
1207     if (!ops->dbg_read_cmd)
1208         return -EOPNOTSUPP;
1209 
1210     return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len);
1211 }
1212 
1213 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
1214                  size_t count, loff_t *ppos)
1215 {
1216     struct hns3_dbg_data *dbg_data = filp->private_data;
1217     struct hnae3_handle *handle = dbg_data->handle;
1218     struct hns3_nic_priv *priv = handle->priv;
1219     ssize_t size = 0;
1220     char **save_buf;
1221     char *read_buf;
1222     u32 index;
1223     int ret;
1224 
1225     ret = hns3_dbg_get_cmd_index(dbg_data, &index);
1226     if (ret)
1227         return ret;
1228 
1229     mutex_lock(&handle->dbgfs_lock);
1230     save_buf = &handle->dbgfs_buf[index];
1231 
1232     if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1233         test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
1234         ret = -EBUSY;
1235         goto out;
1236     }
1237 
1238     if (*save_buf) {
1239         read_buf = *save_buf;
1240     } else {
1241         read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL);
1242         if (!read_buf) {
1243             ret = -ENOMEM;
1244             goto out;
1245         }
1246 
1247         /* save the buffer addr until the last read operation */
1248         *save_buf = read_buf;
1249 
1250         /* get data ready for the first time to read */
1251         ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd,
1252                     read_buf, hns3_dbg_cmd[index].buf_len);
1253         if (ret)
1254             goto out;
1255     }
1256 
1257     size = simple_read_from_buffer(buffer, count, ppos, read_buf,
1258                        strlen(read_buf));
1259     if (size > 0) {
1260         mutex_unlock(&handle->dbgfs_lock);
1261         return size;
1262     }
1263 
1264 out:
1265     /* free the buffer for the last read operation */
1266     if (*save_buf) {
1267         kvfree(*save_buf);
1268         *save_buf = NULL;
1269     }
1270 
1271     mutex_unlock(&handle->dbgfs_lock);
1272     return ret;
1273 }
1274 
1275 static const struct file_operations hns3_dbg_fops = {
1276     .owner = THIS_MODULE,
1277     .open  = simple_open,
1278     .read  = hns3_dbg_read,
1279 };
1280 
1281 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd)
1282 {
1283     struct dentry *entry_dir;
1284     struct hns3_dbg_data *data;
1285     u16 max_queue_num;
1286     unsigned int i;
1287 
1288     entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1289     max_queue_num = hns3_get_max_available_channels(handle);
1290     data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data),
1291                 GFP_KERNEL);
1292     if (!data)
1293         return -ENOMEM;
1294 
1295     for (i = 0; i < max_queue_num; i++) {
1296         char name[HNS3_DBG_FILE_NAME_LEN];
1297 
1298         data[i].handle = handle;
1299         data[i].cmd = hns3_dbg_cmd[cmd].cmd;
1300         data[i].qid = i;
1301         sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i);
1302         debugfs_create_file(name, 0400, entry_dir, &data[i],
1303                     &hns3_dbg_fops);
1304     }
1305 
1306     return 0;
1307 }
1308 
1309 static int
1310 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd)
1311 {
1312     struct hns3_dbg_data *data;
1313     struct dentry *entry_dir;
1314 
1315     data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL);
1316     if (!data)
1317         return -ENOMEM;
1318 
1319     data->handle = handle;
1320     data->cmd = hns3_dbg_cmd[cmd].cmd;
1321     entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1322     debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir,
1323                 data, &hns3_dbg_fops);
1324 
1325     return 0;
1326 }
1327 
1328 int hns3_dbg_init(struct hnae3_handle *handle)
1329 {
1330     struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1331     const char *name = pci_name(handle->pdev);
1332     int ret;
1333     u32 i;
1334 
1335     handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev,
1336                      ARRAY_SIZE(hns3_dbg_cmd),
1337                      sizeof(*handle->dbgfs_buf),
1338                      GFP_KERNEL);
1339     if (!handle->dbgfs_buf)
1340         return -ENOMEM;
1341 
1342     hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry =
1343                 debugfs_create_dir(name, hns3_dbgfs_root);
1344     handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry;
1345 
1346     for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++)
1347         hns3_dbg_dentry[i].dentry =
1348             debugfs_create_dir(hns3_dbg_dentry[i].name,
1349                        handle->hnae3_dbgfs);
1350 
1351     mutex_init(&handle->dbgfs_lock);
1352 
1353     for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1354         if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES &&
1355              ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) ||
1356             (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO &&
1357              !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps)))
1358             continue;
1359 
1360         if (!hns3_dbg_cmd[i].init) {
1361             dev_err(&handle->pdev->dev,
1362                 "cmd %s lack of init func\n",
1363                 hns3_dbg_cmd[i].name);
1364             ret = -EINVAL;
1365             goto out;
1366         }
1367 
1368         ret = hns3_dbg_cmd[i].init(handle, i);
1369         if (ret) {
1370             dev_err(&handle->pdev->dev, "failed to init cmd %s\n",
1371                 hns3_dbg_cmd[i].name);
1372             goto out;
1373         }
1374     }
1375 
1376     return 0;
1377 
1378 out:
1379     mutex_destroy(&handle->dbgfs_lock);
1380     debugfs_remove_recursive(handle->hnae3_dbgfs);
1381     handle->hnae3_dbgfs = NULL;
1382     return ret;
1383 }
1384 
1385 void hns3_dbg_uninit(struct hnae3_handle *handle)
1386 {
1387     u32 i;
1388 
1389     for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++)
1390         if (handle->dbgfs_buf[i]) {
1391             kvfree(handle->dbgfs_buf[i]);
1392             handle->dbgfs_buf[i] = NULL;
1393         }
1394 
1395     mutex_destroy(&handle->dbgfs_lock);
1396     debugfs_remove_recursive(handle->hnae3_dbgfs);
1397     handle->hnae3_dbgfs = NULL;
1398 }
1399 
1400 void hns3_dbg_register_debugfs(const char *debugfs_dir_name)
1401 {
1402     hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1403 }
1404 
1405 void hns3_dbg_unregister_debugfs(void)
1406 {
1407     debugfs_remove_recursive(hns3_dbgfs_root);
1408     hns3_dbgfs_root = NULL;
1409 }
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