hns3/hns3_common/hclge_comm_tqp_stats.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 // Copyright (c) 2021-2021 Hisilicon Limited.
0003
0004 #ifndef __HCLGE_COMM_TQP_STATS_H
0005 #define __HCLGE_COMM_TQP_STATS_H
0006 #include <linux/types.h>
0007 #include <linux/etherdevice.h>
0008 #include "hnae3.h"
0009
0010 /* each tqp has TX & RX two queues */
0011 #define HCLGE_COMM_QUEUE_PAIR_SIZE 2
0012
0013 /* TQP stats */
0014 struct hclge_comm_tqp_stats {
0015     /* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
0016     u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
0017     /* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
0018     u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
0019 };
0020
0021 struct hclge_comm_tqp {
0022     /* copy of device pointer from pci_dev,
0023      * used when perform DMA mapping
0024      */
0025     struct device *dev;
0026     struct hnae3_queue q;
0027     struct hclge_comm_tqp_stats tqp_stats;
0028     u16 index;  /* Global index in a NIC controller */
0029
0030     bool alloced;
0031 };
0032
0033 u64 *hclge_comm_tqps_get_stats(struct hnae3_handle *handle, u64 *data);
0034 int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle);
0035 u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data);
0036 void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle);
0037 int hclge_comm_tqps_update_stats(struct hnae3_handle *handle,
0038                  struct hclge_comm_hw *hw);
0039 #endif