hns3/hns3_common/hclge_comm_cmd.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 // Copyright (c) 2021-2021 Hisilicon Limited.
0003
0004 #ifndef __HCLGE_COMM_CMD_H
0005 #define __HCLGE_COMM_CMD_H
0006 #include <linux/types.h>
0007
0008 #include "hnae3.h"
0009
0010 #define HCLGE_COMM_CMD_FLAG_IN          BIT(0)
0011 #define HCLGE_COMM_CMD_FLAG_NEXT        BIT(2)
0012 #define HCLGE_COMM_CMD_FLAG_WR          BIT(3)
0013 #define HCLGE_COMM_CMD_FLAG_NO_INTR     BIT(4)
0014
0015 #define HCLGE_COMM_SEND_SYNC(flag) \
0016     ((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
0017
0018 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B   0
0019 #define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B   1
0020 #define HCLGE_COMM_PHY_IMP_EN_B         2
0021 #define HCLGE_COMM_MAC_STATS_EXT_EN_B       3
0022 #define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B   4
0023
0024 #define hclge_comm_dev_phy_imp_supported(ae_dev) \
0025     test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
0026
0027 #define HCLGE_COMM_TYPE_CRQ         0
0028 #define HCLGE_COMM_TYPE_CSQ         1
0029
0030 #define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME     200
0031
0032 /* bar registers for cmdq */
0033 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG   0x27000
0034 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG   0x27004
0035 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG        0x27008
0036 #define HCLGE_COMM_NIC_CSQ_TAIL_REG     0x27010
0037 #define HCLGE_COMM_NIC_CSQ_HEAD_REG     0x27014
0038 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG   0x27018
0039 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG   0x2701C
0040 #define HCLGE_COMM_NIC_CRQ_DEPTH_REG        0x27020
0041 #define HCLGE_COMM_NIC_CRQ_TAIL_REG     0x27024
0042 #define HCLGE_COMM_NIC_CRQ_HEAD_REG     0x27028
0043 /* Vector0 interrupt CMDQ event source register(RW) */
0044 #define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG     0x27100
0045 /* Vector0 interrupt CMDQ event status register(RO) */
0046 #define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG   0x27104
0047 #define HCLGE_COMM_CMDQ_INTR_EN_REG     0x27108
0048 #define HCLGE_COMM_CMDQ_INTR_GEN_REG        0x2710C
0049 #define HCLGE_COMM_CMDQ_INTR_STS_REG        0x27104
0050
0051 /* this bit indicates that the driver is ready for hardware reset */
0052 #define HCLGE_COMM_NIC_SW_RST_RDY_B     16
0053 #define HCLGE_COMM_NIC_SW_RST_RDY       BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
0054 #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S       3
0055 #define HCLGE_COMM_NIC_CMQ_DESC_NUM     1024
0056 #define HCLGE_COMM_CMDQ_TX_TIMEOUT      30000
0057
0058 enum hclge_opcode_type {
0059     /* Generic commands */
0060     HCLGE_OPC_QUERY_FW_VER      = 0x0001,
0061     HCLGE_OPC_CFG_RST_TRIGGER   = 0x0020,
0062     HCLGE_OPC_GBL_RST_STATUS    = 0x0021,
0063     HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
0064     HCLGE_OPC_QUERY_PF_RSRC     = 0x0023,
0065     HCLGE_OPC_QUERY_VF_RSRC     = 0x0024,
0066     HCLGE_OPC_GET_CFG_PARAM     = 0x0025,
0067     HCLGE_OPC_PF_RST_DONE       = 0x0026,
0068     HCLGE_OPC_QUERY_VF_RST_RDY  = 0x0027,
0069
0070     HCLGE_OPC_STATS_64_BIT      = 0x0030,
0071     HCLGE_OPC_STATS_32_BIT      = 0x0031,
0072     HCLGE_OPC_STATS_MAC     = 0x0032,
0073     HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
0074     HCLGE_OPC_STATS_MAC_ALL     = 0x0034,
0075
0076     HCLGE_OPC_QUERY_REG_NUM     = 0x0040,
0077     HCLGE_OPC_QUERY_32_BIT_REG  = 0x0041,
0078     HCLGE_OPC_QUERY_64_BIT_REG  = 0x0042,
0079     HCLGE_OPC_DFX_BD_NUM        = 0x0043,
0080     HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
0081     HCLGE_OPC_DFX_SSU_REG_0     = 0x0045,
0082     HCLGE_OPC_DFX_SSU_REG_1     = 0x0046,
0083     HCLGE_OPC_DFX_IGU_EGU_REG   = 0x0047,
0084     HCLGE_OPC_DFX_RPU_REG_0     = 0x0048,
0085     HCLGE_OPC_DFX_RPU_REG_1     = 0x0049,
0086     HCLGE_OPC_DFX_NCSI_REG      = 0x004A,
0087     HCLGE_OPC_DFX_RTC_REG       = 0x004B,
0088     HCLGE_OPC_DFX_PPP_REG       = 0x004C,
0089     HCLGE_OPC_DFX_RCB_REG       = 0x004D,
0090     HCLGE_OPC_DFX_TQP_REG       = 0x004E,
0091     HCLGE_OPC_DFX_SSU_REG_2     = 0x004F,
0092
0093     HCLGE_OPC_QUERY_DEV_SPECS   = 0x0050,
0094
0095     /* MAC command */
0096     HCLGE_OPC_CONFIG_MAC_MODE   = 0x0301,
0097     HCLGE_OPC_CONFIG_AN_MODE    = 0x0304,
0098     HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
0099     HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
0100     HCLGE_OPC_CONFIG_SPEED_DUP  = 0x0309,
0101     HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
0102     HCLGE_OPC_MAC_TNL_INT_EN    = 0x0311,
0103     HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
0104     HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
0105     HCLGE_OPC_CONFIG_FEC_MODE   = 0x031A,
0106     HCLGE_OPC_QUERY_ROH_TYPE_INFO   = 0x0389,
0107
0108     /* PTP commands */
0109     HCLGE_OPC_PTP_INT_EN        = 0x0501,
0110     HCLGE_OPC_PTP_MODE_CFG      = 0x0507,
0111
0112     /* PFC/Pause commands */
0113     HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
0114     HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
0115     HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
0116     HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
0117     HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
0118     HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
0119     HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
0120     HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
0121     HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
0122     HCLGE_OPC_QOS_MAP               = 0x070A,
0123
0124     /* ETS/scheduler commands */
0125     HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
0126     HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
0127     HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
0128     HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
0129     HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
0130     HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
0131     HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
0132     HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
0133     HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
0134     HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
0135     HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
0136     HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
0137     HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
0138     HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
0139     HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
0140     HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
0141     HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
0142     HCLGE_OPC_TM_NODES      = 0x0816,
0143     HCLGE_OPC_ETS_TC_WEIGHT     = 0x0843,
0144     HCLGE_OPC_QSET_DFX_STS      = 0x0844,
0145     HCLGE_OPC_PRI_DFX_STS       = 0x0845,
0146     HCLGE_OPC_PG_DFX_STS        = 0x0846,
0147     HCLGE_OPC_PORT_DFX_STS      = 0x0847,
0148     HCLGE_OPC_SCH_NQ_CNT        = 0x0848,
0149     HCLGE_OPC_SCH_RQ_CNT        = 0x0849,
0150     HCLGE_OPC_TM_INTERNAL_STS   = 0x0850,
0151     HCLGE_OPC_TM_INTERNAL_CNT   = 0x0851,
0152     HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
0153
0154     /* Packet buffer allocate commands */
0155     HCLGE_OPC_TX_BUFF_ALLOC     = 0x0901,
0156     HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
0157     HCLGE_OPC_RX_PRIV_WL_ALLOC  = 0x0903,
0158     HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
0159     HCLGE_OPC_RX_COM_WL_ALLOC   = 0x0905,
0160     HCLGE_OPC_RX_GBL_PKT_CNT    = 0x0906,
0161
0162     /* TQP management command */
0163     HCLGE_OPC_SET_TQP_MAP       = 0x0A01,
0164
0165     /* TQP commands */
0166     HCLGE_OPC_CFG_TX_QUEUE      = 0x0B01,
0167     HCLGE_OPC_QUERY_TX_POINTER  = 0x0B02,
0168     HCLGE_OPC_QUERY_TX_STATS    = 0x0B03,
0169     HCLGE_OPC_TQP_TX_QUEUE_TC   = 0x0B04,
0170     HCLGE_OPC_CFG_RX_QUEUE      = 0x0B11,
0171     HCLGE_OPC_QUERY_RX_POINTER  = 0x0B12,
0172     HCLGE_OPC_QUERY_RX_STATS    = 0x0B13,
0173     HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
0174     HCLGE_OPC_CFG_RX_QUEUE_LRO  = 0x0B17,
0175     HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
0176     HCLGE_OPC_RESET_TQP_QUEUE   = 0x0B22,
0177
0178     /* PPU commands */
0179     HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
0180
0181     /* TSO command */
0182     HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
0183     HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
0184
0185     /* RSS commands */
0186     HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
0187     HCLGE_OPC_RSS_INDIR_TABLE   = 0x0D07,
0188     HCLGE_OPC_RSS_TC_MODE       = 0x0D08,
0189     HCLGE_OPC_RSS_INPUT_TUPLE   = 0x0D02,
0190
0191     /* Promisuous mode command */
0192     HCLGE_OPC_CFG_PROMISC_MODE  = 0x0E01,
0193
0194     /* Vlan offload commands */
0195     HCLGE_OPC_VLAN_PORT_TX_CFG  = 0x0F01,
0196     HCLGE_OPC_VLAN_PORT_RX_CFG  = 0x0F02,
0197
0198     /* Interrupts commands */
0199     HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
0200     HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
0201
0202     /* MAC commands */
0203     HCLGE_OPC_MAC_VLAN_ADD          = 0x1000,
0204     HCLGE_OPC_MAC_VLAN_REMOVE       = 0x1001,
0205     HCLGE_OPC_MAC_VLAN_TYPE_ID      = 0x1002,
0206     HCLGE_OPC_MAC_VLAN_INSERT       = 0x1003,
0207     HCLGE_OPC_MAC_VLAN_ALLOCATE     = 0x1004,
0208     HCLGE_OPC_MAC_ETHTYPE_ADD       = 0x1010,
0209     HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
0210
0211     /* MAC VLAN commands */
0212     HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
0213
0214     /* VLAN commands */
0215     HCLGE_OPC_VLAN_FILTER_CTRL      = 0x1100,
0216     HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
0217     HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
0218     HCLGE_OPC_PORT_VLAN_BYPASS  = 0x1103,
0219
0220     /* Flow Director commands */
0221     HCLGE_OPC_FD_MODE_CTRL      = 0x1200,
0222     HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
0223     HCLGE_OPC_FD_KEY_CONFIG     = 0x1202,
0224     HCLGE_OPC_FD_TCAM_OP        = 0x1203,
0225     HCLGE_OPC_FD_AD_OP      = 0x1204,
0226     HCLGE_OPC_FD_CNT_OP     = 0x1205,
0227     HCLGE_OPC_FD_USER_DEF_OP    = 0x1207,
0228     HCLGE_OPC_FD_QB_CTRL        = 0x1210,
0229     HCLGE_OPC_FD_QB_AD_OP       = 0x1211,
0230
0231     /* MDIO command */
0232     HCLGE_OPC_MDIO_CONFIG       = 0x1900,
0233
0234     /* QCN commands */
0235     HCLGE_OPC_QCN_MOD_CFG       = 0x1A01,
0236     HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
0237     HCLGE_OPC_QCN_SHAPPING_CFG  = 0x1A03,
0238     HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
0239     HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
0240     HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
0241     HCLGE_OPC_QCN_AJUST_INIT    = 0x1A07,
0242     HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
0243
0244     /* Mailbox command */
0245     HCLGEVF_OPC_MBX_PF_TO_VF    = 0x2000,
0246     HCLGEVF_OPC_MBX_VF_TO_PF    = 0x2001,
0247
0248     /* Led command */
0249     HCLGE_OPC_LED_STATUS_CFG    = 0xB000,
0250
0251     /* clear hardware resource command */
0252     HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
0253
0254     /* NCL config command */
0255     HCLGE_OPC_QUERY_NCL_CONFIG  = 0x7011,
0256
0257     /* IMP stats command */
0258     HCLGE_OPC_IMP_STATS_BD      = 0x7012,
0259     HCLGE_OPC_IMP_STATS_INFO        = 0x7013,
0260     HCLGE_OPC_IMP_COMPAT_CFG        = 0x701A,
0261
0262     /* SFP command */
0263     HCLGE_OPC_GET_SFP_EEPROM    = 0x7100,
0264     HCLGE_OPC_GET_SFP_EXIST     = 0x7101,
0265     HCLGE_OPC_GET_SFP_INFO      = 0x7104,
0266
0267     /* Error INT commands */
0268     HCLGE_MAC_COMMON_INT_EN     = 0x030E,
0269     HCLGE_TM_SCH_ECC_INT_EN     = 0x0829,
0270     HCLGE_SSU_ECC_INT_CMD       = 0x0989,
0271     HCLGE_SSU_COMMON_INT_CMD    = 0x098C,
0272     HCLGE_PPU_MPF_ECC_INT_CMD   = 0x0B40,
0273     HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
0274     HCLGE_PPU_PF_OTHER_INT_CMD  = 0x0B42,
0275     HCLGE_COMMON_ECC_INT_CFG    = 0x1505,
0276     HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
0277     HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
0278     HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
0279     HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
0280     HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT  = 0x1514,
0281     HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT   = 0x1515,
0282     HCLGE_QUERY_ALL_ERR_BD_NUM      = 0x1516,
0283     HCLGE_QUERY_ALL_ERR_INFO        = 0x1517,
0284     HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
0285     HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
0286     HCLGE_ROCEE_PF_RAS_INT_CMD  = 0x1584,
0287     HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD  = 0x1585,
0288     HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD  = 0x1586,
0289     HCLGE_IGU_EGU_TNL_INT_EN    = 0x1803,
0290     HCLGE_IGU_COMMON_INT_EN     = 0x1806,
0291     HCLGE_TM_QCN_MEM_INT_CFG    = 0x1A14,
0292     HCLGE_PPP_CMD0_INT_CMD      = 0x2100,
0293     HCLGE_PPP_CMD1_INT_CMD      = 0x2101,
0294     HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
0295     HCLGE_NCSI_INT_EN       = 0x2401,
0296
0297     /* ROH MAC commands */
0298     HCLGE_OPC_MAC_ADDR_CHECK    = 0x9004,
0299
0300     /* PHY command */
0301     HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,
0302     HCLGE_OPC_PHY_REG       = 0x7026,
0303
0304     /* Query link diagnosis info command */
0305     HCLGE_OPC_QUERY_LINK_DIAGNOSIS  = 0x702A,
0306 };
0307
0308 enum hclge_comm_cmd_return_status {
0309     HCLGE_COMM_CMD_EXEC_SUCCESS = 0,
0310     HCLGE_COMM_CMD_NO_AUTH      = 1,
0311     HCLGE_COMM_CMD_NOT_SUPPORTED    = 2,
0312     HCLGE_COMM_CMD_QUEUE_FULL   = 3,
0313     HCLGE_COMM_CMD_NEXT_ERR     = 4,
0314     HCLGE_COMM_CMD_UNEXE_ERR    = 5,
0315     HCLGE_COMM_CMD_PARA_ERR     = 6,
0316     HCLGE_COMM_CMD_RESULT_ERR   = 7,
0317     HCLGE_COMM_CMD_TIMEOUT      = 8,
0318     HCLGE_COMM_CMD_HILINK_ERR   = 9,
0319     HCLGE_COMM_CMD_QUEUE_ILLEGAL    = 10,
0320     HCLGE_COMM_CMD_INVALID      = 11,
0321 };
0322
0323 enum HCLGE_COMM_CAP_BITS {
0324     HCLGE_COMM_CAP_UDP_GSO_B,
0325     HCLGE_COMM_CAP_QB_B,
0326     HCLGE_COMM_CAP_FD_FORWARD_TC_B,
0327     HCLGE_COMM_CAP_PTP_B,
0328     HCLGE_COMM_CAP_INT_QL_B,
0329     HCLGE_COMM_CAP_HW_TX_CSUM_B,
0330     HCLGE_COMM_CAP_TX_PUSH_B,
0331     HCLGE_COMM_CAP_PHY_IMP_B,
0332     HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,
0333     HCLGE_COMM_CAP_HW_PAD_B,
0334     HCLGE_COMM_CAP_STASH_B,
0335     HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,
0336     HCLGE_COMM_CAP_RAS_IMP_B = 12,
0337     HCLGE_COMM_CAP_FEC_B = 13,
0338     HCLGE_COMM_CAP_PAUSE_B = 14,
0339     HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
0340     HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
0341     HCLGE_COMM_CAP_CQ_B = 18,
0342 };
0343
0344 enum HCLGE_COMM_API_CAP_BITS {
0345     HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
0346 };
0347
0348 /* capabilities bits map between imp firmware and local driver */
0349 struct hclge_comm_caps_bit_map {
0350     u16 imp_bit;
0351     u16 local_bit;
0352 };
0353
0354 struct hclge_comm_firmware_compat_cmd {
0355     __le32 compat;
0356     u8 rsv[20];
0357 };
0358
0359 enum hclge_comm_cmd_state {
0360     HCLGE_COMM_STATE_CMD_DISABLE,
0361 };
0362
0363 struct hclge_comm_errcode {
0364     u32 imp_errcode;
0365     int common_errno;
0366 };
0367
0368 #define HCLGE_COMM_QUERY_CAP_LENGTH     3
0369 struct hclge_comm_query_version_cmd {
0370     __le32 firmware;
0371     __le32 hardware;
0372     __le32 api_caps;
0373     __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */
0374 };
0375
0376 #define HCLGE_DESC_DATA_LEN     6
0377 struct hclge_desc {
0378     __le16 opcode;
0379     __le16 flag;
0380     __le16 retval;
0381     __le16 rsv;
0382     __le32 data[HCLGE_DESC_DATA_LEN];
0383 };
0384
0385 struct hclge_comm_cmq_ring {
0386     dma_addr_t desc_dma_addr;
0387     struct hclge_desc *desc;
0388     struct pci_dev *pdev;
0389     u32 head;
0390     u32 tail;
0391
0392     u16 buf_size;
0393     u16 desc_num;
0394     int next_to_use;
0395     int next_to_clean;
0396     u8 ring_type; /* cmq ring type */
0397     spinlock_t lock; /* Command queue lock */
0398 };
0399
0400 enum hclge_comm_cmd_status {
0401     HCLGE_COMM_STATUS_SUCCESS   = 0,
0402     HCLGE_COMM_ERR_CSQ_FULL     = -1,
0403     HCLGE_COMM_ERR_CSQ_TIMEOUT  = -2,
0404     HCLGE_COMM_ERR_CSQ_ERROR    = -3,
0405 };
0406
0407 struct hclge_comm_cmq {
0408     struct hclge_comm_cmq_ring csq;
0409     struct hclge_comm_cmq_ring crq;
0410     u16 tx_timeout;
0411     enum hclge_comm_cmd_status last_status;
0412 };
0413
0414 struct hclge_comm_hw {
0415     void __iomem *io_base;
0416     void __iomem *mem_base;
0417     struct hclge_comm_cmq cmq;
0418     unsigned long comm_state;
0419 };
0420
0421 static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)
0422 {
0423     writel(value, base + reg);
0424 }
0425
0426 static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
0427 {
0428     u8 __iomem *reg_addr = READ_ONCE(base);
0429
0430     return readl(reg_addr + reg);
0431 }
0432
0433 #define hclge_comm_write_dev(a, reg, value) \
0434     hclge_comm_write_reg((a)->io_base, reg, value)
0435 #define hclge_comm_read_dev(a, reg) \
0436     hclge_comm_read_reg((a)->io_base, reg)
0437
0438 void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
0439 int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
0440                         struct hclge_comm_hw *hw,
0441                         u32 *fw_version, bool is_pf);
0442 int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
0443 int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
0444             int num);
0445 void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
0446 int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
0447                       struct hclge_comm_hw *hw, bool en);
0448 void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
0449 void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
0450                      enum hclge_opcode_type opcode,
0451                      bool is_read);
0452 void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
0453                struct hclge_comm_hw *hw);
0454 int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);
0455 int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
0456             u32 *fw_version, bool is_pf,
0457             unsigned long reset_pending);
0458
0459 #endif