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0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 // Copyright (c) 2016-2017 Hisilicon Limited.
0003 
0004 #ifndef __HNAE3_H
0005 #define __HNAE3_H
0006 
0007 /* Names used in this framework:
0008  *      ae handle (handle):
0009  *        a set of queues provided by AE
0010  *      ring buffer queue (rbq):
0011  *        the channel between upper layer and the AE, can do tx and rx
0012  *      ring:
0013  *        a tx or rx channel within a rbq
0014  *      ring description (desc):
0015  *        an element in the ring with packet information
0016  *      buffer:
0017  *        a memory region referred by desc with the full packet payload
0018  *
0019  * "num" means a static number set as a parameter, "count" mean a dynamic
0020  *   number set while running
0021  * "cb" means control block
0022  */
0023 
0024 #include <linux/acpi.h>
0025 #include <linux/dcbnl.h>
0026 #include <linux/delay.h>
0027 #include <linux/device.h>
0028 #include <linux/ethtool.h>
0029 #include <linux/module.h>
0030 #include <linux/netdevice.h>
0031 #include <linux/pci.h>
0032 #include <linux/pkt_sched.h>
0033 #include <linux/types.h>
0034 #include <net/pkt_cls.h>
0035 
0036 #define HNAE3_MOD_VERSION "1.0"
0037 
0038 #define HNAE3_MIN_VECTOR_NUM    2 /* first one for misc, another for IO */
0039 
0040 /* Device version */
0041 #define HNAE3_DEVICE_VERSION_V1   0x00020
0042 #define HNAE3_DEVICE_VERSION_V2   0x00021
0043 #define HNAE3_DEVICE_VERSION_V3   0x00030
0044 
0045 #define HNAE3_PCI_REVISION_BIT_SIZE     8
0046 
0047 /* Device IDs */
0048 #define HNAE3_DEV_ID_GE             0xA220
0049 #define HNAE3_DEV_ID_25GE           0xA221
0050 #define HNAE3_DEV_ID_25GE_RDMA          0xA222
0051 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC       0xA223
0052 #define HNAE3_DEV_ID_50GE_RDMA          0xA224
0053 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC       0xA225
0054 #define HNAE3_DEV_ID_100G_RDMA_MACSEC       0xA226
0055 #define HNAE3_DEV_ID_200G_RDMA          0xA228
0056 #define HNAE3_DEV_ID_VF             0xA22E
0057 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF        0xA22F
0058 
0059 #define HNAE3_CLASS_NAME_SIZE 16
0060 
0061 #define HNAE3_DEV_INITED_B          0x0
0062 #define HNAE3_DEV_SUPPORT_ROCE_B        0x1
0063 #define HNAE3_DEV_SUPPORT_DCB_B         0x2
0064 #define HNAE3_KNIC_CLIENT_INITED_B      0x3
0065 #define HNAE3_UNIC_CLIENT_INITED_B      0x4
0066 #define HNAE3_ROCE_CLIENT_INITED_B      0x5
0067 
0068 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
0069         BIT(HNAE3_DEV_SUPPORT_ROCE_B))
0070 
0071 #define hnae3_dev_roce_supported(hdev) \
0072     hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
0073 
0074 #define hnae3_dev_dcb_supported(hdev) \
0075     hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
0076 
0077 enum HNAE3_DEV_CAP_BITS {
0078     HNAE3_DEV_SUPPORT_FD_B,
0079     HNAE3_DEV_SUPPORT_GRO_B,
0080     HNAE3_DEV_SUPPORT_FEC_B,
0081     HNAE3_DEV_SUPPORT_UDP_GSO_B,
0082     HNAE3_DEV_SUPPORT_QB_B,
0083     HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
0084     HNAE3_DEV_SUPPORT_PTP_B,
0085     HNAE3_DEV_SUPPORT_INT_QL_B,
0086     HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
0087     HNAE3_DEV_SUPPORT_TX_PUSH_B,
0088     HNAE3_DEV_SUPPORT_PHY_IMP_B,
0089     HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
0090     HNAE3_DEV_SUPPORT_HW_PAD_B,
0091     HNAE3_DEV_SUPPORT_STASH_B,
0092     HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
0093     HNAE3_DEV_SUPPORT_PAUSE_B,
0094     HNAE3_DEV_SUPPORT_RAS_IMP_B,
0095     HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
0096     HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
0097     HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
0098     HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
0099     HNAE3_DEV_SUPPORT_CQ_B,
0100 };
0101 
0102 #define hnae3_dev_fd_supported(hdev) \
0103     test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)
0104 
0105 #define hnae3_dev_gro_supported(hdev) \
0106     test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps)
0107 
0108 #define hnae3_dev_fec_supported(hdev) \
0109     test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
0110 
0111 #define hnae3_dev_udp_gso_supported(hdev) \
0112     test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
0113 
0114 #define hnae3_dev_qb_supported(hdev) \
0115     test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
0116 
0117 #define hnae3_dev_fd_forward_tc_supported(hdev) \
0118     test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
0119 
0120 #define hnae3_dev_ptp_supported(hdev) \
0121     test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
0122 
0123 #define hnae3_dev_int_ql_supported(hdev) \
0124     test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
0125 
0126 #define hnae3_dev_hw_csum_supported(hdev) \
0127     test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
0128 
0129 #define hnae3_dev_tx_push_supported(hdev) \
0130     test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
0131 
0132 #define hnae3_dev_phy_imp_supported(hdev) \
0133     test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
0134 
0135 #define hnae3_dev_ras_imp_supported(hdev) \
0136     test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
0137 
0138 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \
0139     test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
0140 
0141 #define hnae3_dev_hw_pad_supported(hdev) \
0142     test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
0143 
0144 #define hnae3_dev_stash_supported(hdev) \
0145     test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
0146 
0147 #define hnae3_dev_pause_supported(hdev) \
0148     test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
0149 
0150 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
0151     test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
0152 
0153 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
0154     test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
0155 
0156 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
0157     test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
0158 
0159 #define hnae3_ae_dev_cq_supported(ae_dev) \
0160     test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
0161 
0162 enum HNAE3_PF_CAP_BITS {
0163     HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
0164 };
0165 #define ring_ptr_move_fw(ring, p) \
0166     ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
0167 #define ring_ptr_move_bw(ring, p) \
0168     ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
0169 
0170 struct hnae3_handle;
0171 
0172 struct hnae3_queue {
0173     void __iomem *io_base;
0174     void __iomem *mem_base;
0175     struct hnae3_ae_algo *ae_algo;
0176     struct hnae3_handle *handle;
0177     int tqp_index;      /* index in a handle */
0178     u32 buf_size;       /* size for hnae_desc->addr, preset by AE */
0179     u16 tx_desc_num;    /* total number of tx desc */
0180     u16 rx_desc_num;    /* total number of rx desc */
0181 };
0182 
0183 struct hns3_mac_stats {
0184     u64 tx_pause_cnt;
0185     u64 rx_pause_cnt;
0186 };
0187 
0188 /* hnae3 loop mode */
0189 enum hnae3_loop {
0190     HNAE3_LOOP_APP,
0191     HNAE3_LOOP_SERIAL_SERDES,
0192     HNAE3_LOOP_PARALLEL_SERDES,
0193     HNAE3_LOOP_PHY,
0194     HNAE3_LOOP_NONE,
0195 };
0196 
0197 enum hnae3_client_type {
0198     HNAE3_CLIENT_KNIC,
0199     HNAE3_CLIENT_ROCE,
0200 };
0201 
0202 /* mac media type */
0203 enum hnae3_media_type {
0204     HNAE3_MEDIA_TYPE_UNKNOWN,
0205     HNAE3_MEDIA_TYPE_FIBER,
0206     HNAE3_MEDIA_TYPE_COPPER,
0207     HNAE3_MEDIA_TYPE_BACKPLANE,
0208     HNAE3_MEDIA_TYPE_NONE,
0209 };
0210 
0211 /* must be consistent with definition in firmware */
0212 enum hnae3_module_type {
0213     HNAE3_MODULE_TYPE_UNKNOWN   = 0x00,
0214     HNAE3_MODULE_TYPE_FIBRE_LR  = 0x01,
0215     HNAE3_MODULE_TYPE_FIBRE_SR  = 0x02,
0216     HNAE3_MODULE_TYPE_AOC       = 0x03,
0217     HNAE3_MODULE_TYPE_CR        = 0x04,
0218     HNAE3_MODULE_TYPE_KR        = 0x05,
0219     HNAE3_MODULE_TYPE_TP        = 0x06,
0220 };
0221 
0222 enum hnae3_fec_mode {
0223     HNAE3_FEC_AUTO = 0,
0224     HNAE3_FEC_BASER,
0225     HNAE3_FEC_RS,
0226     HNAE3_FEC_USER_DEF,
0227 };
0228 
0229 enum hnae3_reset_notify_type {
0230     HNAE3_UP_CLIENT,
0231     HNAE3_DOWN_CLIENT,
0232     HNAE3_INIT_CLIENT,
0233     HNAE3_UNINIT_CLIENT,
0234 };
0235 
0236 enum hnae3_hw_error_type {
0237     HNAE3_PPU_POISON_ERROR,
0238     HNAE3_CMDQ_ECC_ERROR,
0239     HNAE3_IMP_RD_POISON_ERROR,
0240     HNAE3_ROCEE_AXI_RESP_ERROR,
0241 };
0242 
0243 enum hnae3_reset_type {
0244     HNAE3_VF_RESET,
0245     HNAE3_VF_FUNC_RESET,
0246     HNAE3_VF_PF_FUNC_RESET,
0247     HNAE3_VF_FULL_RESET,
0248     HNAE3_FLR_RESET,
0249     HNAE3_FUNC_RESET,
0250     HNAE3_GLOBAL_RESET,
0251     HNAE3_IMP_RESET,
0252     HNAE3_NONE_RESET,
0253     HNAE3_MAX_RESET,
0254 };
0255 
0256 enum hnae3_port_base_vlan_state {
0257     HNAE3_PORT_BASE_VLAN_DISABLE,
0258     HNAE3_PORT_BASE_VLAN_ENABLE,
0259     HNAE3_PORT_BASE_VLAN_MODIFY,
0260     HNAE3_PORT_BASE_VLAN_NOCHANGE,
0261 };
0262 
0263 enum hnae3_dbg_cmd {
0264     HNAE3_DBG_CMD_TM_NODES,
0265     HNAE3_DBG_CMD_TM_PRI,
0266     HNAE3_DBG_CMD_TM_QSET,
0267     HNAE3_DBG_CMD_TM_MAP,
0268     HNAE3_DBG_CMD_TM_PG,
0269     HNAE3_DBG_CMD_TM_PORT,
0270     HNAE3_DBG_CMD_TC_SCH_INFO,
0271     HNAE3_DBG_CMD_QOS_PAUSE_CFG,
0272     HNAE3_DBG_CMD_QOS_PRI_MAP,
0273     HNAE3_DBG_CMD_QOS_BUF_CFG,
0274     HNAE3_DBG_CMD_DEV_INFO,
0275     HNAE3_DBG_CMD_TX_BD,
0276     HNAE3_DBG_CMD_RX_BD,
0277     HNAE3_DBG_CMD_MAC_UC,
0278     HNAE3_DBG_CMD_MAC_MC,
0279     HNAE3_DBG_CMD_MNG_TBL,
0280     HNAE3_DBG_CMD_LOOPBACK,
0281     HNAE3_DBG_CMD_PTP_INFO,
0282     HNAE3_DBG_CMD_INTERRUPT_INFO,
0283     HNAE3_DBG_CMD_RESET_INFO,
0284     HNAE3_DBG_CMD_IMP_INFO,
0285     HNAE3_DBG_CMD_NCL_CONFIG,
0286     HNAE3_DBG_CMD_REG_BIOS_COMMON,
0287     HNAE3_DBG_CMD_REG_SSU,
0288     HNAE3_DBG_CMD_REG_IGU_EGU,
0289     HNAE3_DBG_CMD_REG_RPU,
0290     HNAE3_DBG_CMD_REG_NCSI,
0291     HNAE3_DBG_CMD_REG_RTC,
0292     HNAE3_DBG_CMD_REG_PPP,
0293     HNAE3_DBG_CMD_REG_RCB,
0294     HNAE3_DBG_CMD_REG_TQP,
0295     HNAE3_DBG_CMD_REG_MAC,
0296     HNAE3_DBG_CMD_REG_DCB,
0297     HNAE3_DBG_CMD_VLAN_CONFIG,
0298     HNAE3_DBG_CMD_QUEUE_MAP,
0299     HNAE3_DBG_CMD_RX_QUEUE_INFO,
0300     HNAE3_DBG_CMD_TX_QUEUE_INFO,
0301     HNAE3_DBG_CMD_FD_TCAM,
0302     HNAE3_DBG_CMD_FD_COUNTER,
0303     HNAE3_DBG_CMD_MAC_TNL_STATUS,
0304     HNAE3_DBG_CMD_SERV_INFO,
0305     HNAE3_DBG_CMD_UMV_INFO,
0306     HNAE3_DBG_CMD_PAGE_POOL_INFO,
0307     HNAE3_DBG_CMD_COAL_INFO,
0308     HNAE3_DBG_CMD_UNKNOWN,
0309 };
0310 
0311 struct hnae3_vector_info {
0312     u8 __iomem *io_addr;
0313     int vector;
0314 };
0315 
0316 #define HNAE3_RING_TYPE_B 0
0317 #define HNAE3_RING_TYPE_TX 0
0318 #define HNAE3_RING_TYPE_RX 1
0319 #define HNAE3_RING_GL_IDX_S 0
0320 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
0321 #define HNAE3_RING_GL_RX 0
0322 #define HNAE3_RING_GL_TX 1
0323 
0324 #define HNAE3_FW_VERSION_BYTE3_SHIFT    24
0325 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)
0326 #define HNAE3_FW_VERSION_BYTE2_SHIFT    16
0327 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)
0328 #define HNAE3_FW_VERSION_BYTE1_SHIFT    8
0329 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)
0330 #define HNAE3_FW_VERSION_BYTE0_SHIFT    0
0331 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)
0332 
0333 struct hnae3_ring_chain_node {
0334     struct hnae3_ring_chain_node *next;
0335     u32 tqp_index;
0336     u32 flag;
0337     u32 int_gl_idx;
0338 };
0339 
0340 #define HNAE3_IS_TX_RING(node) \
0341     (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
0342 
0343 /* device specification info from firmware */
0344 struct hnae3_dev_specs {
0345     u32 mac_entry_num; /* number of mac-vlan table entry */
0346     u32 mng_entry_num; /* number of manager table entry */
0347     u32 max_tm_rate;
0348     u16 rss_ind_tbl_size;
0349     u16 rss_key_size;
0350     u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
0351     u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
0352     u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
0353     u16 max_frm_size;
0354     u16 max_qset_num;
0355     u16 umv_size;
0356     u16 mc_mac_size;
0357     u32 mac_stats_num;
0358 };
0359 
0360 struct hnae3_client_ops {
0361     int (*init_instance)(struct hnae3_handle *handle);
0362     void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
0363     void (*link_status_change)(struct hnae3_handle *handle, bool state);
0364     int (*reset_notify)(struct hnae3_handle *handle,
0365                 enum hnae3_reset_notify_type type);
0366     void (*process_hw_error)(struct hnae3_handle *handle,
0367                  enum hnae3_hw_error_type);
0368 };
0369 
0370 #define HNAE3_CLIENT_NAME_LENGTH 16
0371 struct hnae3_client {
0372     char name[HNAE3_CLIENT_NAME_LENGTH];
0373     unsigned long state;
0374     enum hnae3_client_type type;
0375     const struct hnae3_client_ops *ops;
0376     struct list_head node;
0377 };
0378 
0379 #define HNAE3_DEV_CAPS_MAX_NUM  96
0380 struct hnae3_ae_dev {
0381     struct pci_dev *pdev;
0382     const struct hnae3_ae_ops *ops;
0383     struct list_head node;
0384     u32 flag;
0385     unsigned long hw_err_reset_req;
0386     struct hnae3_dev_specs dev_specs;
0387     u32 dev_version;
0388     unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
0389     void *priv;
0390 };
0391 
0392 /* This struct defines the operation on the handle.
0393  *
0394  * init_ae_dev(): (mandatory)
0395  *   Get PF configure from pci_dev and initialize PF hardware
0396  * uninit_ae_dev()
0397  *   Disable PF device and release PF resource
0398  * register_client
0399  *   Register client to ae_dev
0400  * unregister_client()
0401  *   Unregister client from ae_dev
0402  * start()
0403  *   Enable the hardware
0404  * stop()
0405  *   Disable the hardware
0406  * start_client()
0407  *   Inform the hclge that client has been started
0408  * stop_client()
0409  *   Inform the hclge that client has been stopped
0410  * get_status()
0411  *   Get the carrier state of the back channel of the handle, 1 for ok, 0 for
0412  *   non-ok
0413  * get_ksettings_an_result()
0414  *   Get negotiation status,speed and duplex
0415  * get_media_type()
0416  *   Get media type of MAC
0417  * check_port_speed()
0418  *   Check target speed whether is supported
0419  * adjust_link()
0420  *   Adjust link status
0421  * set_loopback()
0422  *   Set loopback
0423  * set_promisc_mode
0424  *   Set promisc mode
0425  * request_update_promisc_mode
0426  *   request to hclge(vf) to update promisc mode
0427  * set_mtu()
0428  *   set mtu
0429  * get_pauseparam()
0430  *   get tx and rx of pause frame use
0431  * set_pauseparam()
0432  *   set tx and rx of pause frame use
0433  * set_autoneg()
0434  *   set auto autonegotiation of pause frame use
0435  * get_autoneg()
0436  *   get auto autonegotiation of pause frame use
0437  * restart_autoneg()
0438  *   restart autonegotiation
0439  * halt_autoneg()
0440  *   halt/resume autonegotiation when autonegotiation on
0441  * get_coalesce_usecs()
0442  *   get usecs to delay a TX interrupt after a packet is sent
0443  * get_rx_max_coalesced_frames()
0444  *   get Maximum number of packets to be sent before a TX interrupt.
0445  * set_coalesce_usecs()
0446  *   set usecs to delay a TX interrupt after a packet is sent
0447  * set_coalesce_frames()
0448  *   set Maximum number of packets to be sent before a TX interrupt.
0449  * get_mac_addr()
0450  *   get mac address
0451  * set_mac_addr()
0452  *   set mac address
0453  * add_uc_addr
0454  *   Add unicast addr to mac table
0455  * rm_uc_addr
0456  *   Remove unicast addr from mac table
0457  * set_mc_addr()
0458  *   Set multicast address
0459  * add_mc_addr
0460  *   Add multicast address to mac table
0461  * rm_mc_addr
0462  *   Remove multicast address from mac table
0463  * update_stats()
0464  *   Update Old network device statistics
0465  * get_mac_stats()
0466  *   get mac pause statistics including tx_cnt and rx_cnt
0467  * get_ethtool_stats()
0468  *   Get ethtool network device statistics
0469  * get_strings()
0470  *   Get a set of strings that describe the requested objects
0471  * get_sset_count()
0472  *   Get number of strings that @get_strings will write
0473  * update_led_status()
0474  *   Update the led status
0475  * set_led_id()
0476  *   Set led id
0477  * get_regs()
0478  *   Get regs dump
0479  * get_regs_len()
0480  *   Get the len of the regs dump
0481  * get_rss_key_size()
0482  *   Get rss key size
0483  * get_rss()
0484  *   Get rss table
0485  * set_rss()
0486  *   Set rss table
0487  * get_tc_size()
0488  *   Get tc size of handle
0489  * get_vector()
0490  *   Get vector number and vector information
0491  * put_vector()
0492  *   Put the vector in hdev
0493  * map_ring_to_vector()
0494  *   Map rings to vector
0495  * unmap_ring_from_vector()
0496  *   Unmap rings from vector
0497  * reset_queue()
0498  *   Reset queue
0499  * get_fw_version()
0500  *   Get firmware version
0501  * get_mdix_mode()
0502  *   Get media typr of phy
0503  * enable_vlan_filter()
0504  *   Enable vlan filter
0505  * set_vlan_filter()
0506  *   Set vlan filter config of Ports
0507  * set_vf_vlan_filter()
0508  *   Set vlan filter config of vf
0509  * enable_hw_strip_rxvtag()
0510  *   Enable/disable hardware strip vlan tag of packets received
0511  * set_gro_en
0512  *   Enable/disable HW GRO
0513  * add_arfs_entry
0514  *   Check the 5-tuples of flow, and create flow director rule
0515  * get_vf_config
0516  *   Get the VF configuration setting by the host
0517  * set_vf_link_state
0518  *   Set VF link status
0519  * set_vf_spoofchk
0520  *   Enable/disable spoof check for specified vf
0521  * set_vf_trust
0522  *   Enable/disable trust for specified vf, if the vf being trusted, then
0523  *   it can enable promisc mode
0524  * set_vf_rate
0525  *   Set the max tx rate of specified vf.
0526  * set_vf_mac
0527  *   Configure the default MAC for specified VF
0528  * get_module_eeprom
0529  *   Get the optical module eeprom info.
0530  * add_cls_flower
0531  *   Add clsflower rule
0532  * del_cls_flower
0533  *   Delete clsflower rule
0534  * cls_flower_active
0535  *   Check if any cls flower rule exist
0536  * dbg_read_cmd
0537  *   Execute debugfs read command.
0538  * set_tx_hwts_info
0539  *   Save information for 1588 tx packet
0540  * get_rx_hwts
0541  *   Get 1588 rx hwstamp
0542  * get_ts_info
0543  *   Get phc info
0544  * clean_vf_config
0545  *   Clean residual vf info after disable sriov
0546  */
0547 struct hnae3_ae_ops {
0548     int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
0549     void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
0550     void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
0551                   enum hnae3_reset_type rst_type);
0552     void (*reset_done)(struct hnae3_ae_dev *ae_dev);
0553     int (*init_client_instance)(struct hnae3_client *client,
0554                     struct hnae3_ae_dev *ae_dev);
0555     void (*uninit_client_instance)(struct hnae3_client *client,
0556                        struct hnae3_ae_dev *ae_dev);
0557     int (*start)(struct hnae3_handle *handle);
0558     void (*stop)(struct hnae3_handle *handle);
0559     int (*client_start)(struct hnae3_handle *handle);
0560     void (*client_stop)(struct hnae3_handle *handle);
0561     int (*get_status)(struct hnae3_handle *handle);
0562     void (*get_ksettings_an_result)(struct hnae3_handle *handle,
0563                     u8 *auto_neg, u32 *speed, u8 *duplex);
0564 
0565     int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
0566                    u8 duplex);
0567 
0568     void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
0569                    u8 *module_type);
0570     int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
0571     void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
0572             u8 *fec_mode);
0573     int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
0574     void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
0575     int (*set_loopback)(struct hnae3_handle *handle,
0576                 enum hnae3_loop loop_mode, bool en);
0577 
0578     int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
0579                 bool en_mc_pmc);
0580     void (*request_update_promisc_mode)(struct hnae3_handle *handle);
0581     int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
0582 
0583     void (*get_pauseparam)(struct hnae3_handle *handle,
0584                    u32 *auto_neg, u32 *rx_en, u32 *tx_en);
0585     int (*set_pauseparam)(struct hnae3_handle *handle,
0586                   u32 auto_neg, u32 rx_en, u32 tx_en);
0587 
0588     int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
0589     int (*get_autoneg)(struct hnae3_handle *handle);
0590     int (*restart_autoneg)(struct hnae3_handle *handle);
0591     int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
0592 
0593     void (*get_coalesce_usecs)(struct hnae3_handle *handle,
0594                    u32 *tx_usecs, u32 *rx_usecs);
0595     void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
0596                         u32 *tx_frames, u32 *rx_frames);
0597     int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
0598     int (*set_coalesce_frames)(struct hnae3_handle *handle,
0599                    u32 coalesce_frames);
0600     void (*get_coalesce_range)(struct hnae3_handle *handle,
0601                    u32 *tx_frames_low, u32 *rx_frames_low,
0602                    u32 *tx_frames_high, u32 *rx_frames_high,
0603                    u32 *tx_usecs_low, u32 *rx_usecs_low,
0604                    u32 *tx_usecs_high, u32 *rx_usecs_high);
0605 
0606     void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
0607     int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,
0608                 bool is_first);
0609     int (*do_ioctl)(struct hnae3_handle *handle,
0610             struct ifreq *ifr, int cmd);
0611     int (*add_uc_addr)(struct hnae3_handle *handle,
0612                const unsigned char *addr);
0613     int (*rm_uc_addr)(struct hnae3_handle *handle,
0614               const unsigned char *addr);
0615     int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
0616     int (*add_mc_addr)(struct hnae3_handle *handle,
0617                const unsigned char *addr);
0618     int (*rm_mc_addr)(struct hnae3_handle *handle,
0619               const unsigned char *addr);
0620     void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
0621     void (*update_stats)(struct hnae3_handle *handle,
0622                  struct net_device_stats *net_stats);
0623     void (*get_stats)(struct hnae3_handle *handle, u64 *data);
0624     void (*get_mac_stats)(struct hnae3_handle *handle,
0625                   struct hns3_mac_stats *mac_stats);
0626     void (*get_strings)(struct hnae3_handle *handle,
0627                 u32 stringset, u8 *data);
0628     int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
0629 
0630     void (*get_regs)(struct hnae3_handle *handle, u32 *version,
0631              void *data);
0632     int (*get_regs_len)(struct hnae3_handle *handle);
0633 
0634     u32 (*get_rss_key_size)(struct hnae3_handle *handle);
0635     int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
0636                u8 *hfunc);
0637     int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
0638                const u8 *key, const u8 hfunc);
0639     int (*set_rss_tuple)(struct hnae3_handle *handle,
0640                  struct ethtool_rxnfc *cmd);
0641     int (*get_rss_tuple)(struct hnae3_handle *handle,
0642                  struct ethtool_rxnfc *cmd);
0643 
0644     int (*get_tc_size)(struct hnae3_handle *handle);
0645 
0646     int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
0647               struct hnae3_vector_info *vector_info);
0648     int (*put_vector)(struct hnae3_handle *handle, int vector_num);
0649     int (*map_ring_to_vector)(struct hnae3_handle *handle,
0650                   int vector_num,
0651                   struct hnae3_ring_chain_node *vr_chain);
0652     int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
0653                       int vector_num,
0654                       struct hnae3_ring_chain_node *vr_chain);
0655 
0656     int (*reset_queue)(struct hnae3_handle *handle);
0657     u32 (*get_fw_version)(struct hnae3_handle *handle);
0658     void (*get_mdix_mode)(struct hnae3_handle *handle,
0659                   u8 *tp_mdix_ctrl, u8 *tp_mdix);
0660 
0661     int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
0662     int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
0663                    u16 vlan_id, bool is_kill);
0664     int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
0665                   u16 vlan, u8 qos, __be16 proto);
0666     int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
0667     void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
0668     enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
0669                          unsigned long *addr);
0670     void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
0671                       enum hnae3_reset_type rst_type);
0672     void (*get_channels)(struct hnae3_handle *handle,
0673                  struct ethtool_channels *ch);
0674     void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
0675                       u16 *alloc_tqps, u16 *max_rss_size);
0676     int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
0677                 bool rxfh_configured);
0678     void (*get_flowctrl_adv)(struct hnae3_handle *handle,
0679                  u32 *flowctrl_adv);
0680     int (*set_led_id)(struct hnae3_handle *handle,
0681               enum ethtool_phys_id_state status);
0682     void (*get_link_mode)(struct hnae3_handle *handle,
0683                   unsigned long *supported,
0684                   unsigned long *advertising);
0685     int (*add_fd_entry)(struct hnae3_handle *handle,
0686                 struct ethtool_rxnfc *cmd);
0687     int (*del_fd_entry)(struct hnae3_handle *handle,
0688                 struct ethtool_rxnfc *cmd);
0689     int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
0690                    struct ethtool_rxnfc *cmd);
0691     int (*get_fd_rule_info)(struct hnae3_handle *handle,
0692                 struct ethtool_rxnfc *cmd);
0693     int (*get_fd_all_rules)(struct hnae3_handle *handle,
0694                 struct ethtool_rxnfc *cmd, u32 *rule_locs);
0695     void (*enable_fd)(struct hnae3_handle *handle, bool enable);
0696     int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
0697                   u16 flow_id, struct flow_keys *fkeys);
0698     int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
0699                 char *buf, int len);
0700     pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
0701     bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
0702     bool (*ae_dev_resetting)(struct hnae3_handle *handle);
0703     unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
0704     int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
0705     u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
0706     void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
0707     int (*mac_connect_phy)(struct hnae3_handle *handle);
0708     void (*mac_disconnect_phy)(struct hnae3_handle *handle);
0709     int (*get_vf_config)(struct hnae3_handle *handle, int vf,
0710                  struct ifla_vf_info *ivf);
0711     int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
0712                  int link_state);
0713     int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
0714                    bool enable);
0715     int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
0716     int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
0717                int min_tx_rate, int max_tx_rate, bool force);
0718     int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
0719     int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
0720                  u32 len, u8 *data);
0721     bool (*get_cmdq_stat)(struct hnae3_handle *handle);
0722     int (*add_cls_flower)(struct hnae3_handle *handle,
0723                   struct flow_cls_offload *cls_flower, int tc);
0724     int (*del_cls_flower)(struct hnae3_handle *handle,
0725                   struct flow_cls_offload *cls_flower);
0726     bool (*cls_flower_active)(struct hnae3_handle *handle);
0727     int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
0728                       struct ethtool_link_ksettings *cmd);
0729     int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
0730                       const struct ethtool_link_ksettings *cmd);
0731     bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
0732                  struct sk_buff *skb);
0733     void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
0734                 u32 nsec, u32 sec);
0735     int (*get_ts_info)(struct hnae3_handle *handle,
0736                struct ethtool_ts_info *info);
0737     int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
0738                        u32 *status_code);
0739     void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
0740 };
0741 
0742 struct hnae3_dcb_ops {
0743     /* IEEE 802.1Qaz std */
0744     int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
0745     int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
0746     int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
0747     int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
0748 
0749     /* DCBX configuration */
0750     u8   (*getdcbx)(struct hnae3_handle *);
0751     u8   (*setdcbx)(struct hnae3_handle *, u8);
0752 
0753     int (*setup_tc)(struct hnae3_handle *handle,
0754             struct tc_mqprio_qopt_offload *mqprio_qopt);
0755 };
0756 
0757 struct hnae3_ae_algo {
0758     const struct hnae3_ae_ops *ops;
0759     struct list_head node;
0760     const struct pci_device_id *pdev_id_table;
0761 };
0762 
0763 #define HNAE3_INT_NAME_LEN        32
0764 #define HNAE3_ITR_COUNTDOWN_START 100
0765 
0766 #define HNAE3_MAX_TC        8
0767 #define HNAE3_MAX_USER_PRIO 8
0768 struct hnae3_tc_info {
0769     u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
0770     u16 tqp_count[HNAE3_MAX_TC];
0771     u16 tqp_offset[HNAE3_MAX_TC];
0772     u8 max_tc; /* Total number of TCs */
0773     u8 num_tc; /* Total number of enabled TCs */
0774     bool mqprio_active;
0775 };
0776 
0777 struct hnae3_knic_private_info {
0778     struct net_device *netdev; /* Set by KNIC client when init instance */
0779     u16 rss_size;          /* Allocated RSS queues */
0780     u16 req_rss_size;
0781     u16 rx_buf_len;
0782     u16 num_tx_desc;
0783     u16 num_rx_desc;
0784     u32 tx_spare_buf_size;
0785 
0786     struct hnae3_tc_info tc_info;
0787 
0788     u16 num_tqps;         /* total number of TQPs in this handle */
0789     struct hnae3_queue **tqp;  /* array base of all TQPs in this instance */
0790     const struct hnae3_dcb_ops *dcb_ops;
0791 
0792     u16 int_rl_setting;
0793     enum pkt_hash_types rss_type;
0794     void __iomem *io_base;
0795 };
0796 
0797 struct hnae3_roce_private_info {
0798     struct net_device *netdev;
0799     void __iomem *roce_io_base;
0800     void __iomem *roce_mem_base;
0801     int base_vector;
0802     int num_vectors;
0803 
0804     /* The below attributes defined for RoCE client, hnae3 gives
0805      * initial values to them, and RoCE client can modify and use
0806      * them.
0807      */
0808     unsigned long reset_state;
0809     unsigned long instance_state;
0810     unsigned long state;
0811 };
0812 
0813 #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
0814 #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
0815 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK    BIT(2)
0816 #define HNAE3_SUPPORT_VF          BIT(3)
0817 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK  BIT(4)
0818 
0819 #define HNAE3_USER_UPE      BIT(0)  /* unicast promisc enabled by user */
0820 #define HNAE3_USER_MPE      BIT(1)  /* mulitcast promisc enabled by user */
0821 #define HNAE3_BPE       BIT(2)  /* broadcast promisc enable */
0822 #define HNAE3_OVERFLOW_UPE  BIT(3)  /* unicast mac vlan overflow */
0823 #define HNAE3_OVERFLOW_MPE  BIT(4)  /* multicast mac vlan overflow */
0824 #define HNAE3_UPE       (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
0825 #define HNAE3_MPE       (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
0826 
0827 enum hnae3_pflag {
0828     HNAE3_PFLAG_LIMIT_PROMISC,
0829     HNAE3_PFLAG_MAX
0830 };
0831 
0832 struct hnae3_handle {
0833     struct hnae3_client *client;
0834     struct pci_dev *pdev;
0835     void *priv;
0836     struct hnae3_ae_algo *ae_algo;  /* the class who provides this handle */
0837     u64 flags; /* Indicate the capabilities for this handle */
0838 
0839     union {
0840         struct net_device *netdev; /* first member */
0841         struct hnae3_knic_private_info kinfo;
0842         struct hnae3_roce_private_info rinfo;
0843     };
0844 
0845     u32 numa_node_mask; /* for multi-chip support */
0846 
0847     enum hnae3_port_base_vlan_state port_base_vlan_state;
0848 
0849     u8 netdev_flags;
0850     struct dentry *hnae3_dbgfs;
0851     /* protects concurrent contention between debugfs commands */
0852     struct mutex dbgfs_lock;
0853     char **dbgfs_buf;
0854 
0855     /* Network interface message level enabled bits */
0856     u32 msg_enable;
0857 
0858     unsigned long supported_pflags;
0859     unsigned long priv_flags;
0860 };
0861 
0862 #define hnae3_set_field(origin, mask, shift, val) \
0863     do { \
0864         (origin) &= (~(mask)); \
0865         (origin) |= ((val) << (shift)) & (mask); \
0866     } while (0)
0867 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
0868 
0869 #define hnae3_set_bit(origin, shift, val) \
0870     hnae3_set_field(origin, 0x1 << (shift), shift, val)
0871 #define hnae3_get_bit(origin, shift) \
0872     hnae3_get_field(origin, 0x1 << (shift), shift)
0873 
0874 #define HNAE3_FORMAT_MAC_ADDR_LEN   18
0875 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0  0
0876 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4  4
0877 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5  5
0878 
0879 static inline void hnae3_format_mac_addr(char *format_mac_addr,
0880                      const u8 *mac_addr)
0881 {
0882     snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x",
0883          mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],
0884          mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],
0885          mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);
0886 }
0887 
0888 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
0889 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
0890 
0891 void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
0892 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
0893 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
0894 
0895 void hnae3_unregister_client(struct hnae3_client *client);
0896 int hnae3_register_client(struct hnae3_client *client);
0897 
0898 void hnae3_set_client_init_flag(struct hnae3_client *client,
0899                 struct hnae3_ae_dev *ae_dev,
0900                 unsigned int inited);
0901 #endif
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