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0002
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0004 #ifndef __HCLGE_MBX_H
0005 #define __HCLGE_MBX_H
0006 #include <linux/init.h>
0007 #include <linux/mutex.h>
0008 #include <linux/types.h>
0009
0010 enum HCLGE_MBX_OPCODE {
0011 HCLGE_MBX_RESET = 0x01,
0012 HCLGE_MBX_ASSERTING_RESET,
0013 HCLGE_MBX_SET_UNICAST,
0014 HCLGE_MBX_SET_MULTICAST,
0015 HCLGE_MBX_SET_VLAN,
0016 HCLGE_MBX_MAP_RING_TO_VECTOR,
0017 HCLGE_MBX_UNMAP_RING_TO_VECTOR,
0018 HCLGE_MBX_SET_PROMISC_MODE,
0019 HCLGE_MBX_SET_MACVLAN,
0020 HCLGE_MBX_API_NEGOTIATE,
0021 HCLGE_MBX_GET_QINFO,
0022 HCLGE_MBX_GET_QDEPTH,
0023 HCLGE_MBX_GET_BASIC_INFO,
0024 HCLGE_MBX_GET_RETA,
0025 HCLGE_MBX_GET_RSS_KEY,
0026 HCLGE_MBX_GET_MAC_ADDR,
0027 HCLGE_MBX_PF_VF_RESP,
0028 HCLGE_MBX_GET_BDNUM,
0029 HCLGE_MBX_GET_BUFSIZE,
0030 HCLGE_MBX_GET_STREAMID,
0031 HCLGE_MBX_SET_AESTART,
0032 HCLGE_MBX_SET_TSOSTATS,
0033 HCLGE_MBX_LINK_STAT_CHANGE,
0034 HCLGE_MBX_GET_BASE_CONFIG,
0035 HCLGE_MBX_BIND_FUNC_QUEUE,
0036 HCLGE_MBX_GET_LINK_STATUS,
0037 HCLGE_MBX_QUEUE_RESET,
0038 HCLGE_MBX_KEEP_ALIVE,
0039 HCLGE_MBX_SET_ALIVE,
0040 HCLGE_MBX_SET_MTU,
0041 HCLGE_MBX_GET_QID_IN_PF,
0042 HCLGE_MBX_LINK_STAT_MODE,
0043 HCLGE_MBX_GET_LINK_MODE,
0044 HCLGE_MBX_PUSH_VLAN_INFO,
0045 HCLGE_MBX_GET_MEDIA_TYPE,
0046 HCLGE_MBX_PUSH_PROMISC_INFO,
0047 HCLGE_MBX_VF_UNINIT,
0048 HCLGE_MBX_HANDLE_VF_TBL,
0049 HCLGE_MBX_GET_RING_VECTOR_MAP,
0050
0051 HCLGE_MBX_GET_VF_FLR_STATUS = 200,
0052 HCLGE_MBX_PUSH_LINK_STATUS,
0053 HCLGE_MBX_NCSI_ERROR,
0054 };
0055
0056
0057 enum hclge_mbx_mac_vlan_subcode {
0058 HCLGE_MBX_MAC_VLAN_UC_MODIFY = 0,
0059 HCLGE_MBX_MAC_VLAN_UC_ADD,
0060 HCLGE_MBX_MAC_VLAN_UC_REMOVE,
0061 HCLGE_MBX_MAC_VLAN_MC_MODIFY,
0062 HCLGE_MBX_MAC_VLAN_MC_ADD,
0063 HCLGE_MBX_MAC_VLAN_MC_REMOVE,
0064 };
0065
0066
0067 enum hclge_mbx_vlan_cfg_subcode {
0068 HCLGE_MBX_VLAN_FILTER = 0,
0069 HCLGE_MBX_VLAN_TX_OFF_CFG,
0070 HCLGE_MBX_VLAN_RX_OFF_CFG,
0071 HCLGE_MBX_PORT_BASE_VLAN_CFG,
0072 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE,
0073 HCLGE_MBX_ENABLE_VLAN_FILTER,
0074 };
0075
0076 enum hclge_mbx_tbl_cfg_subcode {
0077 HCLGE_MBX_VPORT_LIST_CLEAR,
0078 };
0079
0080 #define HCLGE_MBX_MAX_MSG_SIZE 14
0081 #define HCLGE_MBX_MAX_RESP_DATA_SIZE 8U
0082 #define HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM 4
0083
0084 #define HCLGE_RESET_SCHED_TIMEOUT (3 * HZ)
0085 #define HCLGE_MBX_SCHED_TIMEOUT (HZ / 2)
0086
0087 struct hclge_ring_chain_param {
0088 u8 ring_type;
0089 u8 tqp_index;
0090 u8 int_gl_index;
0091 };
0092
0093 struct hclge_basic_info {
0094 u8 hw_tc_map;
0095 u8 rsv;
0096 __le16 mbx_api_version;
0097 __le32 pf_caps;
0098 };
0099
0100 struct hclgevf_mbx_resp_status {
0101 struct mutex mbx_mutex;
0102 u32 origin_mbx_msg;
0103 bool received_resp;
0104 int resp_status;
0105 u16 match_id;
0106 u8 additional_info[HCLGE_MBX_MAX_RESP_DATA_SIZE];
0107 };
0108
0109 struct hclge_respond_to_vf_msg {
0110 int status;
0111 u8 data[HCLGE_MBX_MAX_RESP_DATA_SIZE];
0112 u16 len;
0113 };
0114
0115 struct hclge_vf_to_pf_msg {
0116 u8 code;
0117 union {
0118 struct {
0119 u8 subcode;
0120 u8 data[HCLGE_MBX_MAX_MSG_SIZE];
0121 };
0122 struct {
0123 u8 en_bc;
0124 u8 en_uc;
0125 u8 en_mc;
0126 u8 en_limit_promisc;
0127 };
0128 struct {
0129 u8 vector_id;
0130 u8 ring_num;
0131 struct hclge_ring_chain_param
0132 param[HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM];
0133 };
0134 };
0135 };
0136
0137 struct hclge_pf_to_vf_msg {
0138 __le16 code;
0139 union {
0140
0141 struct {
0142 __le16 vf_mbx_msg_code;
0143 __le16 vf_mbx_msg_subcode;
0144 __le16 resp_status;
0145 u8 resp_data[HCLGE_MBX_MAX_RESP_DATA_SIZE];
0146 };
0147
0148 struct {
0149 u8 msg_data[HCLGE_MBX_MAX_MSG_SIZE];
0150 };
0151 };
0152 };
0153
0154 struct hclge_mbx_vf_to_pf_cmd {
0155 u8 rsv;
0156 u8 mbx_src_vfid;
0157 u8 mbx_need_resp;
0158 u8 rsv1[1];
0159 u8 msg_len;
0160 u8 rsv2;
0161 __le16 match_id;
0162 struct hclge_vf_to_pf_msg msg;
0163 };
0164
0165 #define HCLGE_MBX_NEED_RESP_B 0
0166
0167 struct hclge_mbx_pf_to_vf_cmd {
0168 u8 dest_vfid;
0169 u8 rsv[3];
0170 u8 msg_len;
0171 u8 rsv1;
0172 __le16 match_id;
0173 struct hclge_pf_to_vf_msg msg;
0174 };
0175
0176 struct hclge_vf_rst_cmd {
0177 u8 dest_vfid;
0178 u8 vf_rst;
0179 u8 rsv[22];
0180 };
0181
0182 #pragma pack(1)
0183 struct hclge_mbx_link_status {
0184 __le16 link_status;
0185 __le32 speed;
0186 __le16 duplex;
0187 u8 flag;
0188 };
0189
0190 struct hclge_mbx_link_mode {
0191 __le16 idx;
0192 __le64 link_mode;
0193 };
0194
0195 struct hclge_mbx_port_base_vlan {
0196 __le16 state;
0197 __le16 vlan_proto;
0198 __le16 qos;
0199 __le16 vlan_tag;
0200 };
0201
0202 struct hclge_mbx_vf_queue_info {
0203 __le16 num_tqps;
0204 __le16 rss_size;
0205 __le16 rx_buf_len;
0206 };
0207
0208 struct hclge_mbx_vf_queue_depth {
0209 __le16 num_tx_desc;
0210 __le16 num_rx_desc;
0211 };
0212
0213 struct hclge_mbx_vlan_filter {
0214 u8 is_kill;
0215 __le16 vlan_id;
0216 __le16 proto;
0217 };
0218
0219 struct hclge_mbx_mtu_info {
0220 __le32 mtu;
0221 };
0222
0223 #pragma pack()
0224
0225
0226 struct hclgevf_mbx_arq_ring {
0227 #define HCLGE_MBX_MAX_ARQ_MSG_SIZE 8
0228 #define HCLGE_MBX_MAX_ARQ_MSG_NUM 1024
0229 struct hclgevf_dev *hdev;
0230 u32 head;
0231 u32 tail;
0232 atomic_t count;
0233 __le16 msg_q[HCLGE_MBX_MAX_ARQ_MSG_NUM][HCLGE_MBX_MAX_ARQ_MSG_SIZE];
0234 };
0235
0236 #define hclge_mbx_ring_ptr_move_crq(crq) \
0237 (crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)
0238 #define hclge_mbx_tail_ptr_move_arq(arq) \
0239 (arq.tail = (arq.tail + 1) % HCLGE_MBX_MAX_ARQ_MSG_NUM)
0240 #define hclge_mbx_head_ptr_move_arq(arq) \
0241 (arq.head = (arq.head + 1) % HCLGE_MBX_MAX_ARQ_MSG_NUM)
0242
0243
0244 #define HCLGE_MBX_PUSH_LINK_STATUS_EN BIT(0)
0245 #endif