hisilicon/hns/hns_dsaf_ppe.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2014-2015 Hisilicon Limited.
0004  */
0005
0006 #ifndef _HNS_DSAF_PPE_H
0007 #define _HNS_DSAF_PPE_H
0008
0009 #include <linux/platform_device.h>
0010
0011 #include "hns_dsaf_main.h"
0012 #include "hns_dsaf_mac.h"
0013 #include "hns_dsaf_rcb.h"
0014
0015 #define HNS_PPE_SERVICE_NW_ENGINE_NUM DSAF_COMM_CHN
0016 #define HNS_PPE_DEBUG_NW_ENGINE_NUM 1
0017 #define HNS_PPE_COM_NUM DSAF_COMM_DEV_NUM
0018
0019 #define PPE_COMMON_REG_OFFSET 0x70000
0020 #define PPE_REG_OFFSET 0x10000
0021
0022 #define ETH_PPE_DUMP_NUM 576
0023 #define ETH_PPE_STATIC_NUM 12
0024
0025 #define HNS_PPEV2_RSS_IND_TBL_SIZE 256
0026 #define HNS_PPEV2_RSS_KEY_SIZE 40 /* in bytes or 320 bits */
0027 #define HNS_PPEV2_RSS_KEY_NUM (HNS_PPEV2_RSS_KEY_SIZE / sizeof(u32))
0028
0029 #define HNS_PPEV2_MAX_FRAME_LEN 0X980
0030
0031 enum ppe_qid_mode {
0032     PPE_QID_MODE0 = 0, /* fixed queue id mode */
0033     PPE_QID_MODE1,     /* switch:128VM non switch:6Port/4VM/4TC */
0034     PPE_QID_MODE2,     /* switch:32VM/4TC non switch:6Port/16VM */
0035     PPE_QID_MODE3,     /* switch:4TC/8RSS non switch:2Port/64VM */
0036     PPE_QID_MODE4,     /* switch:8VM/16RSS non switch:2Port/16VM/4TC */
0037     PPE_QID_MODE5,     /* switch:16VM/8TC non switch:6Port/16RSS */
0038     PPE_QID_MODE6,     /* switch:32VM/4RSS non switch:6Port/2VM/8TC */
0039     PPE_QID_MODE7,     /* switch:32RSS non switch:2Port/8VM/8TC */
0040     PPE_QID_MODE8,     /* switch:6VM/4TC/4RSS non switch:2Port/16VM/4RSS */
0041     PPE_QID_MODE9,     /* non switch:2Port/32VM/2RSS */
0042     PPE_QID_MODE10,    /* non switch:2Port/32RSS */
0043     PPE_QID_MODE11,    /* non switch:2Port/4TC/16RSS */
0044 };
0045
0046 enum ppe_port_mode {
0047     PPE_MODE_GE = 0,
0048     PPE_MODE_XGE,
0049 };
0050
0051 enum ppe_common_mode {
0052     PPE_COMMON_MODE_DEBUG = 0,
0053     PPE_COMMON_MODE_SERVICE,
0054     PPE_COMMON_MODE_MAX
0055 };
0056
0057 struct hns_ppe_hw_stats {
0058     u64 rx_pkts_from_sw;
0059     u64 rx_pkts;
0060     u64 rx_drop_no_bd;
0061     u64 rx_alloc_buf_fail;
0062     u64 rx_alloc_buf_wait;
0063     u64 rx_drop_no_buf;
0064     u64 rx_err_fifo_full;
0065     u64 tx_bd_form_rcb;
0066     u64 tx_pkts_from_rcb;
0067     u64 tx_pkts;
0068     u64 tx_err_fifo_empty;
0069     u64 tx_err_checksum;
0070 };
0071
0072 struct hns_ppe_cb {
0073     struct device *dev;
0074     struct hns_ppe_cb *next;    /* pointer to next ppe device */
0075     struct ppe_common_cb *ppe_common_cb; /* belong to */
0076     struct hns_ppe_hw_stats hw_stats;
0077
0078     u8 index;   /* index in a ppe common device */
0079     u8 __iomem *io_base;
0080     int virq;
0081     u32 rss_indir_table[HNS_PPEV2_RSS_IND_TBL_SIZE]; /*shadow indir tab */
0082     u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]; /* rss hash key */
0083 };
0084
0085 struct ppe_common_cb {
0086     struct device *dev;
0087     struct dsaf_device *dsaf_dev;
0088     u8 __iomem *io_base;
0089
0090     enum ppe_common_mode ppe_mode;
0091
0092     u8 comm_index;   /*ppe_common index*/
0093
0094     u32 ppe_num;
0095     struct hns_ppe_cb ppe_cb[];
0096
0097 };
0098
0099 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb);
0100 int hns_ppe_init(struct dsaf_device *dsaf_dev);
0101
0102 void hns_ppe_uninit(struct dsaf_device *dsaf_dev);
0103
0104 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index);
0105
0106 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb);
0107
0108 int hns_ppe_get_sset_count(int stringset);
0109 int hns_ppe_get_regs_count(void);
0110 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data);
0111
0112 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data);
0113 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data);
0114 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value);
0115 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
0116              const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]);
0117 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
0118                  const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE]);
0119 #endif /* _HNS_DSAF_PPE_H */