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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014-2015 Hisilicon Limited.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/netdevice.h>
0010 #include <linux/etherdevice.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_platform.h>
0015 
0016 #include "hns_dsaf_ppe.h"
0017 
0018 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
0019 {
0020     dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
0021 }
0022 
0023 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
0024              const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
0025 {
0026     u32 key_item;
0027 
0028     for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
0029         dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
0030                    rss_key[key_item]);
0031 }
0032 
0033 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
0034                  const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
0035 {
0036     int i;
0037     int reg_value;
0038 
0039     for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
0040         reg_value = dsaf_read_dev(ppe_cb,
0041                       PPEV2_INDRECTION_TBL_REG + i * 0x4);
0042 
0043         dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
0044                    PPEV2_CFG_RSS_TBL_4N0_S,
0045                    rss_tab[i * 4 + 0] & 0x1F);
0046         dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
0047                    PPEV2_CFG_RSS_TBL_4N1_S,
0048                 rss_tab[i * 4 + 1] & 0x1F);
0049         dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
0050                    PPEV2_CFG_RSS_TBL_4N2_S,
0051                 rss_tab[i * 4 + 2] & 0x1F);
0052         dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
0053                    PPEV2_CFG_RSS_TBL_4N3_S,
0054                 rss_tab[i * 4 + 3] & 0x1F);
0055         dsaf_write_dev(
0056             ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
0057     }
0058 }
0059 
0060 static u8 __iomem *
0061 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
0062 {
0063     return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
0064 }
0065 
0066 /**
0067  * hns_ppe_common_get_cfg - get ppe common config
0068  * @dsaf_dev: dasf device
0069  * @comm_index: common index
0070  * return 0 - success , negative --fail
0071  */
0072 static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
0073 {
0074     struct ppe_common_cb *ppe_common;
0075     int ppe_num;
0076 
0077     if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
0078         ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
0079     else
0080         ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
0081 
0082     ppe_common = devm_kzalloc(dsaf_dev->dev,
0083                   struct_size(ppe_common, ppe_cb, ppe_num),
0084                   GFP_KERNEL);
0085     if (!ppe_common)
0086         return -ENOMEM;
0087 
0088     ppe_common->ppe_num = ppe_num;
0089     ppe_common->dsaf_dev = dsaf_dev;
0090     ppe_common->comm_index = comm_index;
0091     if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
0092         ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
0093     else
0094         ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
0095     ppe_common->dev = dsaf_dev->dev;
0096 
0097     ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
0098 
0099     dsaf_dev->ppe_common[comm_index] = ppe_common;
0100 
0101     return 0;
0102 }
0103 
0104 static void
0105 hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
0106 {
0107     dsaf_dev->ppe_common[comm_index] = NULL;
0108 }
0109 
0110 static u8 __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
0111                       int ppe_idx)
0112 {
0113     return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
0114 }
0115 
0116 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
0117 {
0118     u32 i;
0119     struct hns_ppe_cb *ppe_cb;
0120     u32 ppe_num = ppe_common->ppe_num;
0121 
0122     for (i = 0; i < ppe_num; i++) {
0123         ppe_cb = &ppe_common->ppe_cb[i];
0124         ppe_cb->dev = ppe_common->dev;
0125         ppe_cb->next = NULL;
0126         ppe_cb->ppe_common_cb = ppe_common;
0127         ppe_cb->index = i;
0128         ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
0129         ppe_cb->virq = 0;
0130     }
0131 }
0132 
0133 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
0134 {
0135     dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
0136              PPE_CNT_CLR_CE_B, 1);
0137 }
0138 
0139 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
0140 {
0141     dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
0142 }
0143 
0144 /**
0145  * hns_ppe_checksum_hw - set ppe checksum caculate
0146  * @ppe_cb: ppe device
0147  * @value: value
0148  */
0149 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
0150 {
0151     dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
0152                0xfffffff, 0, value);
0153 }
0154 
0155 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
0156                  enum ppe_qid_mode qid_mdoe)
0157 {
0158     dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
0159                PPE_CFG_QID_MODE_CF_QID_MODE_M,
0160                PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
0161 }
0162 
0163 /**
0164  * hns_ppe_set_qid - set ppe qid
0165  * @ppe_common: ppe common device
0166  * @qid: queue id
0167  */
0168 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
0169 {
0170     u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
0171 
0172     if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
0173                 PPE_CFG_QID_MODE_DEF_QID_S)) {
0174         dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
0175                    PPE_CFG_QID_MODE_DEF_QID_S, qid);
0176         dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
0177     }
0178 }
0179 
0180 /**
0181  * hns_ppe_set_port_mode - set port mode
0182  * @ppe_cb: ppe device
0183  * @mode: port mode
0184  */
0185 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
0186                   enum ppe_port_mode mode)
0187 {
0188     dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
0189 }
0190 
0191 /**
0192  * hns_ppe_common_init_hw - init ppe common device
0193  * @ppe_common: ppe common device
0194  *
0195  * Return 0 on success, negative on failure
0196  */
0197 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
0198 {
0199     enum ppe_qid_mode qid_mode;
0200     struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
0201     enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
0202 
0203     dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0);
0204     msleep(100);
0205     dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1);
0206     msleep(100);
0207 
0208     if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
0209         switch (dsaf_mode) {
0210         case DSAF_MODE_ENABLE_FIX:
0211         case DSAF_MODE_DISABLE_FIX:
0212             qid_mode = PPE_QID_MODE0;
0213             hns_ppe_set_qid(ppe_common, 0);
0214             break;
0215         case DSAF_MODE_ENABLE_0VM:
0216         case DSAF_MODE_DISABLE_2PORT_64VM:
0217             qid_mode = PPE_QID_MODE3;
0218             break;
0219         case DSAF_MODE_ENABLE_8VM:
0220         case DSAF_MODE_DISABLE_2PORT_16VM:
0221             qid_mode = PPE_QID_MODE4;
0222             break;
0223         case DSAF_MODE_ENABLE_16VM:
0224         case DSAF_MODE_DISABLE_6PORT_0VM:
0225             qid_mode = PPE_QID_MODE5;
0226             break;
0227         case DSAF_MODE_ENABLE_32VM:
0228         case DSAF_MODE_DISABLE_6PORT_16VM:
0229             qid_mode = PPE_QID_MODE2;
0230             break;
0231         case DSAF_MODE_ENABLE_128VM:
0232         case DSAF_MODE_DISABLE_6PORT_4VM:
0233             qid_mode = PPE_QID_MODE1;
0234             break;
0235         case DSAF_MODE_DISABLE_2PORT_8VM:
0236             qid_mode = PPE_QID_MODE7;
0237             break;
0238         case DSAF_MODE_DISABLE_6PORT_2VM:
0239             qid_mode = PPE_QID_MODE6;
0240             break;
0241         default:
0242             dev_err(ppe_common->dev,
0243                 "get ppe queue mode failed! dsaf_mode=%d\n",
0244                 dsaf_mode);
0245             return -EINVAL;
0246         }
0247         hns_ppe_set_qid_mode(ppe_common, qid_mode);
0248     }
0249 
0250     dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
0251              PPE_COMMON_CNT_CLR_CE_B, 1);
0252 
0253     return 0;
0254 }
0255 
0256 /*clr ppe exception irq*/
0257 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
0258 {
0259     u32 clr_vlue = 0xfffffffful;
0260     u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
0261     u32 vld_msk = 0;
0262 
0263     /*only care bit 0,1,7*/
0264     dsaf_set_bit(vld_msk, 0, 1);
0265     dsaf_set_bit(vld_msk, 1, 1);
0266     dsaf_set_bit(vld_msk, 7, 1);
0267 
0268     /*clr sts**/
0269     dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
0270 
0271     /*for some reserved bits, so set 0**/
0272     dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
0273 }
0274 
0275 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb)
0276 {
0277     int wait_cnt;
0278     u32 val;
0279 
0280     wait_cnt = 0;
0281     while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
0282         val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU;
0283         if (!val)
0284             break;
0285 
0286         usleep_range(100, 200);
0287     }
0288 
0289     if (wait_cnt >= HNS_MAX_WAIT_CNT) {
0290         dev_err(ppe_cb->dev, "hns ppe tx fifo clean wait timeout, still has %u pkt.\n",
0291             val);
0292         return -EBUSY;
0293     }
0294 
0295     return 0;
0296 }
0297 
0298 /**
0299  * hns_ppe_init_hw - init ppe
0300  * @ppe_cb: ppe device
0301  */
0302 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
0303 {
0304     struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
0305     u32 port = ppe_cb->index;
0306     struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
0307     int i;
0308 
0309     /* get default RSS key */
0310     netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
0311 
0312     dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
0313     mdelay(10);
0314     dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);
0315 
0316     /* clr and msk except irq*/
0317     hns_ppe_exc_irq_en(ppe_cb, 0);
0318 
0319     if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
0320         hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
0321         dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
0322     } else {
0323         hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
0324     }
0325 
0326     hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
0327     hns_ppe_cnt_clr_ce(ppe_cb);
0328 
0329     if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
0330         hns_ppe_set_vlan_strip(ppe_cb, 0);
0331 
0332         dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
0333                    HNS_PPEV2_MAX_FRAME_LEN);
0334 
0335         /* set default RSS key in h/w */
0336         hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
0337 
0338         /* Set default indrection table in h/w */
0339         for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
0340             ppe_cb->rss_indir_table[i] = i;
0341         hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
0342     }
0343 }
0344 
0345 /**
0346  * hns_ppe_uninit_hw - uninit ppe
0347  * @ppe_cb: ppe device
0348  */
0349 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
0350 {
0351     u32 port;
0352 
0353     if (ppe_cb->ppe_common_cb) {
0354         struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev;
0355 
0356         port = ppe_cb->index;
0357         dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
0358     }
0359 }
0360 
0361 static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
0362 {
0363     u32 i;
0364 
0365     for (i = 0; i < ppe_common->ppe_num; i++) {
0366         if (ppe_common->dsaf_dev->mac_cb[i])
0367             hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
0368         memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
0369     }
0370 }
0371 
0372 void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
0373 {
0374     u32 i;
0375 
0376     for (i = 0; i < HNS_PPE_COM_NUM; i++) {
0377         if (dsaf_dev->ppe_common[i])
0378             hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
0379         hns_rcb_common_free_cfg(dsaf_dev, i);
0380         hns_ppe_common_free_cfg(dsaf_dev, i);
0381     }
0382 }
0383 
0384 /**
0385  * hns_ppe_reset_common - reinit ppe/rcb hw
0386  * @dsaf_dev: dasf device
0387  * @ppe_common_index: the index
0388  * return void
0389  */
0390 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
0391 {
0392     u32 i;
0393     int ret;
0394     struct ppe_common_cb *ppe_common;
0395 
0396     ppe_common = dsaf_dev->ppe_common[ppe_common_index];
0397     ret = hns_ppe_common_init_hw(ppe_common);
0398     if (ret)
0399         return;
0400 
0401     for (i = 0; i < ppe_common->ppe_num; i++) {
0402         /* We only need to initiate ppe when the port exists */
0403         if (dsaf_dev->mac_cb[i])
0404             hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
0405     }
0406 
0407     ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
0408     if (ret)
0409         return;
0410 
0411     hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
0412 }
0413 
0414 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
0415 {
0416     struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
0417 
0418     hw_stats->rx_pkts_from_sw
0419         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
0420     hw_stats->rx_pkts
0421         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
0422     hw_stats->rx_drop_no_bd
0423         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
0424     hw_stats->rx_alloc_buf_fail
0425         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
0426     hw_stats->rx_alloc_buf_wait
0427         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
0428     hw_stats->rx_drop_no_buf
0429         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
0430     hw_stats->rx_err_fifo_full
0431         += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
0432 
0433     hw_stats->tx_bd_form_rcb
0434         += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
0435     hw_stats->tx_pkts_from_rcb
0436         += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
0437     hw_stats->tx_pkts
0438         += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
0439     hw_stats->tx_err_fifo_empty
0440         += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
0441     hw_stats->tx_err_checksum
0442         += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
0443 }
0444 
0445 int hns_ppe_get_sset_count(int stringset)
0446 {
0447     if (stringset == ETH_SS_STATS)
0448         return ETH_PPE_STATIC_NUM;
0449     return 0;
0450 }
0451 
0452 int hns_ppe_get_regs_count(void)
0453 {
0454     return ETH_PPE_DUMP_NUM;
0455 }
0456 
0457 /**
0458  * hns_ppe_get_strings - get ppe srting
0459  * @ppe_cb: ppe device
0460  * @stringset: string set type
0461  * @data: output string
0462  */
0463 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
0464 {
0465     int index = ppe_cb->index;
0466     u8 *buff = data;
0467 
0468     ethtool_sprintf(&buff, "ppe%d_rx_sw_pkt", index);
0469     ethtool_sprintf(&buff, "ppe%d_rx_pkt_ok", index);
0470     ethtool_sprintf(&buff, "ppe%d_rx_drop_pkt_no_bd", index);
0471     ethtool_sprintf(&buff, "ppe%d_rx_alloc_buf_fail", index);
0472     ethtool_sprintf(&buff, "ppe%d_rx_alloc_buf_wait", index);
0473     ethtool_sprintf(&buff, "ppe%d_rx_pkt_drop_no_buf", index);
0474     ethtool_sprintf(&buff, "ppe%d_rx_pkt_err_fifo_full", index);
0475 
0476     ethtool_sprintf(&buff, "ppe%d_tx_bd", index);
0477     ethtool_sprintf(&buff, "ppe%d_tx_pkt", index);
0478     ethtool_sprintf(&buff, "ppe%d_tx_pkt_ok", index);
0479     ethtool_sprintf(&buff, "ppe%d_tx_pkt_err_fifo_empty", index);
0480     ethtool_sprintf(&buff, "ppe%d_tx_pkt_err_csum_fail", index);
0481 }
0482 
0483 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
0484 {
0485     u64 *regs_buff = data;
0486     struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
0487 
0488     regs_buff[0] = hw_stats->rx_pkts_from_sw;
0489     regs_buff[1] = hw_stats->rx_pkts;
0490     regs_buff[2] = hw_stats->rx_drop_no_bd;
0491     regs_buff[3] = hw_stats->rx_alloc_buf_fail;
0492     regs_buff[4] = hw_stats->rx_alloc_buf_wait;
0493     regs_buff[5] = hw_stats->rx_drop_no_buf;
0494     regs_buff[6] = hw_stats->rx_err_fifo_full;
0495 
0496     regs_buff[7] = hw_stats->tx_bd_form_rcb;
0497     regs_buff[8] = hw_stats->tx_pkts_from_rcb;
0498     regs_buff[9] = hw_stats->tx_pkts;
0499     regs_buff[10] = hw_stats->tx_err_fifo_empty;
0500     regs_buff[11] = hw_stats->tx_err_checksum;
0501 }
0502 
0503 /**
0504  * hns_ppe_init - init ppe device
0505  * @dsaf_dev: dasf device
0506  * return 0 - success , negative --fail
0507  */
0508 int hns_ppe_init(struct dsaf_device *dsaf_dev)
0509 {
0510     int ret;
0511     int i;
0512 
0513     for (i = 0; i < HNS_PPE_COM_NUM; i++) {
0514         ret = hns_ppe_common_get_cfg(dsaf_dev, i);
0515         if (ret)
0516             goto get_cfg_fail;
0517 
0518         ret = hns_rcb_common_get_cfg(dsaf_dev, i);
0519         if (ret)
0520             goto get_cfg_fail;
0521 
0522         hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
0523 
0524         ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
0525         if (ret)
0526             goto get_cfg_fail;
0527     }
0528 
0529     for (i = 0; i < HNS_PPE_COM_NUM; i++)
0530         hns_ppe_reset_common(dsaf_dev, i);
0531 
0532     return 0;
0533 
0534 get_cfg_fail:
0535     for (i = 0; i < HNS_PPE_COM_NUM; i++) {
0536         hns_rcb_common_free_cfg(dsaf_dev, i);
0537         hns_ppe_common_free_cfg(dsaf_dev, i);
0538     }
0539 
0540     return ret;
0541 }
0542 
0543 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
0544 {
0545     struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
0546     u32 *regs = data;
0547     u32 i;
0548     u32 offset;
0549 
0550     /* ppe common registers */
0551     regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
0552     regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
0553     regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
0554     regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
0555     regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
0556 
0557     for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
0558         offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
0559         regs[5 + i] = dsaf_read_dev(ppe_common, offset);
0560         offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
0561         regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
0562                 = dsaf_read_dev(ppe_common, offset);
0563         offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
0564         regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
0565                 = dsaf_read_dev(ppe_common, offset);
0566         offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
0567         regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
0568                 = dsaf_read_dev(ppe_common, offset);
0569     }
0570 
0571     /* mark end of ppe regs */
0572     for (i = 521; i < 524; i++)
0573         regs[i] = 0xeeeeeeee;
0574 
0575     /* ppe channel registers */
0576     regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
0577     regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
0578     regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
0579     regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
0580     regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
0581     regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
0582     regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
0583     regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
0584 
0585     regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
0586     regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
0587     regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
0588     regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
0589     regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
0590     regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
0591     regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
0592 
0593     regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
0594     regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
0595     regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
0596     regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
0597 
0598     regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
0599     regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
0600 
0601     /* ppe static */
0602     regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
0603     regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
0604     regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
0605     regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
0606     regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
0607     regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
0608     regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
0609     regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
0610     regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
0611     regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
0612     regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
0613     regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
0614 
0615     regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
0616     regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
0617     regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
0618     regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
0619     regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
0620     regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
0621     regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
0622     regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
0623     regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
0624     regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
0625     regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
0626     regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
0627     regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
0628     regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
0629 
0630     /* mark end of ppe regs */
0631     for (i = 572; i < 576; i++)
0632         regs[i] = 0xeeeeeeee;
0633 }
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