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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2014-2015 Hisilicon Limited.
0004  */
0005 
0006 #ifndef __HNS_DSAF_MAIN_H
0007 #define __HNS_DSAF_MAIN_H
0008 #include "hnae.h"
0009 
0010 #include "hns_dsaf_reg.h"
0011 #include "hns_dsaf_mac.h"
0012 
0013 struct hns_mac_cb;
0014 
0015 #define DSAF_DRV_NAME "hns_dsaf"
0016 #define DSAF_MOD_VERSION "v1.0"
0017 #define DSAF_DEVICE_NAME "dsaf"
0018 
0019 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000
0020 
0021 #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/
0022 
0023 #define DSAF_MAX_CHIP_NUM 2  /*max 2 chips */
0024 
0025 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22
0026 
0027 #define HNS_DSAF_MAX_DESC_CNT 1024
0028 #define HNS_DSAF_MIN_DESC_CNT 16
0029 
0030 #define DSAF_INVALID_ENTRY_IDX 0xffff
0031 
0032 #define DSAF_CFG_READ_CNT   30
0033 
0034 #define DSAF_DUMP_REGS_NUM 504
0035 #define DSAF_STATIC_NUM 28
0036 #define DSAF_V2_STATIC_NUM  44
0037 #define DSAF_PRIO_NR    8
0038 #define DSAF_REG_PER_ZONE   3
0039 
0040 #define DSAF_ROCE_CREDIT_CHN    8
0041 #define DSAF_ROCE_CHAN_MODE 3
0042 
0043 #define HNS_MAX_WAIT_CNT 10000
0044 
0045 enum dsaf_roce_port_mode {
0046     DSAF_ROCE_6PORT_MODE,
0047     DSAF_ROCE_4PORT_MODE,
0048     DSAF_ROCE_2PORT_MODE,
0049     DSAF_ROCE_CHAN_MODE_NUM,
0050 };
0051 
0052 enum dsaf_roce_port_num {
0053     DSAF_ROCE_PORT_0,
0054     DSAF_ROCE_PORT_1,
0055     DSAF_ROCE_PORT_2,
0056     DSAF_ROCE_PORT_3,
0057     DSAF_ROCE_PORT_4,
0058     DSAF_ROCE_PORT_5,
0059 };
0060 
0061 enum dsaf_roce_qos_sl {
0062     DSAF_ROCE_SL_0,
0063     DSAF_ROCE_SL_1,
0064     DSAF_ROCE_SL_2,
0065     DSAF_ROCE_SL_3,
0066 };
0067 
0068 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
0069 #define HNS_DSAF_IS_DEBUG(dev) ((dev)->dsaf_mode == DSAF_MODE_DISABLE_SP)
0070 
0071 enum hal_dsaf_mode {
0072     HRD_DSAF_NO_DSAF_MODE   = 0x0,
0073     HRD_DSAF_MODE       = 0x1,
0074 };
0075 
0076 enum hal_dsaf_tc_mode {
0077     HRD_DSAF_4TC_MODE       = 0X0,
0078     HRD_DSAF_8TC_MODE       = 0X1,
0079 };
0080 
0081 struct dsaf_vm_def_vlan {
0082     u32 vm_def_vlan_id;
0083     u32 vm_def_vlan_cfi;
0084     u32 vm_def_vlan_pri;
0085 };
0086 
0087 struct dsaf_tbl_tcam_data {
0088     u32 tbl_tcam_data_high;
0089     u32 tbl_tcam_data_low;
0090 };
0091 
0092 #define DSAF_PORT_MSK_NUM \
0093     ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
0094 struct dsaf_tbl_tcam_mcast_cfg {
0095     u8 tbl_mcast_old_en;
0096     u8 tbl_mcast_item_vld;
0097     u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
0098 };
0099 
0100 struct dsaf_tbl_tcam_ucast_cfg {
0101     u32 tbl_ucast_old_en;
0102     u32 tbl_ucast_item_vld;
0103     u32 tbl_ucast_mac_discard;
0104     u32 tbl_ucast_dvc;
0105     u32 tbl_ucast_out_port;
0106 };
0107 
0108 struct dsaf_tbl_line_cfg {
0109     u32 tbl_line_mac_discard;
0110     u32 tbl_line_dvc;
0111     u32 tbl_line_out_port;
0112 };
0113 
0114 enum dsaf_port_rate_mode {
0115     DSAF_PORT_RATE_1000 = 0,
0116     DSAF_PORT_RATE_2500,
0117     DSAF_PORT_RATE_10000
0118 };
0119 
0120 enum dsaf_stp_port_type {
0121     DSAF_STP_PORT_TYPE_DISCARD = 0,
0122     DSAF_STP_PORT_TYPE_BLOCK = 1,
0123     DSAF_STP_PORT_TYPE_LISTEN = 2,
0124     DSAF_STP_PORT_TYPE_LEARN = 3,
0125     DSAF_STP_PORT_TYPE_FORWARD = 4
0126 };
0127 
0128 enum dsaf_sw_port_type {
0129     DSAF_SW_PORT_TYPE_NON_VLAN = 0,
0130     DSAF_SW_PORT_TYPE_ACCESS = 1,
0131     DSAF_SW_PORT_TYPE_TRUNK = 2,
0132 };
0133 
0134 #define DSAF_SUB_BASE_SIZE                        (0x10000)
0135 
0136 /* dsaf mode define */
0137 enum dsaf_mode {
0138     DSAF_MODE_INVALID = 0,  /**< Invalid dsaf mode */
0139     DSAF_MODE_ENABLE_FIX,   /**< en DSAF-mode, fixed to queue*/
0140     DSAF_MODE_ENABLE_0VM,   /**< en DSAF-mode, support 0 VM */
0141     DSAF_MODE_ENABLE_8VM,   /**< en DSAF-mode, support 8 VM */
0142     DSAF_MODE_ENABLE_16VM,  /**< en DSAF-mode, support 16 VM */
0143     DSAF_MODE_ENABLE_32VM,  /**< en DSAF-mode, support 32 VM */
0144     DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */
0145     DSAF_MODE_ENABLE,       /**< before is enable DSAF mode*/
0146     DSAF_MODE_DISABLE_SP,   /* <non-dsaf, single port mode */
0147     DSAF_MODE_DISABLE_FIX,  /**< non-dasf, fixed to queue*/
0148     DSAF_MODE_DISABLE_2PORT_8VM,    /**< non-dasf, 2port 8VM */
0149     DSAF_MODE_DISABLE_2PORT_16VM,   /**< non-dasf, 2port 16VM */
0150     DSAF_MODE_DISABLE_2PORT_64VM,   /**< non-dasf, 2port 64VM */
0151     DSAF_MODE_DISABLE_6PORT_0VM,    /**< non-dasf, 6port 0VM */
0152     DSAF_MODE_DISABLE_6PORT_2VM,    /**< non-dasf, 6port 2VM */
0153     DSAF_MODE_DISABLE_6PORT_4VM,    /**< non-dasf, 6port 4VM */
0154     DSAF_MODE_DISABLE_6PORT_16VM,   /**< non-dasf, 6port 16VM */
0155     DSAF_MODE_MAX       /**< the last one, use as the num */
0156 };
0157 
0158 #define DSAF_DEST_PORT_NUM 256  /* DSAF max port num */
0159 #define DSAF_WORD_BIT_CNT 32  /* the num bit of word */
0160 
0161 /*mac entry, mc or uc entry*/
0162 struct dsaf_drv_mac_single_dest_entry {
0163     /* mac addr, match the entry*/
0164     u8 addr[ETH_ALEN];
0165     u16 in_vlan_id; /* value of VlanId */
0166 
0167     /* the vld input port num, dsaf-mode fix 0, */
0168     /*  non-dasf is the entry whitch port vld*/
0169     u8 in_port_num;
0170 
0171     u8 port_num; /*output port num*/
0172     u8 rsv[6];
0173 };
0174 
0175 /*only mc entry*/
0176 struct dsaf_drv_mac_multi_dest_entry {
0177     /* mac addr, match the entry*/
0178     u8 addr[ETH_ALEN];
0179     u16 in_vlan_id;
0180     /* this mac addr output port,*/
0181     /*  bit0-bit5 means Port0-Port5(1bit is vld)**/
0182     u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
0183 
0184     /* the vld input port num, dsaf-mode fix 0,*/
0185     /*  non-dasf is the entry whitch port vld*/
0186     u8 in_port_num;
0187     u8 rsv[7];
0188 };
0189 
0190 struct dsaf_hw_stats {
0191     u64 pad_drop;
0192     u64 man_pkts;
0193     u64 rx_pkts;
0194     u64 rx_pkt_id;
0195     u64 rx_pause_frame;
0196     u64 release_buf_num;
0197     u64 sbm_drop;
0198     u64 crc_false;
0199     u64 bp_drop;
0200     u64 rslt_drop;
0201     u64 local_addr_false;
0202     u64 vlan_drop;
0203     u64 stp_drop;
0204     u64 rx_pfc[DSAF_PRIO_NR];
0205     u64 tx_pfc[DSAF_PRIO_NR];
0206     u64 tx_pkts;
0207 };
0208 
0209 struct hnae_vf_cb {
0210     u8 port_index;
0211     struct hns_mac_cb *mac_cb;
0212     struct dsaf_device *dsaf_dev;
0213     struct hnae_handle  ae_handle; /* must be the last member */
0214 };
0215 
0216 struct dsaf_int_xge_src {
0217     u32    xid_xge_ecc_err_int_src;
0218     u32    xid_xge_fsm_timout_int_src;
0219     u32    sbm_xge_lnk_fsm_timout_int_src;
0220     u32    sbm_xge_lnk_ecc_2bit_int_src;
0221     u32    sbm_xge_mib_req_failed_int_src;
0222     u32    sbm_xge_mib_req_fsm_timout_int_src;
0223     u32    sbm_xge_mib_rels_fsm_timout_int_src;
0224     u32    sbm_xge_sram_ecc_2bit_int_src;
0225     u32    sbm_xge_mib_buf_sum_err_int_src;
0226     u32    sbm_xge_mib_req_extra_int_src;
0227     u32    sbm_xge_mib_rels_extra_int_src;
0228     u32    voq_xge_start_to_over_0_int_src;
0229     u32    voq_xge_start_to_over_1_int_src;
0230     u32    voq_xge_ecc_err_int_src;
0231 };
0232 
0233 struct dsaf_int_ppe_src {
0234     u32    xid_ppe_fsm_timout_int_src;
0235     u32    sbm_ppe_lnk_fsm_timout_int_src;
0236     u32    sbm_ppe_lnk_ecc_2bit_int_src;
0237     u32    sbm_ppe_mib_req_failed_int_src;
0238     u32    sbm_ppe_mib_req_fsm_timout_int_src;
0239     u32    sbm_ppe_mib_rels_fsm_timout_int_src;
0240     u32    sbm_ppe_sram_ecc_2bit_int_src;
0241     u32    sbm_ppe_mib_buf_sum_err_int_src;
0242     u32    sbm_ppe_mib_req_extra_int_src;
0243     u32    sbm_ppe_mib_rels_extra_int_src;
0244     u32    voq_ppe_start_to_over_0_int_src;
0245     u32    voq_ppe_ecc_err_int_src;
0246     u32    xod_ppe_fifo_rd_empty_int_src;
0247     u32    xod_ppe_fifo_wr_full_int_src;
0248 };
0249 
0250 struct dsaf_int_rocee_src {
0251     u32    xid_rocee_fsm_timout_int_src;
0252     u32    sbm_rocee_lnk_fsm_timout_int_src;
0253     u32    sbm_rocee_lnk_ecc_2bit_int_src;
0254     u32    sbm_rocee_mib_req_failed_int_src;
0255     u32    sbm_rocee_mib_req_fsm_timout_int_src;
0256     u32    sbm_rocee_mib_rels_fsm_timout_int_src;
0257     u32    sbm_rocee_sram_ecc_2bit_int_src;
0258     u32    sbm_rocee_mib_buf_sum_err_int_src;
0259     u32    sbm_rocee_mib_req_extra_int_src;
0260     u32    sbm_rocee_mib_rels_extra_int_src;
0261     u32    voq_rocee_start_to_over_0_int_src;
0262     u32    voq_rocee_ecc_err_int_src;
0263 };
0264 
0265 struct dsaf_int_tbl_src {
0266     u32    tbl_da0_mis_src;
0267     u32    tbl_da1_mis_src;
0268     u32    tbl_da2_mis_src;
0269     u32    tbl_da3_mis_src;
0270     u32    tbl_da4_mis_src;
0271     u32    tbl_da5_mis_src;
0272     u32    tbl_da6_mis_src;
0273     u32    tbl_da7_mis_src;
0274     u32    tbl_sa_mis_src;
0275     u32    tbl_old_sech_end_src;
0276     u32    lram_ecc_err1_src;
0277     u32    lram_ecc_err2_src;
0278     u32    tram_ecc_err1_src;
0279     u32    tram_ecc_err2_src;
0280     u32    tbl_ucast_bcast_xge0_src;
0281     u32    tbl_ucast_bcast_xge1_src;
0282     u32    tbl_ucast_bcast_xge2_src;
0283     u32    tbl_ucast_bcast_xge3_src;
0284     u32    tbl_ucast_bcast_xge4_src;
0285     u32    tbl_ucast_bcast_xge5_src;
0286     u32    tbl_ucast_bcast_ppe_src;
0287     u32    tbl_ucast_bcast_rocee_src;
0288 };
0289 
0290 struct dsaf_int_stat {
0291     struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
0292     struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
0293     struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
0294     struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
0295 
0296 };
0297 
0298 struct dsaf_misc_op {
0299     void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status,
0300                  u16 speed, int data);
0301     void (*cpld_reset_led)(struct hns_mac_cb *mac_cb);
0302     int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb,
0303                    enum hnae_led_state status);
0304     /* reset series function, it will be reset if the dereset is 0 */
0305     void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset);
0306     void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
0307     void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
0308     void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
0309     void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);
0310     void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,
0311                    bool dereset);
0312     void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);
0313 
0314     phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);
0315     int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);
0316 
0317     int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en);
0318 };
0319 
0320 /* Dsaf device struct define ,and mac ->  dsaf */
0321 struct dsaf_device {
0322     struct device *dev;
0323     struct hnae_ae_dev ae_dev;
0324 
0325     u8 __iomem *sc_base;
0326     u8 __iomem *sds_base;
0327     u8 __iomem *ppe_base;
0328     u8 __iomem *io_base;
0329     struct regmap *sub_ctrl;
0330     phys_addr_t ppe_paddr;
0331 
0332     u32 desc_num; /*  desc num per queue*/
0333     u32 buf_size; /*  ring buffer size */
0334     u32 reset_offset; /* reset field offset in sub sysctrl */
0335     int buf_size_type; /* ring buffer size-type */
0336     enum dsaf_mode dsaf_mode;    /* dsaf mode  */
0337     enum hal_dsaf_mode dsaf_en;
0338     enum hal_dsaf_tc_mode dsaf_tc_mode;
0339     u32 dsaf_ver;
0340     u16 tcam_max_num;   /* max TCAM entry for user except promisc */
0341 
0342     struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
0343     struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
0344     struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM];
0345     struct dsaf_misc_op *misc_op;
0346 
0347     struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
0348     struct dsaf_int_stat int_stat;
0349     /* make sure tcam table config spinlock */
0350     spinlock_t tcam_lock;
0351 };
0352 
0353 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev)
0354 {
0355     return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev));
0356 }
0357 
0358 #define DSAF_TBL_TCAM_KEY_PORT_S 0
0359 #define DSAF_TBL_TCAM_KEY_PORT_M (((1ULL << 4) - 1) << 0)
0360 #define DSAF_TBL_TCAM_KEY_VLAN_S 4
0361 #define DSAF_TBL_TCAM_KEY_VLAN_M (((1ULL << 12) - 1) << 4)
0362 
0363 struct dsaf_drv_tbl_tcam_key {
0364     union {
0365         struct {
0366             u8 mac_3;
0367             u8 mac_2;
0368             u8 mac_1;
0369             u8 mac_0;
0370         } bits;
0371 
0372         u32 val;
0373     } high;
0374     union {
0375         struct {
0376             u16 port_vlan;
0377             u8 mac_5;
0378             u8 mac_4;
0379         } bits;
0380 
0381         u32 val;
0382     } low;
0383 };
0384 
0385 struct dsaf_drv_soft_mac_tbl {
0386     struct dsaf_drv_tbl_tcam_key tcam_key;
0387     u16 index; /*the entry's index in tcam tab*/
0388 };
0389 
0390 struct dsaf_drv_priv {
0391     /* soft tab Mac key, for hardware tab*/
0392     struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
0393 };
0394 
0395 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
0396                           u32 tab_tcam_addr)
0397 {
0398     dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
0399                DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
0400                tab_tcam_addr);
0401 }
0402 
0403 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
0404 {
0405     u32 o_tbl_pul;
0406 
0407     o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
0408     dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
0409     dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
0410     dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
0411     dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
0412 }
0413 
0414 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
0415                           u32 tab_line_addr)
0416 {
0417     dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
0418                DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
0419                tab_line_addr);
0420 }
0421 
0422 static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
0423     struct hnae_handle *handle)
0424 {
0425     return container_of(handle, struct hnae_vf_cb, ae_handle);
0426 }
0427 
0428 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
0429                   struct dsaf_drv_mac_single_dest_entry *mac_entry);
0430 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
0431                  struct dsaf_drv_mac_single_dest_entry *mac_entry);
0432 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
0433                u8 in_port_num, u8 *addr);
0434 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
0435                  struct dsaf_drv_mac_single_dest_entry *mac_entry);
0436 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
0437 
0438 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
0439 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
0440 
0441 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
0442 
0443 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset);
0444 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port);
0445 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
0446               struct dsaf_device *dsaf_dev);
0447 
0448 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
0449 int hns_dsaf_get_regs_count(void);
0450 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
0451 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
0452                    u32 port, bool enable);
0453 
0454 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
0455                   u32 *en);
0456 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
0457                  u32 en);
0458 int hns_dsaf_rm_mac_addr(
0459     struct dsaf_device *dsaf_dev,
0460     struct dsaf_drv_mac_single_dest_entry *mac_entry);
0461 
0462 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev,
0463                  u8 mac_id, u8 port_num);
0464 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port);
0465 
0466 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
0467 
0468 #endif /* __HNS_DSAF_MAIN_H__ */
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