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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014-2015 Hisilicon Limited.
0004  */
0005 
0006 #include <linux/delay.h>
0007 #include <linux/of_mdio.h>
0008 #include "hns_dsaf_main.h"
0009 #include "hns_dsaf_mac.h"
0010 #include "hns_dsaf_gmac.h"
0011 
0012 static const struct mac_stats_string g_gmac_stats_string[] = {
0013     {"gmac_rx_octets_total_ok", MAC_STATS_FIELD_OFF(rx_good_bytes)},
0014     {"gmac_rx_octets_bad", MAC_STATS_FIELD_OFF(rx_bad_bytes)},
0015     {"gmac_rx_uc_pkts", MAC_STATS_FIELD_OFF(rx_uc_pkts)},
0016     {"gmac_rx_mc_pkts", MAC_STATS_FIELD_OFF(rx_mc_pkts)},
0017     {"gmac_rx_bc_pkts", MAC_STATS_FIELD_OFF(rx_bc_pkts)},
0018     {"gmac_rx_pkts_64octets", MAC_STATS_FIELD_OFF(rx_64bytes)},
0019     {"gmac_rx_pkts_65to127", MAC_STATS_FIELD_OFF(rx_65to127)},
0020     {"gmac_rx_pkts_128to255", MAC_STATS_FIELD_OFF(rx_128to255)},
0021     {"gmac_rx_pkts_256to511", MAC_STATS_FIELD_OFF(rx_256to511)},
0022     {"gmac_rx_pkts_512to1023", MAC_STATS_FIELD_OFF(rx_512to1023)},
0023     {"gmac_rx_pkts_1024to1518", MAC_STATS_FIELD_OFF(rx_1024to1518)},
0024     {"gmac_rx_pkts_1519tomax", MAC_STATS_FIELD_OFF(rx_1519tomax)},
0025     {"gmac_rx_fcs_errors", MAC_STATS_FIELD_OFF(rx_fcs_err)},
0026     {"gmac_rx_tagged", MAC_STATS_FIELD_OFF(rx_vlan_pkts)},
0027     {"gmac_rx_data_err", MAC_STATS_FIELD_OFF(rx_data_err)},
0028     {"gmac_rx_align_errors", MAC_STATS_FIELD_OFF(rx_align_err)},
0029     {"gmac_rx_long_errors", MAC_STATS_FIELD_OFF(rx_oversize)},
0030     {"gmac_rx_jabber_errors", MAC_STATS_FIELD_OFF(rx_jabber_err)},
0031     {"gmac_rx_pause_maccontrol", MAC_STATS_FIELD_OFF(rx_pfc_tc0)},
0032     {"gmac_rx_unknown_maccontrol", MAC_STATS_FIELD_OFF(rx_unknown_ctrl)},
0033     {"gmac_rx_very_long_err", MAC_STATS_FIELD_OFF(rx_long_err)},
0034     {"gmac_rx_runt_err", MAC_STATS_FIELD_OFF(rx_minto64)},
0035     {"gmac_rx_short_err", MAC_STATS_FIELD_OFF(rx_under_min)},
0036     {"gmac_rx_filt_pkt", MAC_STATS_FIELD_OFF(rx_filter_pkts)},
0037     {"gmac_rx_octets_total_filt", MAC_STATS_FIELD_OFF(rx_filter_bytes)},
0038     {"gmac_rx_overrun_cnt", MAC_STATS_FIELD_OFF(rx_fifo_overrun_err)},
0039     {"gmac_rx_length_err", MAC_STATS_FIELD_OFF(rx_len_err)},
0040     {"gmac_rx_fail_comma", MAC_STATS_FIELD_OFF(rx_comma_err)},
0041 
0042     {"gmac_tx_octets_ok", MAC_STATS_FIELD_OFF(tx_good_bytes)},
0043     {"gmac_tx_octets_bad", MAC_STATS_FIELD_OFF(tx_bad_bytes)},
0044     {"gmac_tx_uc_pkts", MAC_STATS_FIELD_OFF(tx_uc_pkts)},
0045     {"gmac_tx_mc_pkts", MAC_STATS_FIELD_OFF(tx_mc_pkts)},
0046     {"gmac_tx_bc_pkts", MAC_STATS_FIELD_OFF(tx_bc_pkts)},
0047     {"gmac_tx_pkts_64octets", MAC_STATS_FIELD_OFF(tx_64bytes)},
0048     {"gmac_tx_pkts_65to127", MAC_STATS_FIELD_OFF(tx_65to127)},
0049     {"gmac_tx_pkts_128to255", MAC_STATS_FIELD_OFF(tx_128to255)},
0050     {"gmac_tx_pkts_256to511", MAC_STATS_FIELD_OFF(tx_256to511)},
0051     {"gmac_tx_pkts_512to1023", MAC_STATS_FIELD_OFF(tx_512to1023)},
0052     {"gmac_tx_pkts_1024to1518", MAC_STATS_FIELD_OFF(tx_1024to1518)},
0053     {"gmac_tx_pkts_1519tomax", MAC_STATS_FIELD_OFF(tx_1519tomax)},
0054     {"gmac_tx_excessive_length_drop", MAC_STATS_FIELD_OFF(tx_jabber_err)},
0055     {"gmac_tx_underrun", MAC_STATS_FIELD_OFF(tx_underrun_err)},
0056     {"gmac_tx_tagged", MAC_STATS_FIELD_OFF(tx_vlan)},
0057     {"gmac_tx_crc_error", MAC_STATS_FIELD_OFF(tx_crc_err)},
0058     {"gmac_tx_pause_frames", MAC_STATS_FIELD_OFF(tx_pfc_tc0)}
0059 };
0060 
0061 static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode)
0062 {
0063     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0064 
0065     /*enable GE rX/tX */
0066     if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
0067         dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
0068 
0069     if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
0070         /* enable rx pcs */
0071         dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0);
0072         dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
0073     }
0074 }
0075 
0076 static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode)
0077 {
0078     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0079 
0080     /*disable GE rX/tX */
0081     if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
0082         dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
0083 
0084     if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
0085         /* disable rx pcs */
0086         dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1);
0087         dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
0088     }
0089 }
0090 
0091 /* hns_gmac_get_en - get port enable
0092  * @mac_drv:mac device
0093  * @rx:rx enable
0094  * @tx:tx enable
0095  */
0096 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx)
0097 {
0098     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0099     u32 porten;
0100 
0101     porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
0102     *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B);
0103     *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B);
0104 }
0105 
0106 static void hns_gmac_free(void *mac_drv)
0107 {
0108     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0109     struct dsaf_device *dsaf_dev
0110         = (struct dsaf_device *)dev_get_drvdata(drv->dev);
0111 
0112     u32 mac_id = drv->mac_id;
0113 
0114     dsaf_dev->misc_op->ge_srst(dsaf_dev, mac_id, 0);
0115 }
0116 
0117 static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval)
0118 {
0119     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0120 
0121     dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M,
0122                GMAC_FC_TX_TIMER_S, newval);
0123 }
0124 
0125 static void hns_gmac_get_tx_auto_pause_frames(void *mac_drv, u16 *newval)
0126 {
0127     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0128 
0129     *newval = dsaf_get_dev_field(drv, GMAC_FC_TX_TIMER_REG,
0130                      GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S);
0131 }
0132 
0133 static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval)
0134 {
0135     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0136 
0137     dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M,
0138                GMAC_MAX_FRM_SIZE_S, newval);
0139 
0140     dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M,
0141                GMAC_MAX_FRM_SIZE_S, newval);
0142 }
0143 
0144 static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
0145 {
0146     u32 tx_ctrl;
0147     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0148 
0149     tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
0150     dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
0151     dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
0152     dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
0153 }
0154 
0155 static void hns_gmac_config_an_mode(void *mac_drv, u8 newval)
0156 {
0157     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0158 
0159     dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
0160              GMAC_TX_AN_EN_B, !!newval);
0161 }
0162 
0163 static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
0164 {
0165     u32 tx_loop_pkt_pri;
0166     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0167 
0168     tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
0169     dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
0170     dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
0171     dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
0172 }
0173 
0174 static void hns_gmac_get_duplex_type(void *mac_drv,
0175                      enum hns_gmac_duplex_mdoe *duplex_mode)
0176 {
0177     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0178 
0179     *duplex_mode = (enum hns_gmac_duplex_mdoe)dsaf_get_dev_bit(
0180         drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B);
0181 }
0182 
0183 static void hns_gmac_get_port_mode(void *mac_drv, enum hns_port_mode *port_mode)
0184 {
0185     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0186 
0187     *port_mode = (enum hns_port_mode)dsaf_get_dev_field(
0188         drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
0189 }
0190 
0191 static void hns_gmac_port_mode_get(void *mac_drv,
0192                    struct hns_gmac_port_mode_cfg *port_mode)
0193 {
0194     u32 tx_ctrl;
0195     u32 recv_ctrl;
0196     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0197 
0198     port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field(
0199         drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
0200 
0201     tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
0202     recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
0203 
0204     port_mode->max_frm_size =
0205         dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG,
0206                    GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S);
0207     port_mode->short_runts_thr =
0208         dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG,
0209                    GMAC_SHORT_RUNTS_THR_M,
0210                    GMAC_SHORT_RUNTS_THR_S);
0211 
0212     port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B);
0213     port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B);
0214     port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B);
0215 
0216     port_mode->runt_pkt_en =
0217         dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B);
0218     port_mode->strip_pad_en =
0219         dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B);
0220 }
0221 
0222 static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
0223                    u32 tx_pause_en)
0224 {
0225     u32 pause_en;
0226     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0227 
0228     pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
0229     dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
0230     dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
0231     dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
0232 }
0233 
0234 static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en,
0235                       u32 *tx_pause_en)
0236 {
0237     u32 pause_en;
0238     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0239 
0240     pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
0241 
0242     *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B);
0243     *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B);
0244 }
0245 
0246 static bool hns_gmac_need_adjust_link(void *mac_drv, enum mac_speed speed,
0247                       int duplex)
0248 {
0249     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0250     struct hns_mac_cb *mac_cb = drv->mac_cb;
0251 
0252     return (mac_cb->speed != speed) ||
0253         (mac_cb->half_duplex == duplex);
0254 }
0255 
0256 static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
0257                 u32 full_duplex)
0258 {
0259     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0260 
0261     dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
0262              GMAC_DUPLEX_TYPE_B, !!full_duplex);
0263 
0264     switch (speed) {
0265     case MAC_SPEED_10:
0266         dsaf_set_dev_field(
0267             drv, GMAC_PORT_MODE_REG,
0268             GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
0269         break;
0270     case MAC_SPEED_100:
0271         dsaf_set_dev_field(
0272             drv, GMAC_PORT_MODE_REG,
0273             GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
0274         break;
0275     case MAC_SPEED_1000:
0276         dsaf_set_dev_field(
0277             drv, GMAC_PORT_MODE_REG,
0278             GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
0279         break;
0280     default:
0281         dev_err(drv->dev,
0282             "hns_gmac_adjust_link fail, speed%d mac%d\n",
0283             speed, drv->mac_id);
0284         return -EINVAL;
0285     }
0286 
0287     return 0;
0288 }
0289 
0290 static void hns_gmac_set_uc_match(void *mac_drv, u16 en)
0291 {
0292     struct mac_driver *drv = mac_drv;
0293 
0294     dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG,
0295              GMAC_UC_MATCH_EN_B, !en);
0296     dsaf_set_dev_bit(drv, GMAC_STATION_ADDR_HIGH_2_REG,
0297              GMAC_ADDR_EN_B, !en);
0298 }
0299 
0300 static void hns_gmac_set_promisc(void *mac_drv, u8 en)
0301 {
0302     struct mac_driver *drv = mac_drv;
0303 
0304     if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
0305         hns_gmac_set_uc_match(mac_drv, en);
0306 }
0307 
0308 static int hns_gmac_wait_fifo_clean(void *mac_drv)
0309 {
0310     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0311     int wait_cnt;
0312     u32 val;
0313 
0314     wait_cnt = 0;
0315     while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
0316         val = dsaf_read_dev(drv, GMAC_FIFO_STATE_REG);
0317         /* bit5~bit0 is not send complete pkts */
0318         if ((val & 0x3f) == 0)
0319             break;
0320         usleep_range(100, 200);
0321     }
0322 
0323     if (wait_cnt >= HNS_MAX_WAIT_CNT) {
0324         dev_err(drv->dev,
0325             "hns ge %d fifo was not idle.\n", drv->mac_id);
0326         return -EBUSY;
0327     }
0328 
0329     return 0;
0330 }
0331 
0332 static void hns_gmac_init(void *mac_drv)
0333 {
0334     u32 port;
0335     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0336     struct dsaf_device *dsaf_dev
0337         = (struct dsaf_device *)dev_get_drvdata(drv->dev);
0338 
0339     port = drv->mac_id;
0340 
0341     dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0);
0342     mdelay(10);
0343     dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1);
0344     mdelay(10);
0345     hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX);
0346     hns_gmac_tx_loop_pkt_dis(mac_drv);
0347     if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
0348         hns_gmac_set_uc_match(mac_drv, 0);
0349 
0350     hns_gmac_config_pad_and_crc(mac_drv, 1);
0351 
0352     dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
0353              GMAC_MODE_CHANGE_EB_B, 1);
0354 
0355     /* reduce gmac tx water line to avoid gmac hang-up
0356      * in speed 100M and duplex half.
0357      */
0358     dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK,
0359                GMAC_TX_WATER_LINE_SHIFT, 8);
0360 }
0361 
0362 static void hns_gmac_update_stats(void *mac_drv)
0363 {
0364     struct mac_hw_stats *hw_stats = NULL;
0365     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0366 
0367     hw_stats = &drv->mac_cb->hw_stats;
0368 
0369     /* RX */
0370     hw_stats->rx_good_bytes
0371         += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
0372     hw_stats->rx_bad_bytes
0373         += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
0374     hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
0375     hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
0376     hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
0377     hw_stats->rx_64bytes
0378         += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
0379     hw_stats->rx_65to127
0380         += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
0381     hw_stats->rx_128to255
0382         += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
0383     hw_stats->rx_256to511
0384         += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
0385     hw_stats->rx_512to1023
0386         += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
0387     hw_stats->rx_1024to1518
0388         += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
0389     hw_stats->rx_1519tomax
0390         += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
0391     hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
0392     hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
0393     hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
0394     hw_stats->rx_align_err
0395         += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
0396     hw_stats->rx_oversize
0397         += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
0398     hw_stats->rx_jabber_err
0399         += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
0400     hw_stats->rx_pfc_tc0
0401         += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
0402     hw_stats->rx_unknown_ctrl
0403         += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
0404     hw_stats->rx_long_err
0405         += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
0406     hw_stats->rx_minto64
0407         += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
0408     hw_stats->rx_under_min
0409         += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
0410     hw_stats->rx_filter_pkts
0411         += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
0412     hw_stats->rx_filter_bytes
0413         += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
0414     hw_stats->rx_fifo_overrun_err
0415         += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
0416     hw_stats->rx_len_err
0417         += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
0418     hw_stats->rx_comma_err
0419         += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
0420 
0421     /* TX */
0422     hw_stats->tx_good_bytes
0423         += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
0424     hw_stats->tx_bad_bytes
0425         += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
0426     hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
0427     hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
0428     hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
0429     hw_stats->tx_64bytes
0430         += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
0431     hw_stats->tx_65to127
0432         += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
0433     hw_stats->tx_128to255
0434         += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
0435     hw_stats->tx_256to511
0436         += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
0437     hw_stats->tx_512to1023
0438         += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
0439     hw_stats->tx_1024to1518
0440         += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
0441     hw_stats->tx_1519tomax
0442         += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
0443     hw_stats->tx_jabber_err
0444         += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
0445     hw_stats->tx_underrun_err
0446         += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
0447     hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
0448     hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
0449     hw_stats->tx_pfc_tc0
0450         += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
0451 }
0452 
0453 static void hns_gmac_set_mac_addr(void *mac_drv, const char *mac_addr)
0454 {
0455     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0456 
0457     u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
0458 
0459     u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
0460         | (mac_addr[3] << 16) | (mac_addr[2] << 24);
0461 
0462     u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
0463     u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B);
0464 
0465     dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
0466     dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG,
0467                high_val | (sta_addr_en << GMAC_ADDR_EN_B));
0468 }
0469 
0470 static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode,
0471                     u8 enable)
0472 {
0473     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0474 
0475     switch (loop_mode) {
0476     case MAC_INTERNALLOOP_MAC:
0477         dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B,
0478                  !!enable);
0479         break;
0480     default:
0481         dev_err(drv->dev, "loop_mode error\n");
0482         return -EINVAL;
0483     }
0484 
0485     return 0;
0486 }
0487 
0488 static void hns_gmac_get_info(void *mac_drv, struct mac_info *mac_info)
0489 {
0490     enum hns_gmac_duplex_mdoe duplex;
0491     enum hns_port_mode speed;
0492     u32 rx_pause;
0493     u32 tx_pause;
0494     u32 rx;
0495     u32 tx;
0496     u16 fc_tx_timer;
0497     struct hns_gmac_port_mode_cfg port_mode = { GMAC_10M_MII, 0 };
0498 
0499     hns_gmac_port_mode_get(mac_drv, &port_mode);
0500     mac_info->pad_and_crc_en = port_mode.crc_add && port_mode.pad_enable;
0501     mac_info->auto_neg = port_mode.an_enable;
0502 
0503     hns_gmac_get_tx_auto_pause_frames(mac_drv, &fc_tx_timer);
0504     mac_info->tx_pause_time = fc_tx_timer;
0505 
0506     hns_gmac_get_en(mac_drv, &rx, &tx);
0507     mac_info->port_en = rx && tx;
0508 
0509     hns_gmac_get_duplex_type(mac_drv, &duplex);
0510     mac_info->duplex = duplex;
0511 
0512     hns_gmac_get_port_mode(mac_drv, &speed);
0513     switch (speed) {
0514     case GMAC_10M_SGMII:
0515         mac_info->speed = MAC_SPEED_10;
0516         break;
0517     case GMAC_100M_SGMII:
0518         mac_info->speed = MAC_SPEED_100;
0519         break;
0520     case GMAC_1000M_SGMII:
0521         mac_info->speed = MAC_SPEED_1000;
0522         break;
0523     default:
0524         mac_info->speed = 0;
0525         break;
0526     }
0527 
0528     hns_gmac_get_pausefrm_cfg(mac_drv, &rx_pause, &tx_pause);
0529     mac_info->rx_pause_en = rx_pause;
0530     mac_info->tx_pause_en = tx_pause;
0531 }
0532 
0533 static void hns_gmac_autoneg_stat(void *mac_drv, u32 *enable)
0534 {
0535     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0536 
0537     *enable = dsaf_get_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
0538                    GMAC_TX_AN_EN_B);
0539 }
0540 
0541 static void hns_gmac_get_link_status(void *mac_drv, u32 *link_stat)
0542 {
0543     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0544 
0545     *link_stat = dsaf_get_dev_bit(drv, GMAC_AN_NEG_STATE_REG,
0546                       GMAC_AN_NEG_STAT_RX_SYNC_OK_B);
0547 }
0548 
0549 static void hns_gmac_get_regs(void *mac_drv, void *data)
0550 {
0551     u32 *regs = data;
0552     int i;
0553     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0554 
0555     /* base config registers */
0556     regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG);
0557     regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG);
0558     regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG);
0559     regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG);
0560     regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG);
0561     regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG);
0562     regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG);
0563     regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG);
0564     regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG);
0565     regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
0566     regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
0567     regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG);
0568     regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG);
0569     regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG);
0570     regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
0571     regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG);
0572     regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG);
0573 
0574     /* rx static registers */
0575     regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
0576     regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
0577     regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
0578     regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
0579     regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
0580     regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
0581     regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
0582     regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
0583     regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
0584     regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
0585     regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
0586     regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
0587     regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
0588     regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
0589     regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
0590     regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
0591     regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
0592     regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
0593     regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
0594     regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
0595     regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
0596     regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
0597     regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
0598     regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
0599     regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
0600 
0601     /* tx static registers */
0602     regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
0603     regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
0604     regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
0605     regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
0606     regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
0607     regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
0608     regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
0609     regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
0610     regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
0611     regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
0612     regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
0613     regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
0614     regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
0615     regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
0616     regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
0617     regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
0618     regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
0619 
0620     regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME);
0621     regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG);
0622     regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG);
0623     regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG);
0624     regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG);
0625     regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG);
0626     regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG);
0627     regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
0628     regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG);
0629     regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
0630     regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
0631     regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
0632 
0633     regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG);
0634     regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG);
0635     regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG);
0636     regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG);
0637     regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG);
0638     regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
0639     regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG);
0640     regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG);
0641     regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG);
0642     regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG);
0643     regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG);
0644     regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG);
0645     regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG);
0646     regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG);
0647     regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG);
0648     regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG);
0649     regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG);
0650     regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
0651 
0652     /* mark end of mac regs */
0653     for (i = 89; i < 96; i++)
0654         regs[i] = 0xaaaaaaaa;
0655 }
0656 
0657 static void hns_gmac_get_stats(void *mac_drv, u64 *data)
0658 {
0659     u32 i;
0660     u64 *buf = data;
0661     struct mac_driver *drv = (struct mac_driver *)mac_drv;
0662     struct mac_hw_stats *hw_stats = NULL;
0663 
0664     hw_stats = &drv->mac_cb->hw_stats;
0665 
0666     for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
0667         buf[i] = DSAF_STATS_READ(hw_stats,
0668             g_gmac_stats_string[i].offset);
0669     }
0670 }
0671 
0672 static void hns_gmac_get_strings(u32 stringset, u8 *data)
0673 {
0674     u8 *buff = data;
0675     u32 i;
0676 
0677     if (stringset != ETH_SS_STATS)
0678         return;
0679 
0680     for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++)
0681         ethtool_sprintf(&buff, g_gmac_stats_string[i].desc);
0682 }
0683 
0684 static int hns_gmac_get_sset_count(int stringset)
0685 {
0686     if (stringset == ETH_SS_STATS)
0687         return ARRAY_SIZE(g_gmac_stats_string);
0688 
0689     return 0;
0690 }
0691 
0692 static int hns_gmac_get_regs_count(void)
0693 {
0694     return ETH_GMAC_DUMP_NUM;
0695 }
0696 
0697 void *hns_gmac_config(struct hns_mac_cb *mac_cb, struct mac_params *mac_param)
0698 {
0699     struct mac_driver *mac_drv;
0700 
0701     mac_drv = devm_kzalloc(mac_cb->dev, sizeof(*mac_drv), GFP_KERNEL);
0702     if (!mac_drv)
0703         return NULL;
0704 
0705     mac_drv->mac_init = hns_gmac_init;
0706     mac_drv->mac_enable = hns_gmac_enable;
0707     mac_drv->mac_disable = hns_gmac_disable;
0708     mac_drv->mac_free = hns_gmac_free;
0709     mac_drv->adjust_link = hns_gmac_adjust_link;
0710     mac_drv->need_adjust_link = hns_gmac_need_adjust_link;
0711     mac_drv->set_tx_auto_pause_frames = hns_gmac_set_tx_auto_pause_frames;
0712     mac_drv->config_max_frame_length = hns_gmac_config_max_frame_length;
0713     mac_drv->mac_pausefrm_cfg = hns_gmac_pause_frm_cfg;
0714 
0715     mac_drv->mac_id = mac_param->mac_id;
0716     mac_drv->mac_mode = mac_param->mac_mode;
0717     mac_drv->io_base = mac_param->vaddr;
0718     mac_drv->dev = mac_param->dev;
0719     mac_drv->mac_cb = mac_cb;
0720 
0721     mac_drv->set_mac_addr = hns_gmac_set_mac_addr;
0722     mac_drv->set_an_mode = hns_gmac_config_an_mode;
0723     mac_drv->config_loopback = hns_gmac_config_loopback;
0724     mac_drv->config_pad_and_crc = hns_gmac_config_pad_and_crc;
0725     mac_drv->get_info = hns_gmac_get_info;
0726     mac_drv->autoneg_stat = hns_gmac_autoneg_stat;
0727     mac_drv->get_pause_enable = hns_gmac_get_pausefrm_cfg;
0728     mac_drv->get_link_status = hns_gmac_get_link_status;
0729     mac_drv->get_regs = hns_gmac_get_regs;
0730     mac_drv->get_regs_count = hns_gmac_get_regs_count;
0731     mac_drv->get_ethtool_stats = hns_gmac_get_stats;
0732     mac_drv->get_sset_count = hns_gmac_get_sset_count;
0733     mac_drv->get_strings = hns_gmac_get_strings;
0734     mac_drv->update_stats = hns_gmac_update_stats;
0735     mac_drv->set_promiscuous = hns_gmac_set_promisc;
0736     mac_drv->wait_fifo_clean = hns_gmac_wait_fifo_clean;
0737 
0738     return (void *)mac_drv;
0739 }
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