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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Hisilicon Fast Ethernet MAC Driver
0004  *
0005  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
0006  */
0007 
0008 #include <linux/circ_buf.h>
0009 #include <linux/clk.h>
0010 #include <linux/etherdevice.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/module.h>
0013 #include <linux/of_mdio.h>
0014 #include <linux/of_net.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/reset.h>
0017 
0018 /* MAC control register list */
0019 #define MAC_PORTSEL         0x0200
0020 #define MAC_PORTSEL_STAT_CPU        BIT(0)
0021 #define MAC_PORTSEL_RMII        BIT(1)
0022 #define MAC_PORTSET         0x0208
0023 #define MAC_PORTSET_DUPLEX_FULL     BIT(0)
0024 #define MAC_PORTSET_LINKED      BIT(1)
0025 #define MAC_PORTSET_SPEED_100M      BIT(2)
0026 #define MAC_SET             0x0210
0027 #define MAX_FRAME_SIZE          1600
0028 #define MAX_FRAME_SIZE_MASK     GENMASK(10, 0)
0029 #define BIT_PAUSE_EN            BIT(18)
0030 #define RX_COALESCE_SET         0x0340
0031 #define RX_COALESCED_FRAME_OFFSET   24
0032 #define RX_COALESCED_FRAMES     8
0033 #define RX_COALESCED_TIMER      0x74
0034 #define QLEN_SET            0x0344
0035 #define RX_DEPTH_OFFSET         8
0036 #define MAX_HW_FIFO_DEPTH       64
0037 #define HW_TX_FIFO_DEPTH        12
0038 #define HW_RX_FIFO_DEPTH        (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH)
0039 #define IQFRM_DES           0x0354
0040 #define RX_FRAME_LEN_MASK       GENMASK(11, 0)
0041 #define IQ_ADDR             0x0358
0042 #define EQ_ADDR             0x0360
0043 #define EQFRM_LEN           0x0364
0044 #define ADDRQ_STAT          0x036C
0045 #define TX_CNT_INUSE_MASK       GENMASK(5, 0)
0046 #define BIT_TX_READY            BIT(24)
0047 #define BIT_RX_READY            BIT(25)
0048 /* global control register list */
0049 #define GLB_HOSTMAC_L32         0x0000
0050 #define GLB_HOSTMAC_H16         0x0004
0051 #define GLB_SOFT_RESET          0x0008
0052 #define SOFT_RESET_ALL          BIT(0)
0053 #define GLB_FWCTRL          0x0010
0054 #define FWCTRL_VLAN_ENABLE      BIT(0)
0055 #define FWCTRL_FW2CPU_ENA       BIT(5)
0056 #define FWCTRL_FWALL2CPU        BIT(7)
0057 #define GLB_MACTCTRL            0x0014
0058 #define MACTCTRL_UNI2CPU        BIT(1)
0059 #define MACTCTRL_MULTI2CPU      BIT(3)
0060 #define MACTCTRL_BROAD2CPU      BIT(5)
0061 #define MACTCTRL_MACT_ENA       BIT(7)
0062 #define GLB_IRQ_STAT            0x0030
0063 #define GLB_IRQ_ENA         0x0034
0064 #define IRQ_ENA_PORT0_MASK      GENMASK(7, 0)
0065 #define IRQ_ENA_PORT0           BIT(18)
0066 #define IRQ_ENA_ALL         BIT(19)
0067 #define GLB_IRQ_RAW         0x0038
0068 #define IRQ_INT_RX_RDY          BIT(0)
0069 #define IRQ_INT_TX_PER_PACKET       BIT(1)
0070 #define IRQ_INT_TX_FIFO_EMPTY       BIT(6)
0071 #define IRQ_INT_MULTI_RXRDY     BIT(7)
0072 #define DEF_INT_MASK            (IRQ_INT_MULTI_RXRDY | \
0073                     IRQ_INT_TX_PER_PACKET | \
0074                     IRQ_INT_TX_FIFO_EMPTY)
0075 #define GLB_MAC_L32_BASE        0x0100
0076 #define GLB_MAC_H16_BASE        0x0104
0077 #define MACFLT_HI16_MASK        GENMASK(15, 0)
0078 #define BIT_MACFLT_ENA          BIT(17)
0079 #define BIT_MACFLT_FW2CPU       BIT(21)
0080 #define GLB_MAC_H16(reg)        (GLB_MAC_H16_BASE + ((reg) * 0x8))
0081 #define GLB_MAC_L32(reg)        (GLB_MAC_L32_BASE + ((reg) * 0x8))
0082 #define MAX_MAC_FILTER_NUM      8
0083 #define MAX_UNICAST_ADDRESSES       2
0084 #define MAX_MULTICAST_ADDRESSES     (MAX_MAC_FILTER_NUM - \
0085                     MAX_UNICAST_ADDRESSES)
0086 /* software tx and rx queue number, should be power of 2 */
0087 #define TXQ_NUM             64
0088 #define RXQ_NUM             128
0089 #define FEMAC_POLL_WEIGHT       16
0090 
0091 #define PHY_RESET_DELAYS_PROPERTY   "hisilicon,phy-reset-delays-us"
0092 
0093 enum phy_reset_delays {
0094     PRE_DELAY,
0095     PULSE,
0096     POST_DELAY,
0097     DELAYS_NUM,
0098 };
0099 
0100 struct hisi_femac_queue {
0101     struct sk_buff **skb;
0102     dma_addr_t *dma_phys;
0103     int num;
0104     unsigned int head;
0105     unsigned int tail;
0106 };
0107 
0108 struct hisi_femac_priv {
0109     void __iomem *port_base;
0110     void __iomem *glb_base;
0111     struct clk *clk;
0112     struct reset_control *mac_rst;
0113     struct reset_control *phy_rst;
0114     u32 phy_reset_delays[DELAYS_NUM];
0115     u32 link_status;
0116 
0117     struct device *dev;
0118     struct net_device *ndev;
0119 
0120     struct hisi_femac_queue txq;
0121     struct hisi_femac_queue rxq;
0122     u32 tx_fifo_used_cnt;
0123     struct napi_struct napi;
0124 };
0125 
0126 static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs)
0127 {
0128     u32 val;
0129 
0130     val = readl(priv->glb_base + GLB_IRQ_ENA);
0131     writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
0132 }
0133 
0134 static void hisi_femac_irq_disable(struct hisi_femac_priv *priv, int irqs)
0135 {
0136     u32 val;
0137 
0138     val = readl(priv->glb_base + GLB_IRQ_ENA);
0139     writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
0140 }
0141 
0142 static void hisi_femac_tx_dma_unmap(struct hisi_femac_priv *priv,
0143                     struct sk_buff *skb, unsigned int pos)
0144 {
0145     dma_addr_t dma_addr;
0146 
0147     dma_addr = priv->txq.dma_phys[pos];
0148     dma_unmap_single(priv->dev, dma_addr, skb->len, DMA_TO_DEVICE);
0149 }
0150 
0151 static void hisi_femac_xmit_reclaim(struct net_device *dev)
0152 {
0153     struct sk_buff *skb;
0154     struct hisi_femac_priv *priv = netdev_priv(dev);
0155     struct hisi_femac_queue *txq = &priv->txq;
0156     unsigned int bytes_compl = 0, pkts_compl = 0;
0157     u32 val;
0158 
0159     netif_tx_lock(dev);
0160 
0161     val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK;
0162     while (val < priv->tx_fifo_used_cnt) {
0163         skb = txq->skb[txq->tail];
0164         if (unlikely(!skb)) {
0165             netdev_err(dev, "xmitq_cnt_inuse=%d, tx_fifo_used=%d\n",
0166                    val, priv->tx_fifo_used_cnt);
0167             break;
0168         }
0169         hisi_femac_tx_dma_unmap(priv, skb, txq->tail);
0170         pkts_compl++;
0171         bytes_compl += skb->len;
0172         dev_kfree_skb_any(skb);
0173 
0174         priv->tx_fifo_used_cnt--;
0175 
0176         val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK;
0177         txq->skb[txq->tail] = NULL;
0178         txq->tail = (txq->tail + 1) % txq->num;
0179     }
0180 
0181     netdev_completed_queue(dev, pkts_compl, bytes_compl);
0182 
0183     if (unlikely(netif_queue_stopped(dev)) && pkts_compl)
0184         netif_wake_queue(dev);
0185 
0186     netif_tx_unlock(dev);
0187 }
0188 
0189 static void hisi_femac_adjust_link(struct net_device *dev)
0190 {
0191     struct hisi_femac_priv *priv = netdev_priv(dev);
0192     struct phy_device *phy = dev->phydev;
0193     u32 status = 0;
0194 
0195     if (phy->link)
0196         status |= MAC_PORTSET_LINKED;
0197     if (phy->duplex == DUPLEX_FULL)
0198         status |= MAC_PORTSET_DUPLEX_FULL;
0199     if (phy->speed == SPEED_100)
0200         status |= MAC_PORTSET_SPEED_100M;
0201 
0202     if ((status != priv->link_status) &&
0203         ((status | priv->link_status) & MAC_PORTSET_LINKED)) {
0204         writel(status, priv->port_base + MAC_PORTSET);
0205         priv->link_status = status;
0206         phy_print_status(phy);
0207     }
0208 }
0209 
0210 static void hisi_femac_rx_refill(struct hisi_femac_priv *priv)
0211 {
0212     struct hisi_femac_queue *rxq = &priv->rxq;
0213     struct sk_buff *skb;
0214     u32 pos;
0215     u32 len = MAX_FRAME_SIZE;
0216     dma_addr_t addr;
0217 
0218     pos = rxq->head;
0219     while (readl(priv->port_base + ADDRQ_STAT) & BIT_RX_READY) {
0220         if (!CIRC_SPACE(pos, rxq->tail, rxq->num))
0221             break;
0222         if (unlikely(rxq->skb[pos])) {
0223             netdev_err(priv->ndev, "err skb[%d]=%p\n",
0224                    pos, rxq->skb[pos]);
0225             break;
0226         }
0227         skb = netdev_alloc_skb_ip_align(priv->ndev, len);
0228         if (unlikely(!skb))
0229             break;
0230 
0231         addr = dma_map_single(priv->dev, skb->data, len,
0232                       DMA_FROM_DEVICE);
0233         if (dma_mapping_error(priv->dev, addr)) {
0234             dev_kfree_skb_any(skb);
0235             break;
0236         }
0237         rxq->dma_phys[pos] = addr;
0238         rxq->skb[pos] = skb;
0239         writel(addr, priv->port_base + IQ_ADDR);
0240         pos = (pos + 1) % rxq->num;
0241     }
0242     rxq->head = pos;
0243 }
0244 
0245 static int hisi_femac_rx(struct net_device *dev, int limit)
0246 {
0247     struct hisi_femac_priv *priv = netdev_priv(dev);
0248     struct hisi_femac_queue *rxq = &priv->rxq;
0249     struct sk_buff *skb;
0250     dma_addr_t addr;
0251     u32 rx_pkt_info, pos, len, rx_pkts_num = 0;
0252 
0253     pos = rxq->tail;
0254     while (readl(priv->glb_base + GLB_IRQ_RAW) & IRQ_INT_RX_RDY) {
0255         rx_pkt_info = readl(priv->port_base + IQFRM_DES);
0256         len = rx_pkt_info & RX_FRAME_LEN_MASK;
0257         len -= ETH_FCS_LEN;
0258 
0259         /* tell hardware we will deal with this packet */
0260         writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
0261 
0262         rx_pkts_num++;
0263 
0264         skb = rxq->skb[pos];
0265         if (unlikely(!skb)) {
0266             netdev_err(dev, "rx skb NULL. pos=%d\n", pos);
0267             break;
0268         }
0269         rxq->skb[pos] = NULL;
0270 
0271         addr = rxq->dma_phys[pos];
0272         dma_unmap_single(priv->dev, addr, MAX_FRAME_SIZE,
0273                  DMA_FROM_DEVICE);
0274         skb_put(skb, len);
0275         if (unlikely(skb->len > MAX_FRAME_SIZE)) {
0276             netdev_err(dev, "rcv len err, len = %d\n", skb->len);
0277             dev->stats.rx_errors++;
0278             dev->stats.rx_length_errors++;
0279             dev_kfree_skb_any(skb);
0280             goto next;
0281         }
0282 
0283         skb->protocol = eth_type_trans(skb, dev);
0284         napi_gro_receive(&priv->napi, skb);
0285         dev->stats.rx_packets++;
0286         dev->stats.rx_bytes += skb->len;
0287 next:
0288         pos = (pos + 1) % rxq->num;
0289         if (rx_pkts_num >= limit)
0290             break;
0291     }
0292     rxq->tail = pos;
0293 
0294     hisi_femac_rx_refill(priv);
0295 
0296     return rx_pkts_num;
0297 }
0298 
0299 static int hisi_femac_poll(struct napi_struct *napi, int budget)
0300 {
0301     struct hisi_femac_priv *priv = container_of(napi,
0302                     struct hisi_femac_priv, napi);
0303     struct net_device *dev = priv->ndev;
0304     int work_done = 0, task = budget;
0305     int ints, num;
0306 
0307     do {
0308         hisi_femac_xmit_reclaim(dev);
0309         num = hisi_femac_rx(dev, task);
0310         work_done += num;
0311         task -= num;
0312         if (work_done >= budget)
0313             break;
0314 
0315         ints = readl(priv->glb_base + GLB_IRQ_RAW);
0316         writel(ints & DEF_INT_MASK,
0317                priv->glb_base + GLB_IRQ_RAW);
0318     } while (ints & DEF_INT_MASK);
0319 
0320     if (work_done < budget) {
0321         napi_complete_done(napi, work_done);
0322         hisi_femac_irq_enable(priv, DEF_INT_MASK &
0323                     (~IRQ_INT_TX_PER_PACKET));
0324     }
0325 
0326     return work_done;
0327 }
0328 
0329 static irqreturn_t hisi_femac_interrupt(int irq, void *dev_id)
0330 {
0331     int ints;
0332     struct net_device *dev = (struct net_device *)dev_id;
0333     struct hisi_femac_priv *priv = netdev_priv(dev);
0334 
0335     ints = readl(priv->glb_base + GLB_IRQ_RAW);
0336 
0337     if (likely(ints & DEF_INT_MASK)) {
0338         writel(ints & DEF_INT_MASK,
0339                priv->glb_base + GLB_IRQ_RAW);
0340         hisi_femac_irq_disable(priv, DEF_INT_MASK);
0341         napi_schedule(&priv->napi);
0342     }
0343 
0344     return IRQ_HANDLED;
0345 }
0346 
0347 static int hisi_femac_init_queue(struct device *dev,
0348                  struct hisi_femac_queue *queue,
0349                  unsigned int num)
0350 {
0351     queue->skb = devm_kcalloc(dev, num, sizeof(struct sk_buff *),
0352                   GFP_KERNEL);
0353     if (!queue->skb)
0354         return -ENOMEM;
0355 
0356     queue->dma_phys = devm_kcalloc(dev, num, sizeof(dma_addr_t),
0357                        GFP_KERNEL);
0358     if (!queue->dma_phys)
0359         return -ENOMEM;
0360 
0361     queue->num = num;
0362     queue->head = 0;
0363     queue->tail = 0;
0364 
0365     return 0;
0366 }
0367 
0368 static int hisi_femac_init_tx_and_rx_queues(struct hisi_femac_priv *priv)
0369 {
0370     int ret;
0371 
0372     ret = hisi_femac_init_queue(priv->dev, &priv->txq, TXQ_NUM);
0373     if (ret)
0374         return ret;
0375 
0376     ret = hisi_femac_init_queue(priv->dev, &priv->rxq, RXQ_NUM);
0377     if (ret)
0378         return ret;
0379 
0380     priv->tx_fifo_used_cnt = 0;
0381 
0382     return 0;
0383 }
0384 
0385 static void hisi_femac_free_skb_rings(struct hisi_femac_priv *priv)
0386 {
0387     struct hisi_femac_queue *txq = &priv->txq;
0388     struct hisi_femac_queue *rxq = &priv->rxq;
0389     struct sk_buff *skb;
0390     dma_addr_t dma_addr;
0391     u32 pos;
0392 
0393     pos = rxq->tail;
0394     while (pos != rxq->head) {
0395         skb = rxq->skb[pos];
0396         if (unlikely(!skb)) {
0397             netdev_err(priv->ndev, "NULL rx skb. pos=%d, head=%d\n",
0398                    pos, rxq->head);
0399             continue;
0400         }
0401 
0402         dma_addr = rxq->dma_phys[pos];
0403         dma_unmap_single(priv->dev, dma_addr, MAX_FRAME_SIZE,
0404                  DMA_FROM_DEVICE);
0405 
0406         dev_kfree_skb_any(skb);
0407         rxq->skb[pos] = NULL;
0408         pos = (pos + 1) % rxq->num;
0409     }
0410     rxq->tail = pos;
0411 
0412     pos = txq->tail;
0413     while (pos != txq->head) {
0414         skb = txq->skb[pos];
0415         if (unlikely(!skb)) {
0416             netdev_err(priv->ndev, "NULL tx skb. pos=%d, head=%d\n",
0417                    pos, txq->head);
0418             continue;
0419         }
0420         hisi_femac_tx_dma_unmap(priv, skb, pos);
0421         dev_kfree_skb_any(skb);
0422         txq->skb[pos] = NULL;
0423         pos = (pos + 1) % txq->num;
0424     }
0425     txq->tail = pos;
0426     priv->tx_fifo_used_cnt = 0;
0427 }
0428 
0429 static int hisi_femac_set_hw_mac_addr(struct hisi_femac_priv *priv,
0430                       const unsigned char *mac)
0431 {
0432     u32 reg;
0433 
0434     reg = mac[1] | (mac[0] << 8);
0435     writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
0436 
0437     reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
0438     writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
0439 
0440     return 0;
0441 }
0442 
0443 static int hisi_femac_port_reset(struct hisi_femac_priv *priv)
0444 {
0445     u32 val;
0446 
0447     val = readl(priv->glb_base + GLB_SOFT_RESET);
0448     val |= SOFT_RESET_ALL;
0449     writel(val, priv->glb_base + GLB_SOFT_RESET);
0450 
0451     usleep_range(500, 800);
0452 
0453     val &= ~SOFT_RESET_ALL;
0454     writel(val, priv->glb_base + GLB_SOFT_RESET);
0455 
0456     return 0;
0457 }
0458 
0459 static int hisi_femac_net_open(struct net_device *dev)
0460 {
0461     struct hisi_femac_priv *priv = netdev_priv(dev);
0462 
0463     hisi_femac_port_reset(priv);
0464     hisi_femac_set_hw_mac_addr(priv, dev->dev_addr);
0465     hisi_femac_rx_refill(priv);
0466 
0467     netif_carrier_off(dev);
0468     netdev_reset_queue(dev);
0469     netif_start_queue(dev);
0470     napi_enable(&priv->napi);
0471 
0472     priv->link_status = 0;
0473     if (dev->phydev)
0474         phy_start(dev->phydev);
0475 
0476     writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
0477     hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK);
0478 
0479     return 0;
0480 }
0481 
0482 static int hisi_femac_net_close(struct net_device *dev)
0483 {
0484     struct hisi_femac_priv *priv = netdev_priv(dev);
0485 
0486     hisi_femac_irq_disable(priv, IRQ_ENA_PORT0);
0487 
0488     if (dev->phydev)
0489         phy_stop(dev->phydev);
0490 
0491     netif_stop_queue(dev);
0492     napi_disable(&priv->napi);
0493 
0494     hisi_femac_free_skb_rings(priv);
0495 
0496     return 0;
0497 }
0498 
0499 static netdev_tx_t hisi_femac_net_xmit(struct sk_buff *skb,
0500                        struct net_device *dev)
0501 {
0502     struct hisi_femac_priv *priv = netdev_priv(dev);
0503     struct hisi_femac_queue *txq = &priv->txq;
0504     dma_addr_t addr;
0505     u32 val;
0506 
0507     val = readl(priv->port_base + ADDRQ_STAT);
0508     val &= BIT_TX_READY;
0509     if (!val) {
0510         hisi_femac_irq_enable(priv, IRQ_INT_TX_PER_PACKET);
0511         dev->stats.tx_dropped++;
0512         dev->stats.tx_fifo_errors++;
0513         netif_stop_queue(dev);
0514         return NETDEV_TX_BUSY;
0515     }
0516 
0517     if (unlikely(!CIRC_SPACE(txq->head, txq->tail,
0518                  txq->num))) {
0519         hisi_femac_irq_enable(priv, IRQ_INT_TX_PER_PACKET);
0520         dev->stats.tx_dropped++;
0521         dev->stats.tx_fifo_errors++;
0522         netif_stop_queue(dev);
0523         return NETDEV_TX_BUSY;
0524     }
0525 
0526     addr = dma_map_single(priv->dev, skb->data,
0527                   skb->len, DMA_TO_DEVICE);
0528     if (unlikely(dma_mapping_error(priv->dev, addr))) {
0529         dev_kfree_skb_any(skb);
0530         dev->stats.tx_dropped++;
0531         return NETDEV_TX_OK;
0532     }
0533     txq->dma_phys[txq->head] = addr;
0534 
0535     txq->skb[txq->head] = skb;
0536     txq->head = (txq->head + 1) % txq->num;
0537 
0538     writel(addr, priv->port_base + EQ_ADDR);
0539     writel(skb->len + ETH_FCS_LEN, priv->port_base + EQFRM_LEN);
0540 
0541     priv->tx_fifo_used_cnt++;
0542 
0543     dev->stats.tx_packets++;
0544     dev->stats.tx_bytes += skb->len;
0545     netdev_sent_queue(dev, skb->len);
0546 
0547     return NETDEV_TX_OK;
0548 }
0549 
0550 static int hisi_femac_set_mac_address(struct net_device *dev, void *p)
0551 {
0552     struct hisi_femac_priv *priv = netdev_priv(dev);
0553     struct sockaddr *skaddr = p;
0554 
0555     if (!is_valid_ether_addr(skaddr->sa_data))
0556         return -EADDRNOTAVAIL;
0557 
0558     eth_hw_addr_set(dev, skaddr->sa_data);
0559     dev->addr_assign_type &= ~NET_ADDR_RANDOM;
0560 
0561     hisi_femac_set_hw_mac_addr(priv, dev->dev_addr);
0562 
0563     return 0;
0564 }
0565 
0566 static void hisi_femac_enable_hw_addr_filter(struct hisi_femac_priv *priv,
0567                          unsigned int reg_n, bool enable)
0568 {
0569     u32 val;
0570 
0571     val = readl(priv->glb_base + GLB_MAC_H16(reg_n));
0572     if (enable)
0573         val |= BIT_MACFLT_ENA;
0574     else
0575         val &= ~BIT_MACFLT_ENA;
0576     writel(val, priv->glb_base + GLB_MAC_H16(reg_n));
0577 }
0578 
0579 static void hisi_femac_set_hw_addr_filter(struct hisi_femac_priv *priv,
0580                       unsigned char *addr,
0581                       unsigned int reg_n)
0582 {
0583     unsigned int high, low;
0584     u32 val;
0585 
0586     high = GLB_MAC_H16(reg_n);
0587     low = GLB_MAC_L32(reg_n);
0588 
0589     val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
0590     writel(val, priv->glb_base + low);
0591 
0592     val = readl(priv->glb_base + high);
0593     val &= ~MACFLT_HI16_MASK;
0594     val |= ((addr[0] << 8) | addr[1]);
0595     val |= (BIT_MACFLT_ENA | BIT_MACFLT_FW2CPU);
0596     writel(val, priv->glb_base + high);
0597 }
0598 
0599 static void hisi_femac_set_promisc_mode(struct hisi_femac_priv *priv,
0600                     bool promisc_mode)
0601 {
0602     u32 val;
0603 
0604     val = readl(priv->glb_base + GLB_FWCTRL);
0605     if (promisc_mode)
0606         val |= FWCTRL_FWALL2CPU;
0607     else
0608         val &= ~FWCTRL_FWALL2CPU;
0609     writel(val, priv->glb_base + GLB_FWCTRL);
0610 }
0611 
0612 /* Handle multiple multicast addresses (perfect filtering)*/
0613 static void hisi_femac_set_mc_addr_filter(struct hisi_femac_priv *priv)
0614 {
0615     struct net_device *dev = priv->ndev;
0616     u32 val;
0617 
0618     val = readl(priv->glb_base + GLB_MACTCTRL);
0619     if ((netdev_mc_count(dev) > MAX_MULTICAST_ADDRESSES) ||
0620         (dev->flags & IFF_ALLMULTI)) {
0621         val |= MACTCTRL_MULTI2CPU;
0622     } else {
0623         int reg = MAX_UNICAST_ADDRESSES;
0624         int i;
0625         struct netdev_hw_addr *ha;
0626 
0627         for (i = reg; i < MAX_MAC_FILTER_NUM; i++)
0628             hisi_femac_enable_hw_addr_filter(priv, i, false);
0629 
0630         netdev_for_each_mc_addr(ha, dev) {
0631             hisi_femac_set_hw_addr_filter(priv, ha->addr, reg);
0632             reg++;
0633         }
0634         val &= ~MACTCTRL_MULTI2CPU;
0635     }
0636     writel(val, priv->glb_base + GLB_MACTCTRL);
0637 }
0638 
0639 /* Handle multiple unicast addresses (perfect filtering)*/
0640 static void hisi_femac_set_uc_addr_filter(struct hisi_femac_priv *priv)
0641 {
0642     struct net_device *dev = priv->ndev;
0643     u32 val;
0644 
0645     val = readl(priv->glb_base + GLB_MACTCTRL);
0646     if (netdev_uc_count(dev) > MAX_UNICAST_ADDRESSES) {
0647         val |= MACTCTRL_UNI2CPU;
0648     } else {
0649         int reg = 0;
0650         int i;
0651         struct netdev_hw_addr *ha;
0652 
0653         for (i = reg; i < MAX_UNICAST_ADDRESSES; i++)
0654             hisi_femac_enable_hw_addr_filter(priv, i, false);
0655 
0656         netdev_for_each_uc_addr(ha, dev) {
0657             hisi_femac_set_hw_addr_filter(priv, ha->addr, reg);
0658             reg++;
0659         }
0660         val &= ~MACTCTRL_UNI2CPU;
0661     }
0662     writel(val, priv->glb_base + GLB_MACTCTRL);
0663 }
0664 
0665 static void hisi_femac_net_set_rx_mode(struct net_device *dev)
0666 {
0667     struct hisi_femac_priv *priv = netdev_priv(dev);
0668 
0669     if (dev->flags & IFF_PROMISC) {
0670         hisi_femac_set_promisc_mode(priv, true);
0671     } else {
0672         hisi_femac_set_promisc_mode(priv, false);
0673         hisi_femac_set_mc_addr_filter(priv);
0674         hisi_femac_set_uc_addr_filter(priv);
0675     }
0676 }
0677 
0678 static const struct ethtool_ops hisi_femac_ethtools_ops = {
0679     .get_link       = ethtool_op_get_link,
0680     .get_link_ksettings = phy_ethtool_get_link_ksettings,
0681     .set_link_ksettings = phy_ethtool_set_link_ksettings,
0682 };
0683 
0684 static const struct net_device_ops hisi_femac_netdev_ops = {
0685     .ndo_open       = hisi_femac_net_open,
0686     .ndo_stop       = hisi_femac_net_close,
0687     .ndo_start_xmit     = hisi_femac_net_xmit,
0688     .ndo_eth_ioctl      = phy_do_ioctl_running,
0689     .ndo_set_mac_address    = hisi_femac_set_mac_address,
0690     .ndo_set_rx_mode    = hisi_femac_net_set_rx_mode,
0691 };
0692 
0693 static void hisi_femac_core_reset(struct hisi_femac_priv *priv)
0694 {
0695     reset_control_assert(priv->mac_rst);
0696     reset_control_deassert(priv->mac_rst);
0697 }
0698 
0699 static void hisi_femac_sleep_us(u32 time_us)
0700 {
0701     u32 time_ms;
0702 
0703     if (!time_us)
0704         return;
0705 
0706     time_ms = DIV_ROUND_UP(time_us, 1000);
0707     if (time_ms < 20)
0708         usleep_range(time_us, time_us + 500);
0709     else
0710         msleep(time_ms);
0711 }
0712 
0713 static void hisi_femac_phy_reset(struct hisi_femac_priv *priv)
0714 {
0715     /* To make sure PHY hardware reset success,
0716      * we must keep PHY in deassert state first and
0717      * then complete the hardware reset operation
0718      */
0719     reset_control_deassert(priv->phy_rst);
0720     hisi_femac_sleep_us(priv->phy_reset_delays[PRE_DELAY]);
0721 
0722     reset_control_assert(priv->phy_rst);
0723     /* delay some time to ensure reset ok,
0724      * this depends on PHY hardware feature
0725      */
0726     hisi_femac_sleep_us(priv->phy_reset_delays[PULSE]);
0727     reset_control_deassert(priv->phy_rst);
0728     /* delay some time to ensure later MDIO access */
0729     hisi_femac_sleep_us(priv->phy_reset_delays[POST_DELAY]);
0730 }
0731 
0732 static void hisi_femac_port_init(struct hisi_femac_priv *priv)
0733 {
0734     u32 val;
0735 
0736     /* MAC gets link status info and phy mode by software config */
0737     val = MAC_PORTSEL_STAT_CPU;
0738     if (priv->ndev->phydev->interface == PHY_INTERFACE_MODE_RMII)
0739         val |= MAC_PORTSEL_RMII;
0740     writel(val, priv->port_base + MAC_PORTSEL);
0741 
0742     /*clear all interrupt status */
0743     writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
0744     hisi_femac_irq_disable(priv, IRQ_ENA_PORT0_MASK | IRQ_ENA_PORT0);
0745 
0746     val = readl(priv->glb_base + GLB_FWCTRL);
0747     val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU);
0748     val |= FWCTRL_FW2CPU_ENA;
0749     writel(val, priv->glb_base + GLB_FWCTRL);
0750 
0751     val = readl(priv->glb_base + GLB_MACTCTRL);
0752     val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA);
0753     writel(val, priv->glb_base + GLB_MACTCTRL);
0754 
0755     val = readl(priv->port_base + MAC_SET);
0756     val &= ~MAX_FRAME_SIZE_MASK;
0757     val |= MAX_FRAME_SIZE;
0758     writel(val, priv->port_base + MAC_SET);
0759 
0760     val = RX_COALESCED_TIMER |
0761         (RX_COALESCED_FRAMES << RX_COALESCED_FRAME_OFFSET);
0762     writel(val, priv->port_base + RX_COALESCE_SET);
0763 
0764     val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH;
0765     writel(val, priv->port_base + QLEN_SET);
0766 }
0767 
0768 static int hisi_femac_drv_probe(struct platform_device *pdev)
0769 {
0770     struct device *dev = &pdev->dev;
0771     struct device_node *node = dev->of_node;
0772     struct net_device *ndev;
0773     struct hisi_femac_priv *priv;
0774     struct phy_device *phy;
0775     int ret;
0776 
0777     ndev = alloc_etherdev(sizeof(*priv));
0778     if (!ndev)
0779         return -ENOMEM;
0780 
0781     platform_set_drvdata(pdev, ndev);
0782     SET_NETDEV_DEV(ndev, &pdev->dev);
0783 
0784     priv = netdev_priv(ndev);
0785     priv->dev = dev;
0786     priv->ndev = ndev;
0787 
0788     priv->port_base = devm_platform_ioremap_resource(pdev, 0);
0789     if (IS_ERR(priv->port_base)) {
0790         ret = PTR_ERR(priv->port_base);
0791         goto out_free_netdev;
0792     }
0793 
0794     priv->glb_base = devm_platform_ioremap_resource(pdev, 1);
0795     if (IS_ERR(priv->glb_base)) {
0796         ret = PTR_ERR(priv->glb_base);
0797         goto out_free_netdev;
0798     }
0799 
0800     priv->clk = devm_clk_get(&pdev->dev, NULL);
0801     if (IS_ERR(priv->clk)) {
0802         dev_err(dev, "failed to get clk\n");
0803         ret = -ENODEV;
0804         goto out_free_netdev;
0805     }
0806 
0807     ret = clk_prepare_enable(priv->clk);
0808     if (ret) {
0809         dev_err(dev, "failed to enable clk %d\n", ret);
0810         goto out_free_netdev;
0811     }
0812 
0813     priv->mac_rst = devm_reset_control_get(dev, "mac");
0814     if (IS_ERR(priv->mac_rst)) {
0815         ret = PTR_ERR(priv->mac_rst);
0816         goto out_disable_clk;
0817     }
0818     hisi_femac_core_reset(priv);
0819 
0820     priv->phy_rst = devm_reset_control_get(dev, "phy");
0821     if (IS_ERR(priv->phy_rst)) {
0822         priv->phy_rst = NULL;
0823     } else {
0824         ret = of_property_read_u32_array(node,
0825                          PHY_RESET_DELAYS_PROPERTY,
0826                          priv->phy_reset_delays,
0827                          DELAYS_NUM);
0828         if (ret)
0829             goto out_disable_clk;
0830         hisi_femac_phy_reset(priv);
0831     }
0832 
0833     phy = of_phy_get_and_connect(ndev, node, hisi_femac_adjust_link);
0834     if (!phy) {
0835         dev_err(dev, "connect to PHY failed!\n");
0836         ret = -ENODEV;
0837         goto out_disable_clk;
0838     }
0839 
0840     phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
0841                (unsigned long)phy->phy_id,
0842                phy_modes(phy->interface));
0843 
0844     ret = of_get_ethdev_address(node, ndev);
0845     if (ret) {
0846         eth_hw_addr_random(ndev);
0847         dev_warn(dev, "using random MAC address %pM\n",
0848              ndev->dev_addr);
0849     }
0850 
0851     ndev->watchdog_timeo = 6 * HZ;
0852     ndev->priv_flags |= IFF_UNICAST_FLT;
0853     ndev->netdev_ops = &hisi_femac_netdev_ops;
0854     ndev->ethtool_ops = &hisi_femac_ethtools_ops;
0855     netif_napi_add_weight(ndev, &priv->napi, hisi_femac_poll,
0856                   FEMAC_POLL_WEIGHT);
0857 
0858     hisi_femac_port_init(priv);
0859 
0860     ret = hisi_femac_init_tx_and_rx_queues(priv);
0861     if (ret)
0862         goto out_disconnect_phy;
0863 
0864     ndev->irq = platform_get_irq(pdev, 0);
0865     if (ndev->irq <= 0) {
0866         ret = -ENODEV;
0867         goto out_disconnect_phy;
0868     }
0869 
0870     ret = devm_request_irq(dev, ndev->irq, hisi_femac_interrupt,
0871                    IRQF_SHARED, pdev->name, ndev);
0872     if (ret) {
0873         dev_err(dev, "devm_request_irq %d failed!\n", ndev->irq);
0874         goto out_disconnect_phy;
0875     }
0876 
0877     ret = register_netdev(ndev);
0878     if (ret) {
0879         dev_err(dev, "register_netdev failed!\n");
0880         goto out_disconnect_phy;
0881     }
0882 
0883     return ret;
0884 
0885 out_disconnect_phy:
0886     netif_napi_del(&priv->napi);
0887     phy_disconnect(phy);
0888 out_disable_clk:
0889     clk_disable_unprepare(priv->clk);
0890 out_free_netdev:
0891     free_netdev(ndev);
0892 
0893     return ret;
0894 }
0895 
0896 static int hisi_femac_drv_remove(struct platform_device *pdev)
0897 {
0898     struct net_device *ndev = platform_get_drvdata(pdev);
0899     struct hisi_femac_priv *priv = netdev_priv(ndev);
0900 
0901     netif_napi_del(&priv->napi);
0902     unregister_netdev(ndev);
0903 
0904     phy_disconnect(ndev->phydev);
0905     clk_disable_unprepare(priv->clk);
0906     free_netdev(ndev);
0907 
0908     return 0;
0909 }
0910 
0911 #ifdef CONFIG_PM
0912 static int hisi_femac_drv_suspend(struct platform_device *pdev,
0913                   pm_message_t state)
0914 {
0915     struct net_device *ndev = platform_get_drvdata(pdev);
0916     struct hisi_femac_priv *priv = netdev_priv(ndev);
0917 
0918     disable_irq(ndev->irq);
0919     if (netif_running(ndev)) {
0920         hisi_femac_net_close(ndev);
0921         netif_device_detach(ndev);
0922     }
0923 
0924     clk_disable_unprepare(priv->clk);
0925 
0926     return 0;
0927 }
0928 
0929 static int hisi_femac_drv_resume(struct platform_device *pdev)
0930 {
0931     struct net_device *ndev = platform_get_drvdata(pdev);
0932     struct hisi_femac_priv *priv = netdev_priv(ndev);
0933 
0934     clk_prepare_enable(priv->clk);
0935     if (priv->phy_rst)
0936         hisi_femac_phy_reset(priv);
0937 
0938     if (netif_running(ndev)) {
0939         hisi_femac_port_init(priv);
0940         hisi_femac_net_open(ndev);
0941         netif_device_attach(ndev);
0942     }
0943     enable_irq(ndev->irq);
0944 
0945     return 0;
0946 }
0947 #endif
0948 
0949 static const struct of_device_id hisi_femac_match[] = {
0950     {.compatible = "hisilicon,hisi-femac-v1",},
0951     {.compatible = "hisilicon,hisi-femac-v2",},
0952     {.compatible = "hisilicon,hi3516cv300-femac",},
0953     {},
0954 };
0955 
0956 MODULE_DEVICE_TABLE(of, hisi_femac_match);
0957 
0958 static struct platform_driver hisi_femac_driver = {
0959     .driver = {
0960         .name = "hisi-femac",
0961         .of_match_table = hisi_femac_match,
0962     },
0963     .probe = hisi_femac_drv_probe,
0964     .remove = hisi_femac_drv_remove,
0965 #ifdef CONFIG_PM
0966     .suspend = hisi_femac_drv_suspend,
0967     .resume = hisi_femac_drv_resume,
0968 #endif
0969 };
0970 
0971 module_platform_driver(hisi_femac_driver);
0972 
0973 MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC driver");
0974 MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
0975 MODULE_LICENSE("GPL v2");
0976 MODULE_ALIAS("platform:hisi-femac");
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