google/gve/gve_dqo.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002  * Google virtual Ethernet (gve) driver
0003  *
0004  * Copyright (C) 2015-2021 Google, Inc.
0005  */
0006
0007 #ifndef _GVE_DQO_H_
0008 #define _GVE_DQO_H_
0009
0010 #include "gve_adminq.h"
0011
0012 #define GVE_ITR_ENABLE_BIT_DQO BIT(0)
0013 #define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1)
0014 #define GVE_ITR_NO_UPDATE_DQO (3 << 3)
0015
0016 #define GVE_ITR_INTERVAL_DQO_SHIFT 5
0017 #define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1)
0018
0019 #define GVE_TX_IRQ_RATELIMIT_US_DQO 50
0020 #define GVE_RX_IRQ_RATELIMIT_US_DQO 20
0021 #define GVE_MAX_ITR_INTERVAL_DQO (GVE_ITR_INTERVAL_DQO_MASK * 2)
0022
0023 /* Timeout in seconds to wait for a reinjection completion after receiving
0024  * its corresponding miss completion.
0025  */
0026 #define GVE_REINJECT_COMPL_TIMEOUT 1
0027
0028 /* Timeout in seconds to deallocate the completion tag for a packet that was
0029  * prematurely freed for not receiving a valid completion. This should be large
0030  * enough to rule out the possibility of receiving the corresponding valid
0031  * completion after this interval.
0032  */
0033 #define GVE_DEALLOCATE_COMPL_TIMEOUT 60
0034
0035 netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);
0036 bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);
0037 int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);
0038 int gve_tx_alloc_rings_dqo(struct gve_priv *priv);
0039 void gve_tx_free_rings_dqo(struct gve_priv *priv);
0040 int gve_rx_alloc_rings_dqo(struct gve_priv *priv);
0041 void gve_rx_free_rings_dqo(struct gve_priv *priv);
0042 int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx,
0043               struct napi_struct *napi);
0044 void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx);
0045 void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx);
0046
0047 static inline void
0048 gve_tx_put_doorbell_dqo(const struct gve_priv *priv,
0049             const struct gve_queue_resources *q_resources, u32 val)
0050 {
0051     u64 index;
0052
0053     index = be32_to_cpu(q_resources->db_index);
0054     iowrite32(val, &priv->db_bar2[index]);
0055 }
0056
0057 /* Builds register value to write to DQO IRQ doorbell to enable with specified
0058  * ITR interval.
0059  */
0060 static inline u32 gve_setup_itr_interval_dqo(u32 interval_us)
0061 {
0062     u32 result = GVE_ITR_ENABLE_BIT_DQO;
0063
0064     /* Interval has 2us granularity. */
0065     interval_us >>= 1;
0066
0067     interval_us &= GVE_ITR_INTERVAL_DQO_MASK;
0068     result |= (interval_us << GVE_ITR_INTERVAL_DQO_SHIFT);
0069
0070     return result;
0071 }
0072
0073 static inline void
0074 gve_write_irq_doorbell_dqo(const struct gve_priv *priv,
0075                const struct gve_notify_block *block, u32 val)
0076 {
0077     u32 index = be32_to_cpu(*block->irq_db_index);
0078
0079     iowrite32(val, &priv->db_bar2[index]);
0080 }
0081
0082 /* Sets interrupt throttling interval and enables interrupt
0083  * by writing to IRQ doorbell.
0084  */
0085 static inline void
0086 gve_set_itr_coalesce_usecs_dqo(struct gve_priv *priv,
0087                    struct gve_notify_block *block,
0088                    u32 usecs)
0089 {
0090     gve_write_irq_doorbell_dqo(priv, block,
0091                    gve_setup_itr_interval_dqo(usecs));
0092 }
0093 #endif /* _GVE_DQO_H_ */