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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
0004  *
0005  * Author: Shlomi Gridish <gridish@freescale.com>
0006  *
0007  * Description:
0008  * Internal header file for UCC Gigabit Ethernet unit routines.
0009  *
0010  * Changelog:
0011  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
0012  * - Rearrange code and style fixes
0013  */
0014 #ifndef __UCC_GETH_H__
0015 #define __UCC_GETH_H__
0016 
0017 #include <linux/kernel.h>
0018 #include <linux/list.h>
0019 #include <linux/if_ether.h>
0020 
0021 #include <soc/fsl/qe/immap_qe.h>
0022 #include <soc/fsl/qe/qe.h>
0023 
0024 #include <soc/fsl/qe/ucc.h>
0025 #include <soc/fsl/qe/ucc_fast.h>
0026 
0027 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
0028 #define DRV_NAME "ucc_geth"
0029 
0030 #define NUM_TX_QUEUES                   8
0031 #define NUM_RX_QUEUES                   8
0032 #define NUM_BDS_IN_PREFETCHED_BDS       4
0033 #define TX_IP_OFFSET_ENTRY_MAX          8
0034 #define NUM_OF_PADDRS                   4
0035 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
0036 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
0037 
0038 struct ucc_geth {
0039     struct ucc_fast uccf;
0040     u8 res0[0x100 - sizeof(struct ucc_fast)];
0041 
0042     u32 maccfg1;        /* mac configuration reg. 1 */
0043     u32 maccfg2;        /* mac configuration reg. 2 */
0044     u32 ipgifg;     /* interframe gap reg.  */
0045     u32 hafdup;     /* half-duplex reg.  */
0046     u8 res1[0x10];
0047     u8 miimng[0x18];    /* MII management structure moved to _mii.h */
0048     u32 ifctl;      /* interface control reg */
0049     u32 ifstat;     /* interface statux reg */
0050     u32 macstnaddr1;    /* mac station address part 1 reg */
0051     u32 macstnaddr2;    /* mac station address part 2 reg */
0052     u8 res2[0x8];
0053     u32 uempr;      /* UCC Ethernet Mac parameter reg */
0054     u32 utbipar;        /* UCC tbi address reg */
0055     u16 uescr;      /* UCC Ethernet statistics control reg */
0056     u8 res3[0x180 - 0x15A];
0057     u32 tx64;       /* Total number of frames (including bad
0058                    frames) transmitted that were exactly of the
0059                    minimal length (64 for un tagged, 68 for
0060                    tagged, or with length exactly equal to the
0061                    parameter MINLength */
0062     u32 tx127;      /* Total number of frames (including bad
0063                    frames) transmitted that were between
0064                    MINLength (Including FCS length==4) and 127
0065                    octets */
0066     u32 tx255;      /* Total number of frames (including bad
0067                    frames) transmitted that were between 128
0068                    (Including FCS length==4) and 255 octets */
0069     u32 rx64;       /* Total number of frames received including
0070                    bad frames that were exactly of the mninimal
0071                    length (64 bytes) */
0072     u32 rx127;      /* Total number of frames (including bad
0073                    frames) received that were between MINLength
0074                    (Including FCS length==4) and 127 octets */
0075     u32 rx255;      /* Total number of frames (including bad
0076                    frames) received that were between 128
0077                    (Including FCS length==4) and 255 octets */
0078     u32 txok;       /* Total number of octets residing in frames
0079                    that where involved in successful
0080                    transmission */
0081     u16 txcf;       /* Total number of PAUSE control frames
0082                    transmitted by this MAC */
0083     u8 res4[0x2];
0084     u32 tmca;       /* Total number of frames that were transmitted
0085                    successfully with the group address bit set
0086                    that are not broadcast frames */
0087     u32 tbca;       /* Total number of frames transmitted
0088                    successfully that had destination address
0089                    field equal to the broadcast address */
0090     u32 rxfok;      /* Total number of frames received OK */
0091     u32 rxbok;      /* Total number of octets received OK */
0092     u32 rbyt;       /* Total number of octets received including
0093                    octets in bad frames. Must be implemented in
0094                    HW because it includes octets in frames that
0095                    never even reach the UCC */
0096     u32 rmca;       /* Total number of frames that were received
0097                    successfully with the group address bit set
0098                    that are not broadcast frames */
0099     u32 rbca;       /* Total number of frames received successfully
0100                    that had destination address equal to the
0101                    broadcast address */
0102     u32 scar;       /* Statistics carry register */
0103     u32 scam;       /* Statistics caryy mask register */
0104     u8 res5[0x200 - 0x1c4];
0105 } __packed;
0106 
0107 /* UCC GETH TEMODR Register */
0108 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
0109                              */
0110 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
0111 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
0112                                checksums */
0113 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
0114                                optimization
0115                                enhancement (mode1) */
0116 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
0117                              */
0118 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
0119                                shift */
0120 
0121 /* UCC GETH TEMODR Register */
0122 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000  /* enable Rx
0123                                    statistics */
0124 #define REMODER_RX_EXTENDED_FEATURES            0x80000000  /* enable
0125                                    extended
0126                                    features */
0127 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
0128                                tagged << shift */
0129 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
0130                                tagged << shift */
0131 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
0132                              */
0133 #define REMODER_RMON_STATISTICS                 0x00001000  /* enable rx
0134                                    statistics */
0135 #define REMODER_RX_EXTENDED_FILTERING           0x00000800  /* extended
0136                                    filtering
0137                                    vs.
0138                                    mpc82xx-like
0139                                    filtering */
0140 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
0141                                shift */
0142 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008  /* enable
0143                                    dynamic max
0144                                    frame length
0145                                  */
0146 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004  /* enable
0147                                    dynamic min
0148                                    frame length
0149                                  */
0150 #define REMODER_IP_CHECKSUM_CHECK               0x00000002  /* check IPv4
0151                                    checksums */
0152 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001  /* align ip
0153                                    address to
0154                                    4-byte
0155                                    boundary */
0156 
0157 /* UCC GETH Event Register */
0158 #define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
0159             UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
0160             UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
0161             UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
0162 
0163 #define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
0164             UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
0165             UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
0166             UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
0167 
0168 #define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
0169             UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
0170             UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
0171             UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
0172 
0173 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
0174             UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
0175             UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
0176 
0177 #define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
0178 #define UCCE_TX_EVENTS  (UCCE_TXB | UCC_GETH_UCCE_TXE)
0179 
0180 /* TBI defines */
0181 #define ENET_TBI_MII_CR     0x00    /* Control */
0182 #define ENET_TBI_MII_SR     0x01    /* Status */
0183 #define ENET_TBI_MII_ANA    0x04    /* AN advertisement */
0184 #define ENET_TBI_MII_ANLPBPA    0x05    /* AN link partner base page ability */
0185 #define ENET_TBI_MII_ANEX   0x06    /* AN expansion */
0186 #define ENET_TBI_MII_ANNPT  0x07    /* AN next page transmit */
0187 #define ENET_TBI_MII_ANLPANP    0x08    /* AN link partner ability next page */
0188 #define ENET_TBI_MII_EXST   0x0F    /* Extended status */
0189 #define ENET_TBI_MII_JD     0x10    /* Jitter diagnostics */
0190 #define ENET_TBI_MII_TBICON 0x11    /* TBI control */
0191 
0192 /* TBI MDIO register bit fields*/
0193 #define TBISR_LSTATUS          0x0004
0194 #define TBICON_CLK_SELECT       0x0020
0195 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
0196 #define TBIANA_SYMMETRIC_PAUSE  0x0080
0197 #define TBIANA_HALF_DUPLEX      0x0040
0198 #define TBIANA_FULL_DUPLEX      0x0020
0199 #define TBICR_PHY_RESET         0x8000
0200 #define TBICR_ANEG_ENABLE       0x1000
0201 #define TBICR_RESTART_ANEG      0x0200
0202 #define TBICR_FULL_DUPLEX       0x0100
0203 #define TBICR_SPEED1_SET        0x0040
0204 
0205 #define TBIANA_SETTINGS ( \
0206         TBIANA_ASYMMETRIC_PAUSE \
0207         | TBIANA_SYMMETRIC_PAUSE \
0208         | TBIANA_FULL_DUPLEX \
0209         )
0210 #define TBICR_SETTINGS ( \
0211         TBICR_PHY_RESET \
0212         | TBICR_ANEG_ENABLE \
0213         | TBICR_FULL_DUPLEX \
0214         | TBICR_SPEED1_SET \
0215         )
0216 
0217 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
0218 #define MACCFG1_FLOW_RX                         0x00000020  /* Flow Control
0219                                    Rx */
0220 #define MACCFG1_FLOW_TX                         0x00000010  /* Flow Control
0221                                    Tx */
0222 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008  /* Rx Enable
0223                                    synchronized
0224                                    to Rx stream
0225                                  */
0226 #define MACCFG1_ENABLE_RX                       0x00000004  /* Enable Rx */
0227 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002  /* Tx Enable
0228                                    synchronized
0229                                    to Tx stream
0230                                  */
0231 #define MACCFG1_ENABLE_TX                       0x00000001  /* Enable Tx */
0232 
0233 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
0234 #define MACCFG2_PREL_SHIFT                      (31 - 19)   /* Preamble
0235                                    Length <<
0236                                    shift */
0237 #define MACCFG2_PREL_MASK                       0x0000f000  /* Preamble
0238                                    Length mask */
0239 #define MACCFG2_SRP                             0x00000080  /* Soft Receive
0240                                    Preamble */
0241 #define MACCFG2_STP                             0x00000040  /* Soft
0242                                    Transmit
0243                                    Preamble */
0244 #define MACCFG2_RESERVED_1                      0x00000020  /* Reserved -
0245                                    must be set
0246                                    to 1 */
0247 #define MACCFG2_LC                              0x00000010  /* Length Check
0248                                  */
0249 #define MACCFG2_MPE                             0x00000008  /* Magic packet
0250                                    detect */
0251 #define MACCFG2_FDX                             0x00000001  /* Full Duplex */
0252 #define MACCFG2_FDX_MASK                        0x00000001  /* Full Duplex
0253                                    mask */
0254 #define MACCFG2_PAD_CRC                         0x00000004
0255 #define MACCFG2_CRC_EN                          0x00000002
0256 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000  /* Neither
0257                                    Padding
0258                                    short frames
0259                                    nor CRC */
0260 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002  /* Append CRC
0261                                    only */
0262 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
0263 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100  /* nibble mode
0264                                    (MII/RMII/RGMII
0265                                    10/100bps) */
0266 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200  /* byte mode
0267                                    (GMII/TBI/RTB/RGMII
0268                                    1000bps ) */
0269 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300  /* mask
0270                                    covering all
0271                                    relevant
0272                                    bits */
0273 
0274 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
0275 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)   /* Non
0276                                    back-to-back
0277                                    inter frame
0278                                    gap part 1.
0279                                    << shift */
0280 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)   /* Non
0281                                    back-to-back
0282                                    inter frame
0283                                    gap part 2.
0284                                    << shift */
0285 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)   /* Mimimum IFG
0286                                    Enforcement
0287                                    << shift */
0288 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)   /* back-to-back
0289                                    inter frame
0290                                    gap << shift
0291                                  */
0292 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127 /* Non back-to-back
0293                                inter frame gap part
0294                                1. max val */
0295 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127 /* Non back-to-back
0296                                inter frame gap part
0297                                2. max val */
0298 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255 /* Mimimum IFG
0299                                Enforcement max val */
0300 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127 /* back-to-back inter
0301                                frame gap max val */
0302 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
0303 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
0304 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
0305 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
0306 
0307 /* UCC GETH HAFDUP (Half Duplex Register) */
0308 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)   /* Alternate
0309                                    Binary
0310                                    Exponential
0311                                    Backoff
0312                                    Truncation
0313                                    << shift */
0314 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf /* Alternate Binary
0315                                Exponential Backoff
0316                                Truncation max val */
0317 #define HALFDUP_ALT_BEB                         0x00080000  /* Alternate
0318                                    Binary
0319                                    Exponential
0320                                    Backoff */
0321 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000  /* Back
0322                                    pressure no
0323                                    backoff */
0324 #define HALFDUP_NO_BACKOFF                      0x00020000  /* No Backoff */
0325 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000  /* Excessive
0326                                    Defer */
0327 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)   /* Maximum
0328                                    Retransmission
0329                                    << shift */
0330 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf /* Maximum
0331                                Retransmission max
0332                                val */
0333 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)   /* Collision
0334                                    Window <<
0335                                    shift */
0336 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
0337                                val */
0338 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
0339 #define HALFDUP_RETRANS_MASK                    0x0000F000
0340 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
0341 
0342 /* UCC GETH UCCS (Ethernet Status Register) */
0343 #define UCCS_BPR                                0x02    /* Back pressure (in
0344                                half duplex mode) */
0345 #define UCCS_PAU                                0x02    /* Pause state (in full
0346                                duplex mode) */
0347 #define UCCS_MPD                                0x01    /* Magic Packet
0348                                Detected */
0349 
0350 /* UCC GETH IFSTAT (Interface Status Register) */
0351 #define IFSTAT_EXCESS_DEFER                     0x00000200  /* Excessive
0352                                    transmission
0353                                    defer */
0354 
0355 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
0356 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)   /* Station
0357                                    address 6th
0358                                    octet <<
0359                                    shift */
0360 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)   /* Station
0361                                    address 5th
0362                                    octet <<
0363                                    shift */
0364 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)   /* Station
0365                                    address 4th
0366                                    octet <<
0367                                    shift */
0368 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)   /* Station
0369                                    address 3rd
0370                                    octet <<
0371                                    shift */
0372 
0373 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
0374 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)   /* Station
0375                                    address 2nd
0376                                    octet <<
0377                                    shift */
0378 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)   /* Station
0379                                    address 1st
0380                                    octet <<
0381                                    shift */
0382 
0383 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
0384 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)   /* Pause time
0385                                    value <<
0386                                    shift */
0387 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)   /* Extended
0388                                    pause time
0389                                    value <<
0390                                    shift */
0391 
0392 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
0393 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)   /* Phy address
0394                                    << shift */
0395 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f  /* Phy address
0396                                    mask */
0397 
0398 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
0399 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
0400                                addressed
0401                                statistical counter
0402                                values */
0403 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
0404                                counters */
0405 #define UESCR_MAXCOV_SHIFT                      (15 -  7)   /* Max
0406                                    Coalescing
0407                                    Value <<
0408                                    shift */
0409 #define UESCR_SCOV_SHIFT                        (15 - 15)   /* Status
0410                                    Coalescing
0411                                    Value <<
0412                                    shift */
0413 
0414 /* UCC GETH UDSR (Data Synchronization Register) */
0415 #define UDSR_MAGIC                              0x067E
0416 
0417 struct ucc_geth_thread_data_tx {
0418     u8 res0[104];
0419 } __packed;
0420 
0421 struct ucc_geth_thread_data_rx {
0422     u8 res0[40];
0423 } __packed;
0424 
0425 /* Send Queue Queue-Descriptor */
0426 struct ucc_geth_send_queue_qd {
0427     u32 bd_ring_base;   /* pointer to BD ring base address */
0428     u8 res0[0x8];
0429     u32 last_bd_completed_address;/* initialize to last entry in BD ring */
0430     u8 res1[0x30];
0431 } __packed;
0432 
0433 struct ucc_geth_send_queue_mem_region {
0434     struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
0435 } __packed;
0436 
0437 struct ucc_geth_thread_tx_pram {
0438     u8 res0[64];
0439 } __packed;
0440 
0441 struct ucc_geth_thread_rx_pram {
0442     u8 res0[128];
0443 } __packed;
0444 
0445 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
0446 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
0447 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
0448 
0449 struct ucc_geth_scheduler {
0450     u16 cpucount0;      /* CPU packet counter */
0451     u16 cpucount1;      /* CPU packet counter */
0452     u16 cecount0;       /* QE packet counter */
0453     u16 cecount1;       /* QE packet counter */
0454     u16 cpucount2;      /* CPU packet counter */
0455     u16 cpucount3;      /* CPU packet counter */
0456     u16 cecount2;       /* QE packet counter */
0457     u16 cecount3;       /* QE packet counter */
0458     u16 cpucount4;      /* CPU packet counter */
0459     u16 cpucount5;      /* CPU packet counter */
0460     u16 cecount4;       /* QE packet counter */
0461     u16 cecount5;       /* QE packet counter */
0462     u16 cpucount6;      /* CPU packet counter */
0463     u16 cpucount7;      /* CPU packet counter */
0464     u16 cecount6;       /* QE packet counter */
0465     u16 cecount7;       /* QE packet counter */
0466     u32 weightstatus[NUM_TX_QUEUES];    /* accumulated weight factor */
0467     u32 rtsrshadow;     /* temporary variable handled by QE */
0468     u32 time;       /* temporary variable handled by QE */
0469     u32 ttl;        /* temporary variable handled by QE */
0470     u32 mblinterval;    /* max burst length interval */
0471     u16 nortsrbytetime; /* normalized value of byte time in tsr units */
0472     u8 fracsiz;     /* radix 2 log value of denom. of
0473                    NorTSRByteTime */
0474     u8 res0[1];
0475     u8 strictpriorityq; /* Strict Priority Mask register */
0476     u8 txasap;      /* Transmit ASAP register */
0477     u8 extrabw;     /* Extra BandWidth register */
0478     u8 oldwfqmask;      /* temporary variable handled by QE */
0479     u8 weightfactor[NUM_TX_QUEUES];
0480                       /**< weight factor for queues   */
0481     u32 minw;       /* temporary variable handled by QE */
0482     u8 res1[0x70 - 0x64];
0483 } __packed;
0484 
0485 struct ucc_geth_tx_firmware_statistics_pram {
0486     u32 sicoltx;        /* single collision */
0487     u32 mulcoltx;       /* multiple collision */
0488     u32 latecoltxfr;    /* late collision */
0489     u32 frabortduecol;  /* frames aborted due to transmit collision */
0490     u32 frlostinmactxer;    /* frames lost due to internal MAC error
0491                    transmission that are not counted on any
0492                    other counter */
0493     u32 carriersenseertx;   /* carrier sense error */
0494     u32 frtxok;     /* frames transmitted OK */
0495     u32 txfrexcessivedefer; /* frames with defferal time greater than
0496                    specified threshold */
0497     u32 txpkts256;      /* total packets (including bad) between 256
0498                    and 511 octets */
0499     u32 txpkts512;      /* total packets (including bad) between 512
0500                    and 1023 octets */
0501     u32 txpkts1024;     /* total packets (including bad) between 1024
0502                    and 1518 octets */
0503     u32 txpktsjumbo;    /* total packets (including bad) between 1024
0504                    and MAXLength octets */
0505 } __packed;
0506 
0507 struct ucc_geth_rx_firmware_statistics_pram {
0508     u32 frrxfcser;      /* frames with crc error */
0509     u32 fraligner;      /* frames with alignment error */
0510     u32 inrangelenrxer; /* in range length error */
0511     u32 outrangelenrxer;    /* out of range length error */
0512     u32 frtoolong;      /* frame too long */
0513     u32 runt;       /* runt */
0514     u32 verylongevent;  /* very long event */
0515     u32 symbolerror;    /* symbol error */
0516     u32 dropbsy;        /* drop because of BD not ready */
0517     u8 res0[0x8];
0518     u32 mismatchdrop;   /* drop because of MAC filtering (e.g. address
0519                    or type mismatch) */
0520     u32 underpkts;      /* total frames less than 64 octets */
0521     u32 pkts256;        /* total frames (including bad) between 256 and
0522                    511 octets */
0523     u32 pkts512;        /* total frames (including bad) between 512 and
0524                    1023 octets */
0525     u32 pkts1024;       /* total frames (including bad) between 1024
0526                    and 1518 octets */
0527     u32 pktsjumbo;      /* total frames (including bad) between 1024
0528                    and MAXLength octets */
0529     u32 frlossinmacer;  /* frames lost because of internal MAC error
0530                    that is not counted in any other counter */
0531     u32 pausefr;        /* pause frames */
0532     u8 res1[0x4];
0533     u32 removevlan;     /* total frames that had their VLAN tag removed
0534                  */
0535     u32 replacevlan;    /* total frames that had their VLAN tag
0536                    replaced */
0537     u32 insertvlan;     /* total frames that had their VLAN tag
0538                    inserted */
0539 } __packed;
0540 
0541 struct ucc_geth_rx_interrupt_coalescing_entry {
0542     u32 interruptcoalescingmaxvalue;    /* interrupt coalescing max
0543                            value */
0544     u32 interruptcoalescingcounter; /* interrupt coalescing counter,
0545                        initialize to
0546                        interruptcoalescingmaxvalue */
0547 } __packed;
0548 
0549 struct ucc_geth_rx_interrupt_coalescing_table {
0550     struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
0551                        /**< interrupt coalescing entry */
0552 } __packed;
0553 
0554 struct ucc_geth_rx_prefetched_bds {
0555     struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
0556 } __packed;
0557 
0558 struct ucc_geth_rx_bd_queues_entry {
0559     u32 bdbaseptr;      /* BD base pointer */
0560     u32 bdptr;      /* BD pointer */
0561     u32 externalbdbaseptr;  /* external BD base pointer */
0562     u32 externalbdptr;  /* external BD pointer */
0563 } __packed;
0564 
0565 struct ucc_geth_tx_global_pram {
0566     u16 temoder;
0567     u8 res0[0x38 - 0x02];
0568     u32 sqptr;      /* a base pointer to send queue memory region */
0569     u32 schedulerbasepointer;   /* a base pointer to scheduler memory
0570                        region */
0571     u32 txrmonbaseptr;  /* base pointer to Tx RMON statistics counter */
0572     u32 tstate;     /* tx internal state. High byte contains
0573                    function code */
0574     u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
0575     u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
0576     u32 tqptr;      /* a base pointer to the Tx Queues Memory
0577                    Region */
0578     u8 res2[0x78 - 0x74];
0579     u64 snums_en;
0580     u32 l2l3baseptr;    /* top byte consists of a few other bit fields */
0581 
0582     u16 mtu[8];
0583     u8 res3[0xa8 - 0x94];
0584     u32 wrrtablebase;   /* top byte is reserved */
0585     u8 res4[0xc0 - 0xac];
0586 } __packed;
0587 
0588 /* structure representing Extended Filtering Global Parameters in PRAM */
0589 struct ucc_geth_exf_global_pram {
0590     u32 l2pcdptr;       /* individual address filter, high */
0591     u8 res0[0x10 - 0x04];
0592 } __packed;
0593 
0594 struct ucc_geth_rx_global_pram {
0595     u32 remoder;        /* ethernet mode reg. */
0596     u32 rqptr;      /* base pointer to the Rx Queues Memory Region*/
0597     u32 res0[0x1];
0598     u8 res1[0x20 - 0xC];
0599     u16 typeorlen;      /* cutoff point less than which, type/len field
0600                    is considered length */
0601     u8 res2[0x1];
0602     u8 rxgstpack;       /* acknowledgement on GRACEFUL STOP RX command*/
0603     u32 rxrmonbaseptr;  /* base pointer to Rx RMON statistics counter */
0604     u8 res3[0x30 - 0x28];
0605     u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
0606     u8 res4[0x36 - 0x34];
0607     u8 rstate;      /* rx internal state. High byte contains
0608                    function code */
0609     u8 res5[0x46 - 0x37];
0610     u16 mrblr;      /* max receive buffer length reg. */
0611     u32 rbdqptr;        /* base pointer to RxBD parameter table
0612                    description */
0613     u16 mflr;       /* max frame length reg. */
0614     u16 minflr;     /* min frame length reg. */
0615     u16 maxd1;      /* max dma1 length reg. */
0616     u16 maxd2;      /* max dma2 length reg. */
0617     u32 ecamptr;        /* external CAM address */
0618     u32 l2qt;       /* VLAN priority mapping table. */
0619     u32 l3qt[0x8];      /* IP priority mapping table. */
0620     u16 vlantype;       /* vlan type */
0621     u16 vlantci;        /* default vlan tci */
0622     u8 addressfiltering[64];    /* address filtering data structure */
0623     u32 exfGlobalParam; /* base address for extended filtering global
0624                    parameters */
0625     u8 res6[0x100 - 0xC4];  /* Initialize to zero */
0626 } __packed;
0627 
0628 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
0629 
0630 /* structure representing InitEnet command */
0631 struct ucc_geth_init_pram {
0632     u8 resinit1;
0633     u8 resinit2;
0634     u8 resinit3;
0635     u8 resinit4;
0636     u16 resinit5;
0637     u8 res1[0x1];
0638     u8 largestexternallookupkeysize;
0639     u32 rgftgfrxglobal;
0640     u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
0641     u8 res2[0x38 - 0x30];
0642     u32 txglobal;       /* tx global */
0643     u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
0644     u8 res3[0x1];
0645 } __packed;
0646 
0647 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
0648 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
0649 
0650 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
0651 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
0652 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
0653 #define ENET_INIT_PARAM_SNUM_SHIFT              24
0654 
0655 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
0656 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
0657 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
0658 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
0659 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
0660 
0661 /* structure representing 82xx Address Filtering Enet Address in PRAM */
0662 struct ucc_geth_82xx_enet_address {
0663     u8 res1[0x2];
0664     u16 h;          /* address (MSB) */
0665     u16 m;          /* address */
0666     u16 l;          /* address (LSB) */
0667 } __packed;
0668 
0669 /* structure representing 82xx Address Filtering PRAM */
0670 struct ucc_geth_82xx_address_filtering_pram {
0671     u32 iaddr_h;        /* individual address filter, high */
0672     u32 iaddr_l;        /* individual address filter, low */
0673     u32 gaddr_h;        /* group address filter, high */
0674     u32 gaddr_l;        /* group address filter, low */
0675     struct ucc_geth_82xx_enet_address __iomem taddr;
0676     struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
0677     u8 res0[0x40 - 0x38];
0678 } __packed;
0679 
0680 /* GETH Tx firmware statistics structure, used when calling
0681    UCC_GETH_GetStatistics. */
0682 struct ucc_geth_tx_firmware_statistics {
0683     u32 sicoltx;        /* single collision */
0684     u32 mulcoltx;       /* multiple collision */
0685     u32 latecoltxfr;    /* late collision */
0686     u32 frabortduecol;  /* frames aborted due to transmit collision */
0687     u32 frlostinmactxer;    /* frames lost due to internal MAC error
0688                    transmission that are not counted on any
0689                    other counter */
0690     u32 carriersenseertx;   /* carrier sense error */
0691     u32 frtxok;     /* frames transmitted OK */
0692     u32 txfrexcessivedefer; /* frames with defferal time greater than
0693                    specified threshold */
0694     u32 txpkts256;      /* total packets (including bad) between 256
0695                    and 511 octets */
0696     u32 txpkts512;      /* total packets (including bad) between 512
0697                    and 1023 octets */
0698     u32 txpkts1024;     /* total packets (including bad) between 1024
0699                    and 1518 octets */
0700     u32 txpktsjumbo;    /* total packets (including bad) between 1024
0701                    and MAXLength octets */
0702 } __packed;
0703 
0704 /* GETH Rx firmware statistics structure, used when calling
0705    UCC_GETH_GetStatistics. */
0706 struct ucc_geth_rx_firmware_statistics {
0707     u32 frrxfcser;      /* frames with crc error */
0708     u32 fraligner;      /* frames with alignment error */
0709     u32 inrangelenrxer; /* in range length error */
0710     u32 outrangelenrxer;    /* out of range length error */
0711     u32 frtoolong;      /* frame too long */
0712     u32 runt;       /* runt */
0713     u32 verylongevent;  /* very long event */
0714     u32 symbolerror;    /* symbol error */
0715     u32 dropbsy;        /* drop because of BD not ready */
0716     u8 res0[0x8];
0717     u32 mismatchdrop;   /* drop because of MAC filtering (e.g. address
0718                    or type mismatch) */
0719     u32 underpkts;      /* total frames less than 64 octets */
0720     u32 pkts256;        /* total frames (including bad) between 256 and
0721                    511 octets */
0722     u32 pkts512;        /* total frames (including bad) between 512 and
0723                    1023 octets */
0724     u32 pkts1024;       /* total frames (including bad) between 1024
0725                    and 1518 octets */
0726     u32 pktsjumbo;      /* total frames (including bad) between 1024
0727                    and MAXLength octets */
0728     u32 frlossinmacer;  /* frames lost because of internal MAC error
0729                    that is not counted in any other counter */
0730     u32 pausefr;        /* pause frames */
0731     u8 res1[0x4];
0732     u32 removevlan;     /* total frames that had their VLAN tag removed
0733                  */
0734     u32 replacevlan;    /* total frames that had their VLAN tag
0735                    replaced */
0736     u32 insertvlan;     /* total frames that had their VLAN tag
0737                    inserted */
0738 } __packed;
0739 
0740 /* GETH hardware statistics structure, used when calling
0741    UCC_GETH_GetStatistics. */
0742 struct ucc_geth_hardware_statistics {
0743     u32 tx64;       /* Total number of frames (including bad
0744                    frames) transmitted that were exactly of the
0745                    minimal length (64 for un tagged, 68 for
0746                    tagged, or with length exactly equal to the
0747                    parameter MINLength */
0748     u32 tx127;      /* Total number of frames (including bad
0749                    frames) transmitted that were between
0750                    MINLength (Including FCS length==4) and 127
0751                    octets */
0752     u32 tx255;      /* Total number of frames (including bad
0753                    frames) transmitted that were between 128
0754                    (Including FCS length==4) and 255 octets */
0755     u32 rx64;       /* Total number of frames received including
0756                    bad frames that were exactly of the mninimal
0757                    length (64 bytes) */
0758     u32 rx127;      /* Total number of frames (including bad
0759                    frames) received that were between MINLength
0760                    (Including FCS length==4) and 127 octets */
0761     u32 rx255;      /* Total number of frames (including bad
0762                    frames) received that were between 128
0763                    (Including FCS length==4) and 255 octets */
0764     u32 txok;       /* Total number of octets residing in frames
0765                    that where involved in successful
0766                    transmission */
0767     u16 txcf;       /* Total number of PAUSE control frames
0768                    transmitted by this MAC */
0769     u32 tmca;       /* Total number of frames that were transmitted
0770                    successfully with the group address bit set
0771                    that are not broadcast frames */
0772     u32 tbca;       /* Total number of frames transmitted
0773                    successfully that had destination address
0774                    field equal to the broadcast address */
0775     u32 rxfok;      /* Total number of frames received OK */
0776     u32 rxbok;      /* Total number of octets received OK */
0777     u32 rbyt;       /* Total number of octets received including
0778                    octets in bad frames. Must be implemented in
0779                    HW because it includes octets in frames that
0780                    never even reach the UCC */
0781     u32 rmca;       /* Total number of frames that were received
0782                    successfully with the group address bit set
0783                    that are not broadcast frames */
0784     u32 rbca;       /* Total number of frames received successfully
0785                    that had destination address equal to the
0786                    broadcast address */
0787 } __packed;
0788 
0789 /* UCC GETH Tx errors returned via TxConf callback */
0790 #define TX_ERRORS_DEF      0x0200
0791 #define TX_ERRORS_EXDEF    0x0100
0792 #define TX_ERRORS_LC       0x0080
0793 #define TX_ERRORS_RL       0x0040
0794 #define TX_ERRORS_RC_MASK  0x003C
0795 #define TX_ERRORS_RC_SHIFT 2
0796 #define TX_ERRORS_UN       0x0002
0797 #define TX_ERRORS_CSL      0x0001
0798 
0799 /* UCC GETH Rx errors returned via RxStore callback */
0800 #define RX_ERRORS_CMR      0x0200
0801 #define RX_ERRORS_M        0x0100
0802 #define RX_ERRORS_BC       0x0080
0803 #define RX_ERRORS_MC       0x0040
0804 
0805 /* Transmit BD. These are in addition to values defined in uccf. */
0806 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
0807 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
0808 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
0809 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
0810 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
0811 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
0812 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
0813 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
0814 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
0815         | T_UN | T_CSL) /* transmit errors to report */
0816 
0817 /* Receive BD. These are in addition to values defined in uccf. */
0818 #define R_LG    0x00200000  /* Frame length violation.  */
0819 #define R_NO    0x00100000  /* Non-octet aligned frame.  */
0820 #define R_SH    0x00080000  /* Short frame.  */
0821 #define R_CR    0x00040000  /* CRC error.  */
0822 #define R_OV    0x00020000  /* Overrun.  */
0823 #define R_IPCH  0x00010000  /* IP checksum check failed. */
0824 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
0825 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
0826 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
0827 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
0828 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to
0829                                report */
0830 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
0831         R_OV | R_IPCH)  /* receive errors to discard */
0832 
0833 /* Alignments */
0834 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT   256
0835 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
0836 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
0837 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
0838 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256 /* spec gives values
0839                                based on num of
0840                                threads, but always
0841                                using the maximum is
0842                                easier */
0843 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
0844 #define UCC_GETH_SCHEDULER_ALIGNMENT        8   /* This is a guess */
0845 #define UCC_GETH_TX_STATISTICS_ALIGNMENT    4   /* This is a guess */
0846 #define UCC_GETH_RX_STATISTICS_ALIGNMENT    4   /* This is a guess */
0847 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT  64
0848 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT     8   /* This is a guess */
0849 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128 /* This is a guess */
0850 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8    /* This
0851                                        is a
0852                                        guess
0853                                      */
0854 #define UCC_GETH_RX_BD_RING_ALIGNMENT       32
0855 #define UCC_GETH_TX_BD_RING_ALIGNMENT       32
0856 #define UCC_GETH_MRBLR_ALIGNMENT        128
0857 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT  4
0858 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT   32
0859 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT      64
0860 
0861 #define UCC_GETH_TAD_EF                         0x80
0862 #define UCC_GETH_TAD_V                          0x40
0863 #define UCC_GETH_TAD_REJ                        0x20
0864 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
0865 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
0866 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
0867 #define UCC_GETH_TAD_RQOS_SHIFT                 0
0868 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
0869 #define UCC_GETH_TAD_CFI                        0x10
0870 
0871 #define UCC_GETH_VLAN_PRIORITY_MAX              8
0872 #define UCC_GETH_IP_PRIORITY_MAX                64
0873 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
0874 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
0875 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
0876 #define UCC_GETH_BD_RING_SIZE_MAX       0xffff
0877 
0878 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
0879 
0880 /* Driver definitions */
0881 #define TX_BD_RING_LEN                          0x10
0882 #define RX_BD_RING_LEN                          0x20
0883 
0884 #define TX_RING_MOD_MASK(size)                  (size-1)
0885 #define RX_RING_MOD_MASK(size)                  (size-1)
0886 
0887 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
0888                                for ethernet
0889                                addresses */
0890 
0891 #define TX_TIMEOUT                              (1*HZ)
0892 #define PHY_INIT_TIMEOUT                        100000
0893 #define PHY_CHANGE_TIME                         2
0894 
0895 /* Fast Ethernet (10/100 Mbps) */
0896 #define UCC_GETH_URFS_INIT                      512 /* Rx virtual FIFO size
0897                              */
0898 #define UCC_GETH_URFET_INIT                     256 /* 1/2 urfs */
0899 #define UCC_GETH_URFSET_INIT                    384 /* 3/4 urfs */
0900 #define UCC_GETH_UTFS_INIT                      512 /* Tx virtual FIFO size
0901                              */
0902 #define UCC_GETH_UTFET_INIT                     256 /* 1/2 utfs */
0903 #define UCC_GETH_UTFTT_INIT                     256 /* 1/2 utfs
0904                                due to errata */
0905 /* Gigabit Ethernet (1000 Mbps) */
0906 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
0907                                    FIFO size */
0908 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
0909 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
0910 #define UCC_GETH_UTFS_GIGA_INIT                 4096/*2048*/    /* Tx virtual
0911                                    FIFO size */
0912 #define UCC_GETH_UTFET_GIGA_INIT                2048/*1024*/    /* 1/2 utfs */
0913 #define UCC_GETH_UTFTT_GIGA_INIT                4096/*0x40*/    /* Tx virtual
0914                                    FIFO size */
0915 
0916 #define UCC_GETH_REMODER_INIT                   0   /* bits that must be
0917                                set */
0918 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
0919 
0920 /* Initial value for UPSMR */
0921 #define UCC_GETH_UPSMR_INIT                     UCC_GETH_UPSMR_RES1
0922 
0923 #define UCC_GETH_MACCFG1_INIT                   0
0924 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
0925 
0926 /* Ethernet Address Type. */
0927 enum enet_addr_type {
0928     ENET_ADDR_TYPE_INDIVIDUAL,
0929     ENET_ADDR_TYPE_GROUP,
0930     ENET_ADDR_TYPE_BROADCAST
0931 };
0932 
0933 /* UCC GETH 82xx Ethernet Address Recognition Location */
0934 enum ucc_geth_enet_address_recognition_location {
0935     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
0936                                       address */
0937     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
0938                                    station
0939                                    address
0940                                    paddr1 */
0941     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,  /* additional
0942                                    station
0943                                    address
0944                                    paddr2 */
0945     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,  /* additional
0946                                    station
0947                                    address
0948                                    paddr3 */
0949     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
0950                                    station
0951                                    address
0952                                    paddr4 */
0953     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
0954     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
0955                                       hash */
0956 };
0957 
0958 /* UCC GETH vlan operation tagged */
0959 enum ucc_geth_vlan_operation_tagged {
0960     UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,   /* Tagged - nop */
0961     UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
0962         = 0x1,  /* Tagged - replace vid portion of q tag */
0963     UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
0964         = 0x2,  /* Tagged - if vid0 replace vid with default value  */
0965     UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
0966         = 0x3   /* Tagged - extract q tag from frame */
0967 };
0968 
0969 /* UCC GETH vlan operation non-tagged */
0970 enum ucc_geth_vlan_operation_non_tagged {
0971     UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
0972     UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
0973                                    q tag insert
0974                                  */
0975 };
0976 
0977 /* UCC GETH Rx Quality of Service Mode */
0978 enum ucc_geth_qos_mode {
0979     UCC_GETH_QOS_MODE_DEFAULT = 0x0,    /* default queue */
0980     UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue
0981                                    determined
0982                                    by L2
0983                                    criteria */
0984     UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2  /* queue
0985                                    determined
0986                                    by L3
0987                                    criteria */
0988 };
0989 
0990 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
0991    for combined functionality */
0992 enum ucc_geth_statistics_gathering_mode {
0993     UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
0994                                    statistics
0995                                    gathering */
0996     UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
0997                                     hardware
0998                                     statistics
0999                                     gathering
1000                                   */
1001     UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1002                                       firmware
1003                                       tx
1004                                       statistics
1005                                       gathering
1006                                      */
1007     UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1008                                       firmware
1009                                       rx
1010                                       statistics
1011                                       gathering
1012                                     */
1013 };
1014 
1015 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1016 enum ucc_geth_maccfg2_pad_and_crc_mode {
1017     UCC_GETH_PAD_AND_CRC_MODE_NONE
1018         = MACCFG2_PAD_AND_CRC_MODE_NONE,    /* Neither Padding
1019                                short frames
1020                                nor CRC */
1021     UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1022         = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
1023                                CRC only */
1024     UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1025         MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1026 };
1027 
1028 /* UCC GETH upsmr Flow Control Mode */
1029 enum ucc_geth_flow_control_mode {
1030     UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
1031                                    flow control
1032                                  */
1033     UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1034         = 0x00004000    /* Send pause frame when RxFIFO reaches its
1035                    emergency threshold */
1036 };
1037 
1038 /* UCC GETH number of threads */
1039 enum ucc_geth_num_of_threads {
1040     UCC_GETH_NUM_OF_THREADS_1 = 0x1,    /* 1 */
1041     UCC_GETH_NUM_OF_THREADS_2 = 0x2,    /* 2 */
1042     UCC_GETH_NUM_OF_THREADS_4 = 0x0,    /* 4 */
1043     UCC_GETH_NUM_OF_THREADS_6 = 0x3,    /* 6 */
1044     UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1045 };
1046 
1047 /* UCC GETH number of station addresses */
1048 enum ucc_geth_num_of_station_addresses {
1049     UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1050     UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */
1051 };
1052 
1053 /* UCC GETH 82xx Ethernet Address Container */
1054 struct enet_addr_container {
1055     u8 address[ETH_ALEN];   /* ethernet address */
1056     enum ucc_geth_enet_address_recognition_location location;   /* location in
1057                                    82xx address
1058                                    recognition
1059                                    hardware */
1060     struct list_head node;
1061 };
1062 
1063 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1064 
1065 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1066 struct ucc_geth_tad_params {
1067     int rx_non_dynamic_extended_features_mode;
1068     int reject_frame;
1069     enum ucc_geth_vlan_operation_tagged vtag_op;
1070     enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1071     enum ucc_geth_qos_mode rqos;
1072     u8 vpri;
1073     u16 vid;
1074 };
1075 
1076 /* GETH protocol initialization structure */
1077 struct ucc_geth_info {
1078     struct ucc_fast_info uf_info;
1079     int ipCheckSumCheck;
1080     int ipCheckSumGenerate;
1081     int rxExtendedFiltering;
1082     u32 extendedFilteringChainPointer;
1083     u16 typeorlen;
1084     int dynamicMaxFrameLength;
1085     int dynamicMinFrameLength;
1086     u8 nonBackToBackIfgPart1;
1087     u8 nonBackToBackIfgPart2;
1088     u8 miminumInterFrameGapEnforcement;
1089     u8 backToBackInterFrameGap;
1090     int ipAddressAlignment;
1091     int lengthCheckRx;
1092     u32 mblinterval;
1093     u16 nortsrbytetime;
1094     u8 fracsiz;
1095     u8 strictpriorityq;
1096     u8 txasap;
1097     u8 extrabw;
1098     int miiPreambleSupress;
1099     u8 altBebTruncation;
1100     int altBeb;
1101     int backPressureNoBackoff;
1102     int noBackoff;
1103     int excessDefer;
1104     u8 maxRetransmission;
1105     u8 collisionWindow;
1106     int pro;
1107     int cap;
1108     int rsh;
1109     int rlpb;
1110     int cam;
1111     int bro;
1112     int ecm;
1113     int receiveFlowControl;
1114     int transmitFlowControl;
1115     u8 maxGroupAddrInHash;
1116     u8 maxIndAddrInHash;
1117     u8 prel;
1118     u16 maxFrameLength;
1119     u16 minFrameLength;
1120     u16 maxD1Length;
1121     u16 maxD2Length;
1122     u16 vlantype;
1123     u16 vlantci;
1124     u32 ecamptr;
1125     u32 eventRegMask;
1126     u16 pausePeriod;
1127     u16 extensionField;
1128     struct device_node *phy_node;
1129     struct device_node *tbi_node;
1130     u8 weightfactor[NUM_TX_QUEUES];
1131     u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1132     u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1133     u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1134     u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1135     u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1136     u16 bdRingLenTx[NUM_TX_QUEUES];
1137     u16 bdRingLenRx[NUM_RX_QUEUES];
1138     enum ucc_geth_num_of_station_addresses numStationAddresses;
1139     enum qe_fltr_largest_external_tbl_lookup_key_size
1140         largestexternallookupkeysize;
1141     enum ucc_geth_statistics_gathering_mode statisticsMode;
1142     enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1143     enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1144     enum ucc_geth_qos_mode rxQoSMode;
1145     enum ucc_geth_flow_control_mode aufc;
1146     enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1147     enum ucc_geth_num_of_threads numThreadsTx;
1148     enum ucc_geth_num_of_threads numThreadsRx;
1149     unsigned int riscTx;
1150     unsigned int riscRx;
1151 };
1152 
1153 /* structure representing UCC GETH */
1154 struct ucc_geth_private {
1155     struct ucc_geth_info *ug_info;
1156     struct ucc_fast_private *uccf;
1157     struct device *dev;
1158     struct net_device *ndev;
1159     struct napi_struct napi;
1160     struct work_struct timeout_work;
1161     struct ucc_geth __iomem *ug_regs;
1162     struct ucc_geth_init_pram *p_init_enet_param_shadow;
1163     struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1164     u32 exf_glbl_param_offset;
1165     struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1166     struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1167     struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1168     u32 send_q_mem_reg_offset;
1169     struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1170     u32 thread_dat_tx_offset;
1171     struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1172     u32 thread_dat_rx_offset;
1173     struct ucc_geth_scheduler __iomem *p_scheduler;
1174     u32 scheduler_offset;
1175     struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1176     u32 tx_fw_statistics_pram_offset;
1177     struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1178     u32 rx_fw_statistics_pram_offset;
1179     struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1180     u32 rx_irq_coalescing_tbl_offset;
1181     struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1182     u32 rx_bd_qs_tbl_offset;
1183     u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1184     u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1185     u8 __iomem *confBd[NUM_TX_QUEUES];
1186     u8 __iomem *txBd[NUM_TX_QUEUES];
1187     u8 __iomem *rxBd[NUM_RX_QUEUES];
1188     int badFrame[NUM_RX_QUEUES];
1189     u16 cpucount[NUM_TX_QUEUES];
1190     u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1191     int indAddrRegUsed[NUM_OF_PADDRS];
1192     u8 paddr[NUM_OF_PADDRS][ETH_ALEN];  /* ethernet address */
1193     u8 numGroupAddrInHash;
1194     u8 numIndAddrInHash;
1195     u8 numIndAddrInReg;
1196     int rx_extended_features;
1197     int rx_non_dynamic_extended_features;
1198     struct list_head conf_skbs;
1199     struct list_head group_hash_q;
1200     struct list_head ind_hash_q;
1201     u32 saved_uccm;
1202     spinlock_t lock;
1203     /* pointers to arrays of skbuffs for tx and rx */
1204     struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1205     struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1206     /* indices pointing to the next free sbk in skb arrays */
1207     u16 skb_curtx[NUM_TX_QUEUES];
1208     u16 skb_currx[NUM_RX_QUEUES];
1209     /* index of the first skb which hasn't been transmitted yet. */
1210     u16 skb_dirtytx[NUM_TX_QUEUES];
1211 
1212     struct ugeth_mii_info *mii_info;
1213     struct phy_device *phydev;
1214     phy_interface_t phy_interface;
1215     int max_speed;
1216     uint32_t msg_enable;
1217     int oldspeed;
1218     int oldduplex;
1219     int oldlink;
1220     int wol_en;
1221 
1222     struct device_node *node;
1223 };
1224 
1225 void uec_set_ethtool_ops(struct net_device *netdev);
1226 int init_flow_control_params(u32 automatic_flow_control_mode,
1227         int rx_flow_control_enable, int tx_flow_control_enable,
1228         u16 pause_period, u16 extension_field,
1229         u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1230         u32 __iomem *maccfg1_register);
1231 
1232 
1233 #endif              /* __UCC_GETH_H__ */
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