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0001 /*
0002  * FCC driver for Motorola MPC82xx (PQ2).
0003  *
0004  * Copyright (c) 2003 Intracom S.A.
0005  *  by Pantelis Antoniou <panto@intracom.gr>
0006  *
0007  * 2005 (c) MontaVista Software, Inc.
0008  * Vitaly Bordug <vbordug@ru.mvista.com>
0009  *
0010  * This file is licensed under the terms of the GNU General Public License
0011  * version 2. This program is licensed "as is" without any warranty of any
0012  * kind, whether express or implied.
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/kernel.h>
0017 #include <linux/types.h>
0018 #include <linux/string.h>
0019 #include <linux/ptrace.h>
0020 #include <linux/errno.h>
0021 #include <linux/ioport.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/delay.h>
0024 #include <linux/netdevice.h>
0025 #include <linux/etherdevice.h>
0026 #include <linux/skbuff.h>
0027 #include <linux/spinlock.h>
0028 #include <linux/mii.h>
0029 #include <linux/ethtool.h>
0030 #include <linux/bitops.h>
0031 #include <linux/fs.h>
0032 #include <linux/platform_device.h>
0033 #include <linux/phy.h>
0034 #include <linux/of_address.h>
0035 #include <linux/of_device.h>
0036 #include <linux/of_irq.h>
0037 #include <linux/gfp.h>
0038 #include <linux/pgtable.h>
0039 
0040 #include <asm/immap_cpm2.h>
0041 #include <asm/mpc8260.h>
0042 #include <asm/cpm2.h>
0043 
0044 #include <asm/irq.h>
0045 #include <linux/uaccess.h>
0046 
0047 #include "fs_enet.h"
0048 
0049 /*************************************************/
0050 
0051 /* FCC access macros */
0052 
0053 /* write, read, set bits, clear bits */
0054 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v))
0055 #define R32(_p, _m) in_be32(&(_p)->_m)
0056 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
0057 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
0058 
0059 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v))
0060 #define R16(_p, _m) in_be16(&(_p)->_m)
0061 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
0062 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
0063 
0064 #define W8(_p, _m, _v)  out_8(&(_p)->_m, (_v))
0065 #define R8(_p, _m)  in_8(&(_p)->_m)
0066 #define S8(_p, _m, _v)  W8(_p, _m, R8(_p, _m) | (_v))
0067 #define C8(_p, _m, _v)  W8(_p, _m, R8(_p, _m) & ~(_v))
0068 
0069 /*************************************************/
0070 
0071 #define FCC_MAX_MULTICAST_ADDRS 64
0072 
0073 #define mk_mii_read(REG)    (0x60020000 | ((REG & 0x1f) << 18))
0074 #define mk_mii_write(REG, VAL)  (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
0075 #define mk_mii_end      0
0076 
0077 #define MAX_CR_CMD_LOOPS    10000
0078 
0079 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op)
0080 {
0081     const struct fs_platform_info *fpi = fep->fpi;
0082 
0083     return cpm_command(fpi->cp_command, op);
0084 }
0085 
0086 static int do_pd_setup(struct fs_enet_private *fep)
0087 {
0088     struct platform_device *ofdev = to_platform_device(fep->dev);
0089     struct fs_platform_info *fpi = fep->fpi;
0090     int ret = -EINVAL;
0091 
0092     fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0);
0093     if (!fep->interrupt)
0094         goto out;
0095 
0096     fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0);
0097     if (!fep->fcc.fccp)
0098         goto out;
0099 
0100     fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1);
0101     if (!fep->fcc.ep)
0102         goto out_fccp;
0103 
0104     fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2);
0105     if (!fep->fcc.fcccp)
0106         goto out_ep;
0107 
0108     fep->fcc.mem = (void __iomem *)cpm2_immr;
0109     fpi->dpram_offset = cpm_dpalloc(128, 32);
0110     if (IS_ERR_VALUE(fpi->dpram_offset)) {
0111         ret = fpi->dpram_offset;
0112         goto out_fcccp;
0113     }
0114 
0115     return 0;
0116 
0117 out_fcccp:
0118     iounmap(fep->fcc.fcccp);
0119 out_ep:
0120     iounmap(fep->fcc.ep);
0121 out_fccp:
0122     iounmap(fep->fcc.fccp);
0123 out:
0124     return ret;
0125 }
0126 
0127 #define FCC_NAPI_EVENT_MSK  (FCC_ENET_RXF | FCC_ENET_RXB | FCC_ENET_TXB)
0128 #define FCC_EVENT       (FCC_ENET_RXF | FCC_ENET_TXB)
0129 #define FCC_ERR_EVENT_MSK   (FCC_ENET_TXE)
0130 
0131 static int setup_data(struct net_device *dev)
0132 {
0133     struct fs_enet_private *fep = netdev_priv(dev);
0134 
0135     if (do_pd_setup(fep) != 0)
0136         return -EINVAL;
0137 
0138     fep->ev_napi = FCC_NAPI_EVENT_MSK;
0139     fep->ev = FCC_EVENT;
0140     fep->ev_err = FCC_ERR_EVENT_MSK;
0141 
0142     return 0;
0143 }
0144 
0145 static int allocate_bd(struct net_device *dev)
0146 {
0147     struct fs_enet_private *fep = netdev_priv(dev);
0148     const struct fs_platform_info *fpi = fep->fpi;
0149 
0150     fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev,
0151                         (fpi->tx_ring + fpi->rx_ring) *
0152                         sizeof(cbd_t), &fep->ring_mem_addr,
0153                         GFP_KERNEL);
0154     if (fep->ring_base == NULL)
0155         return -ENOMEM;
0156 
0157     return 0;
0158 }
0159 
0160 static void free_bd(struct net_device *dev)
0161 {
0162     struct fs_enet_private *fep = netdev_priv(dev);
0163     const struct fs_platform_info *fpi = fep->fpi;
0164 
0165     if (fep->ring_base)
0166         dma_free_coherent(fep->dev,
0167             (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
0168             (void __force *)fep->ring_base, fep->ring_mem_addr);
0169 }
0170 
0171 static void cleanup_data(struct net_device *dev)
0172 {
0173     /* nothing */
0174 }
0175 
0176 static void set_promiscuous_mode(struct net_device *dev)
0177 {
0178     struct fs_enet_private *fep = netdev_priv(dev);
0179     fcc_t __iomem *fccp = fep->fcc.fccp;
0180 
0181     S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
0182 }
0183 
0184 static void set_multicast_start(struct net_device *dev)
0185 {
0186     struct fs_enet_private *fep = netdev_priv(dev);
0187     fcc_enet_t __iomem *ep = fep->fcc.ep;
0188 
0189     W32(ep, fen_gaddrh, 0);
0190     W32(ep, fen_gaddrl, 0);
0191 }
0192 
0193 static void set_multicast_one(struct net_device *dev, const u8 *mac)
0194 {
0195     struct fs_enet_private *fep = netdev_priv(dev);
0196     fcc_enet_t __iomem *ep = fep->fcc.ep;
0197     u16 taddrh, taddrm, taddrl;
0198 
0199     taddrh = ((u16)mac[5] << 8) | mac[4];
0200     taddrm = ((u16)mac[3] << 8) | mac[2];
0201     taddrl = ((u16)mac[1] << 8) | mac[0];
0202 
0203     W16(ep, fen_taddrh, taddrh);
0204     W16(ep, fen_taddrm, taddrm);
0205     W16(ep, fen_taddrl, taddrl);
0206     fcc_cr_cmd(fep, CPM_CR_SET_GADDR);
0207 }
0208 
0209 static void set_multicast_finish(struct net_device *dev)
0210 {
0211     struct fs_enet_private *fep = netdev_priv(dev);
0212     fcc_t __iomem *fccp = fep->fcc.fccp;
0213     fcc_enet_t __iomem *ep = fep->fcc.ep;
0214 
0215     /* clear promiscuous always */
0216     C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
0217 
0218     /* if all multi or too many multicasts; just enable all */
0219     if ((dev->flags & IFF_ALLMULTI) != 0 ||
0220         netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) {
0221 
0222         W32(ep, fen_gaddrh, 0xffffffff);
0223         W32(ep, fen_gaddrl, 0xffffffff);
0224     }
0225 
0226     /* read back */
0227     fep->fcc.gaddrh = R32(ep, fen_gaddrh);
0228     fep->fcc.gaddrl = R32(ep, fen_gaddrl);
0229 }
0230 
0231 static void set_multicast_list(struct net_device *dev)
0232 {
0233     struct netdev_hw_addr *ha;
0234 
0235     if ((dev->flags & IFF_PROMISC) == 0) {
0236         set_multicast_start(dev);
0237         netdev_for_each_mc_addr(ha, dev)
0238             set_multicast_one(dev, ha->addr);
0239         set_multicast_finish(dev);
0240     } else
0241         set_promiscuous_mode(dev);
0242 }
0243 
0244 static void restart(struct net_device *dev)
0245 {
0246     struct fs_enet_private *fep = netdev_priv(dev);
0247     const struct fs_platform_info *fpi = fep->fpi;
0248     fcc_t __iomem *fccp = fep->fcc.fccp;
0249     fcc_c_t __iomem *fcccp = fep->fcc.fcccp;
0250     fcc_enet_t __iomem *ep = fep->fcc.ep;
0251     dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
0252     u16 paddrh, paddrm, paddrl;
0253     const unsigned char *mac;
0254     int i;
0255 
0256     C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
0257 
0258     /* clear everything (slow & steady does it) */
0259     for (i = 0; i < sizeof(*ep); i++)
0260         out_8((u8 __iomem *)ep + i, 0);
0261 
0262     /* get physical address */
0263     rx_bd_base_phys = fep->ring_mem_addr;
0264     tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
0265 
0266     /* point to bds */
0267     W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
0268     W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
0269 
0270     /* Set maximum bytes per receive buffer.
0271      * It must be a multiple of 32.
0272      */
0273     W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
0274 
0275     W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
0276     W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
0277 
0278     /* Allocate space in the reserved FCC area of DPRAM for the
0279      * internal buffers.  No one uses this space (yet), so we
0280      * can do this.  Later, we will add resource management for
0281      * this area.
0282      */
0283 
0284     W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset);
0285     W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32);
0286 
0287     W16(ep, fen_padptr, fpi->dpram_offset + 64);
0288 
0289     /* fill with special symbol...  */
0290     memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
0291 
0292     W32(ep, fen_genfcc.fcc_rbptr, 0);
0293     W32(ep, fen_genfcc.fcc_tbptr, 0);
0294     W32(ep, fen_genfcc.fcc_rcrc, 0);
0295     W32(ep, fen_genfcc.fcc_tcrc, 0);
0296     W16(ep, fen_genfcc.fcc_res1, 0);
0297     W32(ep, fen_genfcc.fcc_res2, 0);
0298 
0299     /* no CAM */
0300     W32(ep, fen_camptr, 0);
0301 
0302     /* Set CRC preset and mask */
0303     W32(ep, fen_cmask, 0xdebb20e3);
0304     W32(ep, fen_cpres, 0xffffffff);
0305 
0306     W32(ep, fen_crcec, 0);      /* CRC Error counter       */
0307     W32(ep, fen_alec, 0);       /* alignment error counter */
0308     W32(ep, fen_disfc, 0);      /* discard frame counter   */
0309     W16(ep, fen_retlim, 15);    /* Retry limit threshold   */
0310     W16(ep, fen_pper, 0);       /* Normal persistence      */
0311 
0312     /* set group address */
0313     W32(ep, fen_gaddrh, fep->fcc.gaddrh);
0314     W32(ep, fen_gaddrl, fep->fcc.gaddrh);
0315 
0316     /* Clear hash filter tables */
0317     W32(ep, fen_iaddrh, 0);
0318     W32(ep, fen_iaddrl, 0);
0319 
0320     /* Clear the Out-of-sequence TxBD  */
0321     W16(ep, fen_tfcstat, 0);
0322     W16(ep, fen_tfclen, 0);
0323     W32(ep, fen_tfcptr, 0);
0324 
0325     W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
0326     W16(ep, fen_minflr, PKT_MINBUF_SIZE);   /* minimum frame length register */
0327 
0328     /* set address */
0329     mac = dev->dev_addr;
0330     paddrh = ((u16)mac[5] << 8) | mac[4];
0331     paddrm = ((u16)mac[3] << 8) | mac[2];
0332     paddrl = ((u16)mac[1] << 8) | mac[0];
0333 
0334     W16(ep, fen_paddrh, paddrh);
0335     W16(ep, fen_paddrm, paddrm);
0336     W16(ep, fen_paddrl, paddrl);
0337 
0338     W16(ep, fen_taddrh, 0);
0339     W16(ep, fen_taddrm, 0);
0340     W16(ep, fen_taddrl, 0);
0341 
0342     W16(ep, fen_maxd1, 1520);   /* maximum DMA1 length */
0343     W16(ep, fen_maxd2, 1520);   /* maximum DMA2 length */
0344 
0345     /* Clear stat counters, in case we ever enable RMON */
0346     W32(ep, fen_octc, 0);
0347     W32(ep, fen_colc, 0);
0348     W32(ep, fen_broc, 0);
0349     W32(ep, fen_mulc, 0);
0350     W32(ep, fen_uspc, 0);
0351     W32(ep, fen_frgc, 0);
0352     W32(ep, fen_ospc, 0);
0353     W32(ep, fen_jbrc, 0);
0354     W32(ep, fen_p64c, 0);
0355     W32(ep, fen_p65c, 0);
0356     W32(ep, fen_p128c, 0);
0357     W32(ep, fen_p256c, 0);
0358     W32(ep, fen_p512c, 0);
0359     W32(ep, fen_p1024c, 0);
0360 
0361     W16(ep, fen_rfthr, 0);  /* Suggested by manual */
0362     W16(ep, fen_rfcnt, 0);
0363     W16(ep, fen_cftype, 0);
0364 
0365     fs_init_bds(dev);
0366 
0367     /* adjust to speed (for RMII mode) */
0368     if (fpi->use_rmii) {
0369         if (dev->phydev->speed == 100)
0370             C8(fcccp, fcc_gfemr, 0x20);
0371         else
0372             S8(fcccp, fcc_gfemr, 0x20);
0373     }
0374 
0375     fcc_cr_cmd(fep, CPM_CR_INIT_TRX);
0376 
0377     /* clear events */
0378     W16(fccp, fcc_fcce, 0xffff);
0379 
0380     /* Enable interrupts we wish to service */
0381     W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
0382 
0383     /* Set GFMR to enable Ethernet operating mode */
0384     W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
0385 
0386     /* set sync/delimiters */
0387     W16(fccp, fcc_fdsr, 0xd555);
0388 
0389     W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
0390 
0391     if (fpi->use_rmii)
0392         S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
0393 
0394     /* adjust to duplex mode */
0395     if (dev->phydev->duplex)
0396         S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
0397     else
0398         C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
0399 
0400     /* Restore multicast and promiscuous settings */
0401     set_multicast_list(dev);
0402 
0403     S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
0404 }
0405 
0406 static void stop(struct net_device *dev)
0407 {
0408     struct fs_enet_private *fep = netdev_priv(dev);
0409     fcc_t __iomem *fccp = fep->fcc.fccp;
0410 
0411     /* stop ethernet */
0412     C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
0413 
0414     /* clear events */
0415     W16(fccp, fcc_fcce, 0xffff);
0416 
0417     /* clear interrupt mask */
0418     W16(fccp, fcc_fccm, 0);
0419 
0420     fs_cleanup_bds(dev);
0421 }
0422 
0423 static void napi_clear_event_fs(struct net_device *dev)
0424 {
0425     struct fs_enet_private *fep = netdev_priv(dev);
0426     fcc_t __iomem *fccp = fep->fcc.fccp;
0427 
0428     W16(fccp, fcc_fcce, FCC_NAPI_EVENT_MSK);
0429 }
0430 
0431 static void napi_enable_fs(struct net_device *dev)
0432 {
0433     struct fs_enet_private *fep = netdev_priv(dev);
0434     fcc_t __iomem *fccp = fep->fcc.fccp;
0435 
0436     S16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK);
0437 }
0438 
0439 static void napi_disable_fs(struct net_device *dev)
0440 {
0441     struct fs_enet_private *fep = netdev_priv(dev);
0442     fcc_t __iomem *fccp = fep->fcc.fccp;
0443 
0444     C16(fccp, fcc_fccm, FCC_NAPI_EVENT_MSK);
0445 }
0446 
0447 static void rx_bd_done(struct net_device *dev)
0448 {
0449     /* nothing */
0450 }
0451 
0452 static void tx_kickstart(struct net_device *dev)
0453 {
0454     struct fs_enet_private *fep = netdev_priv(dev);
0455     fcc_t __iomem *fccp = fep->fcc.fccp;
0456 
0457     S16(fccp, fcc_ftodr, 0x8000);
0458 }
0459 
0460 static u32 get_int_events(struct net_device *dev)
0461 {
0462     struct fs_enet_private *fep = netdev_priv(dev);
0463     fcc_t __iomem *fccp = fep->fcc.fccp;
0464 
0465     return (u32)R16(fccp, fcc_fcce);
0466 }
0467 
0468 static void clear_int_events(struct net_device *dev, u32 int_events)
0469 {
0470     struct fs_enet_private *fep = netdev_priv(dev);
0471     fcc_t __iomem *fccp = fep->fcc.fccp;
0472 
0473     W16(fccp, fcc_fcce, int_events & 0xffff);
0474 }
0475 
0476 static void ev_error(struct net_device *dev, u32 int_events)
0477 {
0478     struct fs_enet_private *fep = netdev_priv(dev);
0479 
0480     dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events);
0481 }
0482 
0483 static int get_regs(struct net_device *dev, void *p, int *sizep)
0484 {
0485     struct fs_enet_private *fep = netdev_priv(dev);
0486 
0487     if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1)
0488         return -EINVAL;
0489 
0490     memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
0491     p = (char *)p + sizeof(fcc_t);
0492 
0493     memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
0494     p = (char *)p + sizeof(fcc_enet_t);
0495 
0496     memcpy_fromio(p, fep->fcc.fcccp, 1);
0497     return 0;
0498 }
0499 
0500 static int get_regs_len(struct net_device *dev)
0501 {
0502     return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1;
0503 }
0504 
0505 /* Some transmit errors cause the transmitter to shut
0506  * down.  We now issue a restart transmit.
0507  * Also, to workaround 8260 device erratum CPM37, we must
0508  * disable and then re-enable the transmitterfollowing a
0509  * Late Collision, Underrun, or Retry Limit error.
0510  * In addition, tbptr may point beyond BDs beyond still marked
0511  * as ready due to internal pipelining, so we need to look back
0512  * through the BDs and adjust tbptr to point to the last BD
0513  * marked as ready.  This may result in some buffers being
0514  * retransmitted.
0515  */
0516 static void tx_restart(struct net_device *dev)
0517 {
0518     struct fs_enet_private *fep = netdev_priv(dev);
0519     fcc_t __iomem *fccp = fep->fcc.fccp;
0520     const struct fs_platform_info *fpi = fep->fpi;
0521     fcc_enet_t __iomem *ep = fep->fcc.ep;
0522     cbd_t __iomem *curr_tbptr;
0523     cbd_t __iomem *recheck_bd;
0524     cbd_t __iomem *prev_bd;
0525     cbd_t __iomem *last_tx_bd;
0526 
0527     last_tx_bd = fep->tx_bd_base + (fpi->tx_ring - 1);
0528 
0529     /* get the current bd held in TBPTR  and scan back from this point */
0530     recheck_bd = curr_tbptr = (cbd_t __iomem *)
0531         ((R32(ep, fen_genfcc.fcc_tbptr) - fep->ring_mem_addr) +
0532         fep->ring_base);
0533 
0534     prev_bd = (recheck_bd == fep->tx_bd_base) ? last_tx_bd : recheck_bd - 1;
0535 
0536     /* Move through the bds in reverse, look for the earliest buffer
0537      * that is not ready.  Adjust TBPTR to the following buffer */
0538     while ((CBDR_SC(prev_bd) & BD_ENET_TX_READY) != 0) {
0539         /* Go back one buffer */
0540         recheck_bd = prev_bd;
0541 
0542         /* update the previous buffer */
0543         prev_bd = (prev_bd == fep->tx_bd_base) ? last_tx_bd : prev_bd - 1;
0544 
0545         /* We should never see all bds marked as ready, check anyway */
0546         if (recheck_bd == curr_tbptr)
0547             break;
0548     }
0549     /* Now update the TBPTR and dirty flag to the current buffer */
0550     W32(ep, fen_genfcc.fcc_tbptr,
0551         (uint) (((void *)recheck_bd - fep->ring_base) +
0552         fep->ring_mem_addr));
0553     fep->dirty_tx = recheck_bd;
0554 
0555     C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
0556     udelay(10);
0557     S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
0558 
0559     fcc_cr_cmd(fep, CPM_CR_RESTART_TX);
0560 }
0561 
0562 /*************************************************************************/
0563 
0564 const struct fs_ops fs_fcc_ops = {
0565     .setup_data     = setup_data,
0566     .cleanup_data       = cleanup_data,
0567     .set_multicast_list = set_multicast_list,
0568     .restart        = restart,
0569     .stop           = stop,
0570     .napi_clear_event   = napi_clear_event_fs,
0571     .napi_enable        = napi_enable_fs,
0572     .napi_disable       = napi_disable_fs,
0573     .rx_bd_done     = rx_bd_done,
0574     .tx_kickstart       = tx_kickstart,
0575     .get_int_events     = get_int_events,
0576     .clear_int_events   = clear_int_events,
0577     .ev_error       = ev_error,
0578     .get_regs       = get_regs,
0579     .get_regs_len       = get_regs_len,
0580     .tx_restart     = tx_restart,
0581     .allocate_bd        = allocate_bd,
0582     .free_bd        = free_bd,
0583 };
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