freescale/fs_enet/fs_enet.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef FS_ENET_H
0003 #define FS_ENET_H
0004
0005 #include <linux/mii.h>
0006 #include <linux/netdevice.h>
0007 #include <linux/types.h>
0008 #include <linux/list.h>
0009 #include <linux/phy.h>
0010 #include <linux/dma-mapping.h>
0011
0012 #include <linux/fs_enet_pd.h>
0013 #include <asm/fs_pd.h>
0014
0015 #ifdef CONFIG_CPM1
0016 #include <asm/cpm1.h>
0017 #endif
0018
0019 #if defined(CONFIG_FS_ENET_HAS_FEC)
0020 #include <asm/cpm.h>
0021
0022 #if defined(CONFIG_FS_ENET_MPC5121_FEC)
0023 /* MPC5121 FEC has different register layout */
0024 struct fec {
0025     u32 fec_reserved0;
0026     u32 fec_ievent;         /* Interrupt event reg */
0027     u32 fec_imask;          /* Interrupt mask reg */
0028     u32 fec_reserved1;
0029     u32 fec_r_des_active;       /* Receive descriptor reg */
0030     u32 fec_x_des_active;       /* Transmit descriptor reg */
0031     u32 fec_reserved2[3];
0032     u32 fec_ecntrl;         /* Ethernet control reg */
0033     u32 fec_reserved3[6];
0034     u32 fec_mii_data;       /* MII manage frame reg */
0035     u32 fec_mii_speed;      /* MII speed control reg */
0036     u32 fec_reserved4[7];
0037     u32 fec_mib_ctrlstat;       /* MIB control/status reg */
0038     u32 fec_reserved5[7];
0039     u32 fec_r_cntrl;        /* Receive control reg */
0040     u32 fec_reserved6[15];
0041     u32 fec_x_cntrl;        /* Transmit Control reg */
0042     u32 fec_reserved7[7];
0043     u32 fec_addr_low;       /* Low 32bits MAC address */
0044     u32 fec_addr_high;      /* High 16bits MAC address */
0045     u32 fec_opd;            /* Opcode + Pause duration */
0046     u32 fec_reserved8[10];
0047     u32 fec_hash_table_high;    /* High 32bits hash table */
0048     u32 fec_hash_table_low;     /* Low 32bits hash table */
0049     u32 fec_grp_hash_table_high;    /* High 32bits hash table */
0050     u32 fec_grp_hash_table_low; /* Low 32bits hash table */
0051     u32 fec_reserved9[7];
0052     u32 fec_x_wmrk;         /* FIFO transmit water mark */
0053     u32 fec_reserved10;
0054     u32 fec_r_bound;        /* FIFO receive bound reg */
0055     u32 fec_r_fstart;       /* FIFO receive start reg */
0056     u32 fec_reserved11[11];
0057     u32 fec_r_des_start;        /* Receive descriptor ring */
0058     u32 fec_x_des_start;        /* Transmit descriptor ring */
0059     u32 fec_r_buff_size;        /* Maximum receive buff size */
0060     u32 fec_reserved12[26];
0061     u32 fec_dma_control;        /* DMA Endian and other ctrl */
0062 };
0063 #endif
0064
0065 struct fec_info {
0066     struct fec __iomem *fecp;
0067     u32 mii_speed;
0068 };
0069 #endif
0070
0071 #ifdef CONFIG_CPM2
0072 #include <asm/cpm2.h>
0073 #endif
0074
0075 /* hw driver ops */
0076 struct fs_ops {
0077     int (*setup_data)(struct net_device *dev);
0078     int (*allocate_bd)(struct net_device *dev);
0079     void (*free_bd)(struct net_device *dev);
0080     void (*cleanup_data)(struct net_device *dev);
0081     void (*set_multicast_list)(struct net_device *dev);
0082     void (*adjust_link)(struct net_device *dev);
0083     void (*restart)(struct net_device *dev);
0084     void (*stop)(struct net_device *dev);
0085     void (*napi_clear_event)(struct net_device *dev);
0086     void (*napi_enable)(struct net_device *dev);
0087     void (*napi_disable)(struct net_device *dev);
0088     void (*rx_bd_done)(struct net_device *dev);
0089     void (*tx_kickstart)(struct net_device *dev);
0090     u32 (*get_int_events)(struct net_device *dev);
0091     void (*clear_int_events)(struct net_device *dev, u32 int_events);
0092     void (*ev_error)(struct net_device *dev, u32 int_events);
0093     int (*get_regs)(struct net_device *dev, void *p, int *sizep);
0094     int (*get_regs_len)(struct net_device *dev);
0095     void (*tx_restart)(struct net_device *dev);
0096 };
0097
0098 struct phy_info {
0099     unsigned int id;
0100     const char *name;
0101     void (*startup) (struct net_device * dev);
0102     void (*shutdown) (struct net_device * dev);
0103     void (*ack_int) (struct net_device * dev);
0104 };
0105
0106 /* The FEC stores dest/src/type, data, and checksum for receive packets.
0107  */
0108 #define MAX_MTU 1508        /* Allow fullsized pppoe packets over VLAN */
0109 #define MIN_MTU 46      /* this is data size */
0110 #define CRC_LEN 4
0111
0112 #define PKT_MAXBUF_SIZE     (MAX_MTU+ETH_HLEN+CRC_LEN)
0113 #define PKT_MINBUF_SIZE     (MIN_MTU+ETH_HLEN+CRC_LEN)
0114
0115 /* Must be a multiple of 32 (to cover both FEC & FCC) */
0116 #define PKT_MAXBLR_SIZE     ((PKT_MAXBUF_SIZE + 31) & ~31)
0117 /* This is needed so that invalidate_xxx wont invalidate too much */
0118 #define ENET_RX_ALIGN  16
0119 #define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)
0120
0121 struct fs_enet_private {
0122     struct napi_struct napi;
0123     struct device *dev; /* pointer back to the device (must be initialized first) */
0124     struct net_device *ndev;
0125     spinlock_t lock;    /* during all ops except TX pckt processing */
0126     spinlock_t tx_lock; /* during fs_start_xmit and fs_tx         */
0127     struct fs_platform_info *fpi;
0128     struct work_struct timeout_work;
0129     const struct fs_ops *ops;
0130     int rx_ring, tx_ring;
0131     dma_addr_t ring_mem_addr;
0132     void __iomem *ring_base;
0133     struct sk_buff **rx_skbuff;
0134     struct sk_buff **tx_skbuff;
0135     char *mapped_as_page;
0136     cbd_t __iomem *rx_bd_base;  /* Address of Rx and Tx buffers.    */
0137     cbd_t __iomem *tx_bd_base;
0138     cbd_t __iomem *dirty_tx;    /* ring entries to be free()ed.     */
0139     cbd_t __iomem *cur_rx;
0140     cbd_t __iomem *cur_tx;
0141     int tx_free;
0142     const struct phy_info *phy;
0143     u32 msg_enable;
0144     struct mii_if_info mii_if;
0145     unsigned int last_mii_status;
0146     int interrupt;
0147
0148     int oldduplex, oldspeed, oldlink;   /* current settings */
0149
0150     /* event masks */
0151     u32 ev_napi;        /* mask of NAPI events */
0152     u32 ev;         /* event mask          */
0153     u32 ev_err;     /* error event mask       */
0154
0155     u16 bd_rx_empty;    /* mask of BD rx empty    */
0156     u16 bd_rx_err;      /* mask of BD rx errors   */
0157
0158     union {
0159         struct {
0160             int idx;        /* FEC1 = 0, FEC2 = 1  */
0161             void __iomem *fecp; /* hw registers        */
0162             u32 hthi, htlo;     /* state for multicast */
0163         } fec;
0164
0165         struct {
0166             int idx;        /* FCC1-3 = 0-2        */
0167             void __iomem *fccp; /* hw registers        */
0168             void __iomem *ep;   /* parameter ram       */
0169             void __iomem *fcccp;    /* hw registers cont.  */
0170             void __iomem *mem;  /* FCC DPRAM */
0171             u32 gaddrh, gaddrl; /* group address       */
0172         } fcc;
0173
0174         struct {
0175             int idx;        /* FEC1 = 0, FEC2 = 1  */
0176             void __iomem *sccp; /* hw registers        */
0177             void __iomem *ep;   /* parameter ram       */
0178             u32 hthi, htlo;     /* state for multicast */
0179         } scc;
0180
0181     };
0182 };
0183
0184 /***************************************************************************/
0185
0186 void fs_init_bds(struct net_device *dev);
0187 void fs_cleanup_bds(struct net_device *dev);
0188
0189 /***************************************************************************/
0190
0191 #define DRV_MODULE_NAME     "fs_enet"
0192 #define PFX DRV_MODULE_NAME ": "
0193
0194 /***************************************************************************/
0195
0196 int fs_enet_platform_init(void);
0197 void fs_enet_platform_cleanup(void);
0198
0199 /***************************************************************************/
0200 /* buffer descriptor access macros */
0201
0202 /* access macros */
0203 #if defined(CONFIG_CPM1)
0204 /* for a CPM1 __raw_xxx's are sufficient */
0205 #define __cbd_out32(addr, x)    __raw_writel(x, addr)
0206 #define __cbd_out16(addr, x)    __raw_writew(x, addr)
0207 #define __cbd_in32(addr)    __raw_readl(addr)
0208 #define __cbd_in16(addr)    __raw_readw(addr)
0209 #else
0210 /* for others play it safe */
0211 #define __cbd_out32(addr, x)    out_be32(addr, x)
0212 #define __cbd_out16(addr, x)    out_be16(addr, x)
0213 #define __cbd_in32(addr)    in_be32(addr)
0214 #define __cbd_in16(addr)    in_be16(addr)
0215 #endif
0216
0217 /* write */
0218 #define CBDW_SC(_cbd, _sc)      __cbd_out16(&(_cbd)->cbd_sc, (_sc))
0219 #define CBDW_DATLEN(_cbd, _datlen)  __cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
0220 #define CBDW_BUFADDR(_cbd, _bufaddr)    __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
0221
0222 /* read */
0223 #define CBDR_SC(_cbd)           __cbd_in16(&(_cbd)->cbd_sc)
0224 #define CBDR_DATLEN(_cbd)       __cbd_in16(&(_cbd)->cbd_datlen)
0225 #define CBDR_BUFADDR(_cbd)      __cbd_in32(&(_cbd)->cbd_bufaddr)
0226
0227 /* set bits */
0228 #define CBDS_SC(_cbd, _sc)      CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
0229
0230 /* clear bits */
0231 #define CBDC_SC(_cbd, _sc)      CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
0232
0233 /*******************************************************************/
0234
0235 extern const struct fs_ops fs_fec_ops;
0236 extern const struct fs_ops fs_fcc_ops;
0237 extern const struct fs_ops fs_scc_ops;
0238
0239 /*******************************************************************/
0240
0241 #endif