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0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /* Copyright 2017-2019 NXP */
0003 
0004 #include <asm/unaligned.h>
0005 #include <linux/mdio.h>
0006 #include <linux/module.h>
0007 #include <linux/fsl/enetc_mdio.h>
0008 #include <linux/of_platform.h>
0009 #include <linux/of_mdio.h>
0010 #include <linux/of_net.h>
0011 #include <linux/pcs-lynx.h>
0012 #include "enetc_ierb.h"
0013 #include "enetc_pf.h"
0014 
0015 #define ENETC_DRV_NAME_STR "ENETC PF driver"
0016 
0017 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
0018 {
0019     u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
0020     u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
0021 
0022     put_unaligned_le32(upper, addr);
0023     put_unaligned_le16(lower, addr + 4);
0024 }
0025 
0026 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
0027                       const u8 *addr)
0028 {
0029     u32 upper = get_unaligned_le32(addr);
0030     u16 lower = get_unaligned_le16(addr + 4);
0031 
0032     __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
0033     __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
0034 }
0035 
0036 static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
0037 {
0038     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0039     struct sockaddr *saddr = addr;
0040 
0041     if (!is_valid_ether_addr(saddr->sa_data))
0042         return -EADDRNOTAVAIL;
0043 
0044     eth_hw_addr_set(ndev, saddr->sa_data);
0045     enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
0046 
0047     return 0;
0048 }
0049 
0050 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
0051 {
0052     u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
0053 
0054     val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
0055     enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
0056 }
0057 
0058 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
0059 {
0060     pf->vlan_promisc_simap |= BIT(si_idx);
0061     enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
0062 }
0063 
0064 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
0065 {
0066     pf->vlan_promisc_simap &= ~BIT(si_idx);
0067     enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
0068 }
0069 
0070 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
0071 {
0072     u32 val = 0;
0073 
0074     if (vlan)
0075         val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
0076 
0077     enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
0078 }
0079 
0080 static int enetc_mac_addr_hash_idx(const u8 *addr)
0081 {
0082     u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
0083     u64 mask = 0;
0084     int res = 0;
0085     int i;
0086 
0087     for (i = 0; i < 8; i++)
0088         mask |= BIT_ULL(i * 6);
0089 
0090     for (i = 0; i < 6; i++)
0091         res |= (hweight64(fold & (mask << i)) & 0x1) << i;
0092 
0093     return res;
0094 }
0095 
0096 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
0097 {
0098     filter->mac_addr_cnt = 0;
0099 
0100     bitmap_zero(filter->mac_hash_table,
0101             ENETC_MADDR_HASH_TBL_SZ);
0102 }
0103 
0104 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
0105                      const unsigned char *addr)
0106 {
0107     /* add exact match addr */
0108     ether_addr_copy(filter->mac_addr, addr);
0109     filter->mac_addr_cnt++;
0110 }
0111 
0112 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
0113                      const unsigned char *addr)
0114 {
0115     int idx = enetc_mac_addr_hash_idx(addr);
0116 
0117     /* add hash table entry */
0118     __set_bit(idx, filter->mac_hash_table);
0119     filter->mac_addr_cnt++;
0120 }
0121 
0122 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
0123 {
0124     bool err = si->errata & ENETC_ERR_UCMCSWP;
0125 
0126     if (type == UC) {
0127         enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
0128         enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
0129     } else { /* MC */
0130         enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
0131         enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
0132     }
0133 }
0134 
0135 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
0136                  unsigned long hash)
0137 {
0138     bool err = si->errata & ENETC_ERR_UCMCSWP;
0139 
0140     if (type == UC) {
0141         enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
0142                   lower_32_bits(hash));
0143         enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
0144                   upper_32_bits(hash));
0145     } else { /* MC */
0146         enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
0147                   lower_32_bits(hash));
0148         enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
0149                   upper_32_bits(hash));
0150     }
0151 }
0152 
0153 static void enetc_sync_mac_filters(struct enetc_pf *pf)
0154 {
0155     struct enetc_mac_filter *f = pf->mac_filter;
0156     struct enetc_si *si = pf->si;
0157     int i, pos;
0158 
0159     pos = EMETC_MAC_ADDR_FILT_RES;
0160 
0161     for (i = 0; i < MADDR_TYPE; i++, f++) {
0162         bool em = (f->mac_addr_cnt == 1) && (i == UC);
0163         bool clear = !f->mac_addr_cnt;
0164 
0165         if (clear) {
0166             if (i == UC)
0167                 enetc_clear_mac_flt_entry(si, pos);
0168 
0169             enetc_clear_mac_ht_flt(si, 0, i);
0170             continue;
0171         }
0172 
0173         /* exact match filter */
0174         if (em) {
0175             int err;
0176 
0177             enetc_clear_mac_ht_flt(si, 0, UC);
0178 
0179             err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
0180                               BIT(0));
0181             if (!err)
0182                 continue;
0183 
0184             /* fallback to HT filtering */
0185             dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
0186                  err);
0187         }
0188 
0189         /* hash table filter, clear EM filter for UC entries */
0190         if (i == UC)
0191             enetc_clear_mac_flt_entry(si, pos);
0192 
0193         enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
0194     }
0195 }
0196 
0197 static void enetc_pf_set_rx_mode(struct net_device *ndev)
0198 {
0199     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0200     struct enetc_pf *pf = enetc_si_priv(priv->si);
0201     struct enetc_hw *hw = &priv->si->hw;
0202     bool uprom = false, mprom = false;
0203     struct enetc_mac_filter *filter;
0204     struct netdev_hw_addr *ha;
0205     u32 psipmr = 0;
0206     bool em;
0207 
0208     if (ndev->flags & IFF_PROMISC) {
0209         /* enable promisc mode for SI0 (PF) */
0210         psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
0211         uprom = true;
0212         mprom = true;
0213     } else if (ndev->flags & IFF_ALLMULTI) {
0214         /* enable multi cast promisc mode for SI0 (PF) */
0215         psipmr = ENETC_PSIPMR_SET_MP(0);
0216         mprom = true;
0217     }
0218 
0219     /* first 2 filter entries belong to PF */
0220     if (!uprom) {
0221         /* Update unicast filters */
0222         filter = &pf->mac_filter[UC];
0223         enetc_reset_mac_addr_filter(filter);
0224 
0225         em = (netdev_uc_count(ndev) == 1);
0226         netdev_for_each_uc_addr(ha, ndev) {
0227             if (em) {
0228                 enetc_add_mac_addr_em_filter(filter, ha->addr);
0229                 break;
0230             }
0231 
0232             enetc_add_mac_addr_ht_filter(filter, ha->addr);
0233         }
0234     }
0235 
0236     if (!mprom) {
0237         /* Update multicast filters */
0238         filter = &pf->mac_filter[MC];
0239         enetc_reset_mac_addr_filter(filter);
0240 
0241         netdev_for_each_mc_addr(ha, ndev) {
0242             if (!is_multicast_ether_addr(ha->addr))
0243                 continue;
0244 
0245             enetc_add_mac_addr_ht_filter(filter, ha->addr);
0246         }
0247     }
0248 
0249     if (!uprom || !mprom)
0250         /* update PF entries */
0251         enetc_sync_mac_filters(pf);
0252 
0253     psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
0254           ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
0255     enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
0256 }
0257 
0258 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
0259                      unsigned long hash)
0260 {
0261     enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
0262     enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
0263 }
0264 
0265 static int enetc_vid_hash_idx(unsigned int vid)
0266 {
0267     int res = 0;
0268     int i;
0269 
0270     for (i = 0; i < 6; i++)
0271         res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
0272 
0273     return res;
0274 }
0275 
0276 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
0277 {
0278     int i;
0279 
0280     if (rehash) {
0281         bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
0282 
0283         for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
0284             int hidx = enetc_vid_hash_idx(i);
0285 
0286             __set_bit(hidx, pf->vlan_ht_filter);
0287         }
0288     }
0289 
0290     enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
0291 }
0292 
0293 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
0294 {
0295     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0296     struct enetc_pf *pf = enetc_si_priv(priv->si);
0297     int idx;
0298 
0299     __set_bit(vid, pf->active_vlans);
0300 
0301     idx = enetc_vid_hash_idx(vid);
0302     if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
0303         enetc_sync_vlan_ht_filter(pf, false);
0304 
0305     return 0;
0306 }
0307 
0308 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
0309 {
0310     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0311     struct enetc_pf *pf = enetc_si_priv(priv->si);
0312 
0313     __clear_bit(vid, pf->active_vlans);
0314     enetc_sync_vlan_ht_filter(pf, true);
0315 
0316     return 0;
0317 }
0318 
0319 static void enetc_set_loopback(struct net_device *ndev, bool en)
0320 {
0321     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0322     struct enetc_hw *hw = &priv->si->hw;
0323     u32 reg;
0324 
0325     reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
0326     if (reg & ENETC_PM0_IFM_RG) {
0327         /* RGMII mode */
0328         reg = (reg & ~ENETC_PM0_IFM_RLP) |
0329               (en ? ENETC_PM0_IFM_RLP : 0);
0330         enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
0331     } else {
0332         /* assume SGMII mode */
0333         reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
0334         reg = (reg & ~ENETC_PM0_CMD_XGLP) |
0335               (en ? ENETC_PM0_CMD_XGLP : 0);
0336         reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
0337               (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
0338         enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
0339         enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
0340     }
0341 }
0342 
0343 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
0344 {
0345     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0346     struct enetc_pf *pf = enetc_si_priv(priv->si);
0347     struct enetc_vf_state *vf_state;
0348 
0349     if (vf >= pf->total_vfs)
0350         return -EINVAL;
0351 
0352     if (!is_valid_ether_addr(mac))
0353         return -EADDRNOTAVAIL;
0354 
0355     vf_state = &pf->vf_state[vf];
0356     vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
0357     enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
0358     return 0;
0359 }
0360 
0361 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
0362                 u8 qos, __be16 proto)
0363 {
0364     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0365     struct enetc_pf *pf = enetc_si_priv(priv->si);
0366 
0367     if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
0368         return -EOPNOTSUPP;
0369 
0370     if (vf >= pf->total_vfs)
0371         return -EINVAL;
0372 
0373     if (proto != htons(ETH_P_8021Q))
0374         /* only C-tags supported for now */
0375         return -EPROTONOSUPPORT;
0376 
0377     enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
0378     return 0;
0379 }
0380 
0381 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
0382 {
0383     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0384     struct enetc_pf *pf = enetc_si_priv(priv->si);
0385     u32 cfgr;
0386 
0387     if (vf >= pf->total_vfs)
0388         return -EINVAL;
0389 
0390     cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
0391     cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
0392     enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
0393 
0394     return 0;
0395 }
0396 
0397 static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
0398                    int si)
0399 {
0400     struct device *dev = &pf->si->pdev->dev;
0401     struct enetc_hw *hw = &pf->si->hw;
0402     u8 mac_addr[ETH_ALEN] = { 0 };
0403     int err;
0404 
0405     /* (1) try to get the MAC address from the device tree */
0406     if (np) {
0407         err = of_get_mac_address(np, mac_addr);
0408         if (err == -EPROBE_DEFER)
0409             return err;
0410     }
0411 
0412     /* (2) bootloader supplied MAC address */
0413     if (is_zero_ether_addr(mac_addr))
0414         enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
0415 
0416     /* (3) choose a random one */
0417     if (is_zero_ether_addr(mac_addr)) {
0418         eth_random_addr(mac_addr);
0419         dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
0420              si, mac_addr);
0421     }
0422 
0423     enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
0424 
0425     return 0;
0426 }
0427 
0428 static int enetc_setup_mac_addresses(struct device_node *np,
0429                      struct enetc_pf *pf)
0430 {
0431     int err, i;
0432 
0433     /* The PF might take its MAC from the device tree */
0434     err = enetc_setup_mac_address(np, pf, 0);
0435     if (err)
0436         return err;
0437 
0438     for (i = 0; i < pf->total_vfs; i++) {
0439         err = enetc_setup_mac_address(NULL, pf, i + 1);
0440         if (err)
0441             return err;
0442     }
0443 
0444     return 0;
0445 }
0446 
0447 static void enetc_port_assign_rfs_entries(struct enetc_si *si)
0448 {
0449     struct enetc_pf *pf = enetc_si_priv(si);
0450     struct enetc_hw *hw = &si->hw;
0451     int num_entries, vf_entries, i;
0452     u32 val;
0453 
0454     /* split RFS entries between functions */
0455     val = enetc_port_rd(hw, ENETC_PRFSCAPR);
0456     num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
0457     vf_entries = num_entries / (pf->total_vfs + 1);
0458 
0459     for (i = 0; i < pf->total_vfs; i++)
0460         enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
0461     enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
0462               num_entries - vf_entries * pf->total_vfs);
0463 
0464     /* enable RFS on port */
0465     enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
0466 }
0467 
0468 static void enetc_port_si_configure(struct enetc_si *si)
0469 {
0470     struct enetc_pf *pf = enetc_si_priv(si);
0471     struct enetc_hw *hw = &si->hw;
0472     int num_rings, i;
0473     u32 val;
0474 
0475     val = enetc_port_rd(hw, ENETC_PCAPR0);
0476     num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
0477 
0478     val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
0479     val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
0480 
0481     if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
0482         val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
0483         val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
0484 
0485         dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
0486              num_rings, ENETC_PF_NUM_RINGS);
0487 
0488         num_rings = 0;
0489     }
0490 
0491     /* Add default one-time settings for SI0 (PF) */
0492     val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
0493 
0494     enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
0495 
0496     if (num_rings)
0497         num_rings -= ENETC_PF_NUM_RINGS;
0498 
0499     /* Configure the SIs for each available VF */
0500     val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
0501     val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
0502 
0503     if (num_rings) {
0504         num_rings /= pf->total_vfs;
0505         val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
0506         val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
0507     }
0508 
0509     for (i = 0; i < pf->total_vfs; i++)
0510         enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
0511 
0512     /* Port level VLAN settings */
0513     val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
0514     enetc_port_wr(hw, ENETC_PVCLCTR, val);
0515     /* use outer tag for VLAN filtering */
0516     enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
0517 }
0518 
0519 static void enetc_configure_port_mac(struct enetc_hw *hw)
0520 {
0521     int tc;
0522 
0523     enetc_port_wr(hw, ENETC_PM0_MAXFRM,
0524               ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
0525 
0526     for (tc = 0; tc < 8; tc++)
0527         enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
0528 
0529     enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
0530               ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
0531 
0532     enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
0533               ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
0534 
0535     /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
0536      * and may lead to RX lock-up under traffic. Set it to 1 instead,
0537      * as recommended by the hardware team.
0538      */
0539     enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
0540 }
0541 
0542 static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
0543 {
0544     u32 val;
0545 
0546     if (phy_interface_mode_is_rgmii(phy_mode)) {
0547         val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
0548         val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
0549         val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
0550         enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
0551     }
0552 
0553     if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
0554         val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
0555         enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
0556     }
0557 }
0558 
0559 static void enetc_mac_enable(struct enetc_hw *hw, bool en)
0560 {
0561     u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
0562 
0563     val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
0564     val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
0565 
0566     enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
0567     enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
0568 }
0569 
0570 static void enetc_configure_port_pmac(struct enetc_hw *hw)
0571 {
0572     u32 temp;
0573 
0574     /* Set pMAC step lock */
0575     temp = enetc_port_rd(hw, ENETC_PFPMR);
0576     enetc_port_wr(hw, ENETC_PFPMR,
0577               temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
0578 
0579     temp = enetc_port_rd(hw, ENETC_MMCSR);
0580     enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
0581 }
0582 
0583 static void enetc_configure_port(struct enetc_pf *pf)
0584 {
0585     u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
0586     struct enetc_hw *hw = &pf->si->hw;
0587 
0588     enetc_configure_port_pmac(hw);
0589 
0590     enetc_configure_port_mac(hw);
0591 
0592     enetc_port_si_configure(pf->si);
0593 
0594     /* set up hash key */
0595     get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
0596     enetc_set_rss_key(hw, hash_key);
0597 
0598     /* split up RFS entries */
0599     enetc_port_assign_rfs_entries(pf->si);
0600 
0601     /* enforce VLAN promisc mode for all SIs */
0602     pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
0603     enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
0604 
0605     enetc_port_wr(hw, ENETC_PSIPMR, 0);
0606 
0607     /* enable port */
0608     enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
0609 }
0610 
0611 /* Messaging */
0612 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
0613                         int vf_id)
0614 {
0615     struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
0616     struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
0617     struct enetc_msg_cmd_set_primary_mac *cmd;
0618     struct device *dev = &pf->si->pdev->dev;
0619     u16 cmd_id;
0620     char *addr;
0621 
0622     cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
0623     cmd_id = cmd->header.id;
0624     if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
0625         return ENETC_MSG_CMD_STATUS_FAIL;
0626 
0627     addr = cmd->mac.sa_data;
0628     if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
0629         dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
0630              vf_id);
0631     else
0632         enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
0633 
0634     return ENETC_MSG_CMD_STATUS_OK;
0635 }
0636 
0637 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
0638 {
0639     struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
0640     struct device *dev = &pf->si->pdev->dev;
0641     struct enetc_msg_cmd_header *cmd_hdr;
0642     u16 cmd_type;
0643 
0644     *status = ENETC_MSG_CMD_STATUS_OK;
0645     cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
0646     cmd_type = cmd_hdr->type;
0647 
0648     switch (cmd_type) {
0649     case ENETC_MSG_CMD_MNG_MAC:
0650         *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
0651         break;
0652     default:
0653         dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
0654             cmd_type);
0655     }
0656 }
0657 
0658 #ifdef CONFIG_PCI_IOV
0659 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
0660 {
0661     struct enetc_si *si = pci_get_drvdata(pdev);
0662     struct enetc_pf *pf = enetc_si_priv(si);
0663     int err;
0664 
0665     if (!num_vfs) {
0666         enetc_msg_psi_free(pf);
0667         kfree(pf->vf_state);
0668         pf->num_vfs = 0;
0669         pci_disable_sriov(pdev);
0670     } else {
0671         pf->num_vfs = num_vfs;
0672 
0673         pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
0674                        GFP_KERNEL);
0675         if (!pf->vf_state) {
0676             pf->num_vfs = 0;
0677             return -ENOMEM;
0678         }
0679 
0680         err = enetc_msg_psi_init(pf);
0681         if (err) {
0682             dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
0683             goto err_msg_psi;
0684         }
0685 
0686         err = pci_enable_sriov(pdev, num_vfs);
0687         if (err) {
0688             dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
0689             goto err_en_sriov;
0690         }
0691     }
0692 
0693     return num_vfs;
0694 
0695 err_en_sriov:
0696     enetc_msg_psi_free(pf);
0697 err_msg_psi:
0698     kfree(pf->vf_state);
0699     pf->num_vfs = 0;
0700 
0701     return err;
0702 }
0703 #else
0704 #define enetc_sriov_configure(pdev, num_vfs)    (void)0
0705 #endif
0706 
0707 static int enetc_pf_set_features(struct net_device *ndev,
0708                  netdev_features_t features)
0709 {
0710     netdev_features_t changed = ndev->features ^ features;
0711     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0712     int err;
0713 
0714     if (changed & NETIF_F_HW_TC) {
0715         err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
0716         if (err)
0717             return err;
0718     }
0719 
0720     if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
0721         struct enetc_pf *pf = enetc_si_priv(priv->si);
0722 
0723         if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
0724             enetc_disable_si_vlan_promisc(pf, 0);
0725         else
0726             enetc_enable_si_vlan_promisc(pf, 0);
0727     }
0728 
0729     if (changed & NETIF_F_LOOPBACK)
0730         enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
0731 
0732     enetc_set_features(ndev, features);
0733 
0734     return 0;
0735 }
0736 
0737 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
0738                  void *type_data)
0739 {
0740     switch (type) {
0741     case TC_SETUP_QDISC_MQPRIO:
0742         return enetc_setup_tc_mqprio(ndev, type_data);
0743     case TC_SETUP_QDISC_TAPRIO:
0744         return enetc_setup_tc_taprio(ndev, type_data);
0745     case TC_SETUP_QDISC_CBS:
0746         return enetc_setup_tc_cbs(ndev, type_data);
0747     case TC_SETUP_QDISC_ETF:
0748         return enetc_setup_tc_txtime(ndev, type_data);
0749     case TC_SETUP_BLOCK:
0750         return enetc_setup_tc_psfp(ndev, type_data);
0751     default:
0752         return -EOPNOTSUPP;
0753     }
0754 }
0755 
0756 static const struct net_device_ops enetc_ndev_ops = {
0757     .ndo_open       = enetc_open,
0758     .ndo_stop       = enetc_close,
0759     .ndo_start_xmit     = enetc_xmit,
0760     .ndo_get_stats      = enetc_get_stats,
0761     .ndo_set_mac_address    = enetc_pf_set_mac_addr,
0762     .ndo_set_rx_mode    = enetc_pf_set_rx_mode,
0763     .ndo_vlan_rx_add_vid    = enetc_vlan_rx_add_vid,
0764     .ndo_vlan_rx_kill_vid   = enetc_vlan_rx_del_vid,
0765     .ndo_set_vf_mac     = enetc_pf_set_vf_mac,
0766     .ndo_set_vf_vlan    = enetc_pf_set_vf_vlan,
0767     .ndo_set_vf_spoofchk    = enetc_pf_set_vf_spoofchk,
0768     .ndo_set_features   = enetc_pf_set_features,
0769     .ndo_eth_ioctl      = enetc_ioctl,
0770     .ndo_setup_tc       = enetc_pf_setup_tc,
0771     .ndo_bpf        = enetc_setup_bpf,
0772     .ndo_xdp_xmit       = enetc_xdp_xmit,
0773 };
0774 
0775 static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
0776                   const struct net_device_ops *ndev_ops)
0777 {
0778     struct enetc_ndev_priv *priv = netdev_priv(ndev);
0779 
0780     SET_NETDEV_DEV(ndev, &si->pdev->dev);
0781     priv->ndev = ndev;
0782     priv->si = si;
0783     priv->dev = &si->pdev->dev;
0784     si->ndev = ndev;
0785 
0786     priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
0787     ndev->netdev_ops = ndev_ops;
0788     enetc_set_ethtool_ops(ndev);
0789     ndev->watchdog_timeo = 5 * HZ;
0790     ndev->max_mtu = ENETC_MAX_MTU;
0791 
0792     ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
0793                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
0794                 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |
0795                 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
0796     ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
0797              NETIF_F_HW_VLAN_CTAG_TX |
0798              NETIF_F_HW_VLAN_CTAG_RX |
0799              NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
0800     ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |
0801                   NETIF_F_TSO | NETIF_F_TSO6;
0802 
0803     if (si->num_rss)
0804         ndev->hw_features |= NETIF_F_RXHASH;
0805 
0806     ndev->priv_flags |= IFF_UNICAST_FLT;
0807 
0808     if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
0809         priv->active_offloads |= ENETC_F_QCI;
0810         ndev->features |= NETIF_F_HW_TC;
0811         ndev->hw_features |= NETIF_F_HW_TC;
0812     }
0813 
0814     /* pick up primary MAC address from SI */
0815     enetc_load_primary_mac_addr(&si->hw, ndev);
0816 }
0817 
0818 static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
0819 {
0820     struct device *dev = &pf->si->pdev->dev;
0821     struct enetc_mdio_priv *mdio_priv;
0822     struct mii_bus *bus;
0823     int err;
0824 
0825     bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
0826     if (!bus)
0827         return -ENOMEM;
0828 
0829     bus->name = "Freescale ENETC MDIO Bus";
0830     bus->read = enetc_mdio_read;
0831     bus->write = enetc_mdio_write;
0832     bus->parent = dev;
0833     mdio_priv = bus->priv;
0834     mdio_priv->hw = &pf->si->hw;
0835     mdio_priv->mdio_base = ENETC_EMDIO_BASE;
0836     snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
0837 
0838     err = of_mdiobus_register(bus, np);
0839     if (err)
0840         return dev_err_probe(dev, err, "cannot register MDIO bus\n");
0841 
0842     pf->mdio = bus;
0843 
0844     return 0;
0845 }
0846 
0847 static void enetc_mdio_remove(struct enetc_pf *pf)
0848 {
0849     if (pf->mdio)
0850         mdiobus_unregister(pf->mdio);
0851 }
0852 
0853 static int enetc_imdio_create(struct enetc_pf *pf)
0854 {
0855     struct device *dev = &pf->si->pdev->dev;
0856     struct enetc_mdio_priv *mdio_priv;
0857     struct phylink_pcs *phylink_pcs;
0858     struct mdio_device *mdio_device;
0859     struct mii_bus *bus;
0860     int err;
0861 
0862     bus = mdiobus_alloc_size(sizeof(*mdio_priv));
0863     if (!bus)
0864         return -ENOMEM;
0865 
0866     bus->name = "Freescale ENETC internal MDIO Bus";
0867     bus->read = enetc_mdio_read;
0868     bus->write = enetc_mdio_write;
0869     bus->parent = dev;
0870     bus->phy_mask = ~0;
0871     mdio_priv = bus->priv;
0872     mdio_priv->hw = &pf->si->hw;
0873     mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
0874     snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
0875 
0876     err = mdiobus_register(bus);
0877     if (err) {
0878         dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
0879         goto free_mdio_bus;
0880     }
0881 
0882     mdio_device = mdio_device_create(bus, 0);
0883     if (IS_ERR(mdio_device)) {
0884         err = PTR_ERR(mdio_device);
0885         dev_err(dev, "cannot create mdio device (%d)\n", err);
0886         goto unregister_mdiobus;
0887     }
0888 
0889     phylink_pcs = lynx_pcs_create(mdio_device);
0890     if (!phylink_pcs) {
0891         mdio_device_free(mdio_device);
0892         err = -ENOMEM;
0893         dev_err(dev, "cannot create lynx pcs (%d)\n", err);
0894         goto unregister_mdiobus;
0895     }
0896 
0897     pf->imdio = bus;
0898     pf->pcs = phylink_pcs;
0899 
0900     return 0;
0901 
0902 unregister_mdiobus:
0903     mdiobus_unregister(bus);
0904 free_mdio_bus:
0905     mdiobus_free(bus);
0906     return err;
0907 }
0908 
0909 static void enetc_imdio_remove(struct enetc_pf *pf)
0910 {
0911     struct mdio_device *mdio_device;
0912 
0913     if (pf->pcs) {
0914         mdio_device = lynx_get_mdio_device(pf->pcs);
0915         mdio_device_free(mdio_device);
0916         lynx_pcs_destroy(pf->pcs);
0917     }
0918     if (pf->imdio) {
0919         mdiobus_unregister(pf->imdio);
0920         mdiobus_free(pf->imdio);
0921     }
0922 }
0923 
0924 static bool enetc_port_has_pcs(struct enetc_pf *pf)
0925 {
0926     return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
0927         pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
0928         pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
0929 }
0930 
0931 static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
0932 {
0933     struct device_node *mdio_np;
0934     int err;
0935 
0936     mdio_np = of_get_child_by_name(node, "mdio");
0937     if (mdio_np) {
0938         err = enetc_mdio_probe(pf, mdio_np);
0939 
0940         of_node_put(mdio_np);
0941         if (err)
0942             return err;
0943     }
0944 
0945     if (enetc_port_has_pcs(pf)) {
0946         err = enetc_imdio_create(pf);
0947         if (err) {
0948             enetc_mdio_remove(pf);
0949             return err;
0950         }
0951     }
0952 
0953     return 0;
0954 }
0955 
0956 static void enetc_mdiobus_destroy(struct enetc_pf *pf)
0957 {
0958     enetc_mdio_remove(pf);
0959     enetc_imdio_remove(pf);
0960 }
0961 
0962 static struct phylink_pcs *
0963 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
0964 {
0965     struct enetc_pf *pf = phylink_to_enetc_pf(config);
0966 
0967     return pf->pcs;
0968 }
0969 
0970 static void enetc_pl_mac_config(struct phylink_config *config,
0971                 unsigned int mode,
0972                 const struct phylink_link_state *state)
0973 {
0974     struct enetc_pf *pf = phylink_to_enetc_pf(config);
0975 
0976     enetc_mac_config(&pf->si->hw, state->interface);
0977 }
0978 
0979 static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
0980 {
0981     u32 old_val, val;
0982 
0983     old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
0984 
0985     if (speed == SPEED_1000) {
0986         val &= ~ENETC_PM0_IFM_SSP_MASK;
0987         val |= ENETC_PM0_IFM_SSP_1000;
0988     } else if (speed == SPEED_100) {
0989         val &= ~ENETC_PM0_IFM_SSP_MASK;
0990         val |= ENETC_PM0_IFM_SSP_100;
0991     } else if (speed == SPEED_10) {
0992         val &= ~ENETC_PM0_IFM_SSP_MASK;
0993         val |= ENETC_PM0_IFM_SSP_10;
0994     }
0995 
0996     if (duplex == DUPLEX_FULL)
0997         val |= ENETC_PM0_IFM_FULL_DPX;
0998     else
0999         val &= ~ENETC_PM0_IFM_FULL_DPX;
1000 
1001     if (val == old_val)
1002         return;
1003 
1004     enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
1005 }
1006 
1007 static void enetc_pl_mac_link_up(struct phylink_config *config,
1008                  struct phy_device *phy, unsigned int mode,
1009                  phy_interface_t interface, int speed,
1010                  int duplex, bool tx_pause, bool rx_pause)
1011 {
1012     struct enetc_pf *pf = phylink_to_enetc_pf(config);
1013     u32 pause_off_thresh = 0, pause_on_thresh = 0;
1014     u32 init_quanta = 0, refresh_quanta = 0;
1015     struct enetc_hw *hw = &pf->si->hw;
1016     struct enetc_ndev_priv *priv;
1017     u32 rbmr, cmd_cfg;
1018     int idx;
1019 
1020     priv = netdev_priv(pf->si->ndev);
1021 
1022     if (pf->si->hw_features & ENETC_SI_F_QBV)
1023         enetc_sched_speed_set(priv, speed);
1024 
1025     if (!phylink_autoneg_inband(mode) &&
1026         phy_interface_mode_is_rgmii(interface))
1027         enetc_force_rgmii_mac(hw, speed, duplex);
1028 
1029     /* Flow control */
1030     for (idx = 0; idx < priv->num_rx_rings; idx++) {
1031         rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1032 
1033         if (tx_pause)
1034             rbmr |= ENETC_RBMR_CM;
1035         else
1036             rbmr &= ~ENETC_RBMR_CM;
1037 
1038         enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1039     }
1040 
1041     if (tx_pause) {
1042         /* When the port first enters congestion, send a PAUSE request
1043          * with the maximum number of quanta. When the port exits
1044          * congestion, it will automatically send a PAUSE frame with
1045          * zero quanta.
1046          */
1047         init_quanta = 0xffff;
1048 
1049         /* Also, set up the refresh timer to send follow-up PAUSE
1050          * frames at half the quanta value, in case the congestion
1051          * condition persists.
1052          */
1053         refresh_quanta = 0xffff / 2;
1054 
1055         /* Start emitting PAUSE frames when 3 large frames (or more
1056          * smaller frames) have accumulated in the FIFO waiting to be
1057          * DMAed to the RX ring.
1058          */
1059         pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1060         pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1061     }
1062 
1063     enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1064     enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
1065     enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1066     enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
1067     enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1068     enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1069 
1070     cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
1071 
1072     if (rx_pause)
1073         cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1074     else
1075         cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1076 
1077     enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
1078     enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
1079 
1080     enetc_mac_enable(hw, true);
1081 }
1082 
1083 static void enetc_pl_mac_link_down(struct phylink_config *config,
1084                    unsigned int mode,
1085                    phy_interface_t interface)
1086 {
1087     struct enetc_pf *pf = phylink_to_enetc_pf(config);
1088 
1089     enetc_mac_enable(&pf->si->hw, false);
1090 }
1091 
1092 static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1093     .validate = phylink_generic_validate,
1094     .mac_select_pcs = enetc_pl_mac_select_pcs,
1095     .mac_config = enetc_pl_mac_config,
1096     .mac_link_up = enetc_pl_mac_link_up,
1097     .mac_link_down = enetc_pl_mac_link_down,
1098 };
1099 
1100 static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1101                 struct device_node *node)
1102 {
1103     struct enetc_pf *pf = enetc_si_priv(priv->si);
1104     struct phylink *phylink;
1105     int err;
1106 
1107     pf->phylink_config.dev = &priv->ndev->dev;
1108     pf->phylink_config.type = PHYLINK_NETDEV;
1109     pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1110         MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1111 
1112     __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1113           pf->phylink_config.supported_interfaces);
1114     __set_bit(PHY_INTERFACE_MODE_SGMII,
1115           pf->phylink_config.supported_interfaces);
1116     __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1117           pf->phylink_config.supported_interfaces);
1118     __set_bit(PHY_INTERFACE_MODE_USXGMII,
1119           pf->phylink_config.supported_interfaces);
1120     phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);
1121 
1122     phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1123                  pf->if_mode, &enetc_mac_phylink_ops);
1124     if (IS_ERR(phylink)) {
1125         err = PTR_ERR(phylink);
1126         return err;
1127     }
1128 
1129     priv->phylink = phylink;
1130 
1131     return 0;
1132 }
1133 
1134 static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1135 {
1136     phylink_destroy(priv->phylink);
1137 }
1138 
1139 /* Initialize the entire shared memory for the flow steering entries
1140  * of this port (PF + VFs)
1141  */
1142 static int enetc_init_port_rfs_memory(struct enetc_si *si)
1143 {
1144     struct enetc_cmd_rfse rfse = {0};
1145     struct enetc_hw *hw = &si->hw;
1146     int num_rfs, i, err = 0;
1147     u32 val;
1148 
1149     val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1150     num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1151 
1152     for (i = 0; i < num_rfs; i++) {
1153         err = enetc_set_fs_entry(si, &rfse, i);
1154         if (err)
1155             break;
1156     }
1157 
1158     return err;
1159 }
1160 
1161 static int enetc_init_port_rss_memory(struct enetc_si *si)
1162 {
1163     struct enetc_hw *hw = &si->hw;
1164     int num_rss, err;
1165     int *rss_table;
1166     u32 val;
1167 
1168     val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1169     num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1170     if (!num_rss)
1171         return 0;
1172 
1173     rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1174     if (!rss_table)
1175         return -ENOMEM;
1176 
1177     err = enetc_set_rss_table(si, rss_table, num_rss);
1178 
1179     kfree(rss_table);
1180 
1181     return err;
1182 }
1183 
1184 static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1185 {
1186     struct device_node *node = pdev->dev.of_node;
1187     struct platform_device *ierb_pdev;
1188     struct device_node *ierb_node;
1189 
1190     /* Don't register with the IERB if the PF itself is disabled */
1191     if (!node || !of_device_is_available(node))
1192         return 0;
1193 
1194     ierb_node = of_find_compatible_node(NULL, NULL,
1195                         "fsl,ls1028a-enetc-ierb");
1196     if (!ierb_node || !of_device_is_available(ierb_node))
1197         return -ENODEV;
1198 
1199     ierb_pdev = of_find_device_by_node(ierb_node);
1200     of_node_put(ierb_node);
1201 
1202     if (!ierb_pdev)
1203         return -EPROBE_DEFER;
1204 
1205     return enetc_ierb_register_pf(ierb_pdev, pdev);
1206 }
1207 
1208 static int enetc_pf_probe(struct pci_dev *pdev,
1209               const struct pci_device_id *ent)
1210 {
1211     struct device_node *node = pdev->dev.of_node;
1212     struct enetc_ndev_priv *priv;
1213     struct net_device *ndev;
1214     struct enetc_si *si;
1215     struct enetc_pf *pf;
1216     int err;
1217 
1218     err = enetc_pf_register_with_ierb(pdev);
1219     if (err == -EPROBE_DEFER)
1220         return err;
1221     if (err)
1222         dev_warn(&pdev->dev,
1223              "Could not register with IERB driver: %pe, please update the device tree\n",
1224              ERR_PTR(err));
1225 
1226     err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1227     if (err)
1228         return dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
1229 
1230     si = pci_get_drvdata(pdev);
1231     if (!si->hw.port || !si->hw.global) {
1232         err = -ENODEV;
1233         dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1234         goto err_map_pf_space;
1235     }
1236 
1237     err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1238                    &si->cbd_ring);
1239     if (err)
1240         goto err_setup_cbdr;
1241 
1242     err = enetc_init_port_rfs_memory(si);
1243     if (err) {
1244         dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1245         goto err_init_port_rfs;
1246     }
1247 
1248     err = enetc_init_port_rss_memory(si);
1249     if (err) {
1250         dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1251         goto err_init_port_rss;
1252     }
1253 
1254     if (node && !of_device_is_available(node)) {
1255         dev_info(&pdev->dev, "device is disabled, skipping\n");
1256         err = -ENODEV;
1257         goto err_device_disabled;
1258     }
1259 
1260     pf = enetc_si_priv(si);
1261     pf->si = si;
1262     pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1263 
1264     err = enetc_setup_mac_addresses(node, pf);
1265     if (err)
1266         goto err_setup_mac_addresses;
1267 
1268     enetc_configure_port(pf);
1269 
1270     enetc_get_si_caps(si);
1271 
1272     ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1273     if (!ndev) {
1274         err = -ENOMEM;
1275         dev_err(&pdev->dev, "netdev creation failed\n");
1276         goto err_alloc_netdev;
1277     }
1278 
1279     enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1280 
1281     priv = netdev_priv(ndev);
1282 
1283     enetc_init_si_rings_params(priv);
1284 
1285     err = enetc_alloc_si_resources(priv);
1286     if (err) {
1287         dev_err(&pdev->dev, "SI resource alloc failed\n");
1288         goto err_alloc_si_res;
1289     }
1290 
1291     err = enetc_configure_si(priv);
1292     if (err) {
1293         dev_err(&pdev->dev, "Failed to configure SI\n");
1294         goto err_config_si;
1295     }
1296 
1297     err = enetc_alloc_msix(priv);
1298     if (err) {
1299         dev_err(&pdev->dev, "MSIX alloc failed\n");
1300         goto err_alloc_msix;
1301     }
1302 
1303     err = of_get_phy_mode(node, &pf->if_mode);
1304     if (err) {
1305         dev_err(&pdev->dev, "Failed to read PHY mode\n");
1306         goto err_phy_mode;
1307     }
1308 
1309     err = enetc_mdiobus_create(pf, node);
1310     if (err)
1311         goto err_mdiobus_create;
1312 
1313     err = enetc_phylink_create(priv, node);
1314     if (err)
1315         goto err_phylink_create;
1316 
1317     err = register_netdev(ndev);
1318     if (err)
1319         goto err_reg_netdev;
1320 
1321     return 0;
1322 
1323 err_reg_netdev:
1324     enetc_phylink_destroy(priv);
1325 err_phylink_create:
1326     enetc_mdiobus_destroy(pf);
1327 err_mdiobus_create:
1328 err_phy_mode:
1329     enetc_free_msix(priv);
1330 err_config_si:
1331 err_alloc_msix:
1332     enetc_free_si_resources(priv);
1333 err_alloc_si_res:
1334     si->ndev = NULL;
1335     free_netdev(ndev);
1336 err_alloc_netdev:
1337 err_init_port_rss:
1338 err_init_port_rfs:
1339 err_device_disabled:
1340 err_setup_mac_addresses:
1341     enetc_teardown_cbdr(&si->cbd_ring);
1342 err_setup_cbdr:
1343 err_map_pf_space:
1344     enetc_pci_remove(pdev);
1345 
1346     return err;
1347 }
1348 
1349 static void enetc_pf_remove(struct pci_dev *pdev)
1350 {
1351     struct enetc_si *si = pci_get_drvdata(pdev);
1352     struct enetc_pf *pf = enetc_si_priv(si);
1353     struct enetc_ndev_priv *priv;
1354 
1355     priv = netdev_priv(si->ndev);
1356 
1357     if (pf->num_vfs)
1358         enetc_sriov_configure(pdev, 0);
1359 
1360     unregister_netdev(si->ndev);
1361 
1362     enetc_phylink_destroy(priv);
1363     enetc_mdiobus_destroy(pf);
1364 
1365     enetc_free_msix(priv);
1366 
1367     enetc_free_si_resources(priv);
1368     enetc_teardown_cbdr(&si->cbd_ring);
1369 
1370     free_netdev(si->ndev);
1371 
1372     enetc_pci_remove(pdev);
1373 }
1374 
1375 static const struct pci_device_id enetc_pf_id_table[] = {
1376     { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1377     { 0, } /* End of table. */
1378 };
1379 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1380 
1381 static struct pci_driver enetc_pf_driver = {
1382     .name = KBUILD_MODNAME,
1383     .id_table = enetc_pf_id_table,
1384     .probe = enetc_pf_probe,
1385     .remove = enetc_pf_remove,
1386 #ifdef CONFIG_PCI_IOV
1387     .sriov_configure = enetc_sriov_configure,
1388 #endif
1389 };
1390 module_pci_driver(enetc_pf_driver);
1391 
1392 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1393 MODULE_LICENSE("Dual BSD/GPL");
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