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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2014-2016 Freescale Semiconductor Inc.
0004  * Copyright 2017-2021 NXP
0005  *
0006  */
0007 
0008 #ifndef __FSL_DPSW_CMD_H
0009 #define __FSL_DPSW_CMD_H
0010 
0011 #include "dpsw.h"
0012 
0013 /* DPSW Version */
0014 #define DPSW_VER_MAJOR      8
0015 #define DPSW_VER_MINOR      9
0016 
0017 #define DPSW_CMD_BASE_VERSION   1
0018 #define DPSW_CMD_VERSION_2  2
0019 #define DPSW_CMD_ID_OFFSET  4
0020 
0021 #define DPSW_CMD_ID(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION)
0022 #define DPSW_CMD_V2(id) (((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_VERSION_2)
0023 
0024 /* Command IDs */
0025 #define DPSW_CMDID_CLOSE                    DPSW_CMD_ID(0x800)
0026 #define DPSW_CMDID_OPEN                     DPSW_CMD_ID(0x802)
0027 
0028 #define DPSW_CMDID_GET_API_VERSION          DPSW_CMD_ID(0xa02)
0029 
0030 #define DPSW_CMDID_ENABLE                   DPSW_CMD_ID(0x002)
0031 #define DPSW_CMDID_DISABLE                  DPSW_CMD_ID(0x003)
0032 #define DPSW_CMDID_GET_ATTR                 DPSW_CMD_V2(0x004)
0033 #define DPSW_CMDID_RESET                    DPSW_CMD_ID(0x005)
0034 
0035 #define DPSW_CMDID_SET_IRQ_ENABLE           DPSW_CMD_ID(0x012)
0036 
0037 #define DPSW_CMDID_SET_IRQ_MASK             DPSW_CMD_ID(0x014)
0038 
0039 #define DPSW_CMDID_GET_IRQ_STATUS           DPSW_CMD_ID(0x016)
0040 #define DPSW_CMDID_CLEAR_IRQ_STATUS         DPSW_CMD_ID(0x017)
0041 
0042 #define DPSW_CMDID_SET_REFLECTION_IF        DPSW_CMD_ID(0x022)
0043 
0044 #define DPSW_CMDID_IF_SET_TCI               DPSW_CMD_ID(0x030)
0045 #define DPSW_CMDID_IF_SET_STP               DPSW_CMD_ID(0x031)
0046 
0047 #define DPSW_CMDID_IF_GET_COUNTER           DPSW_CMD_V2(0x034)
0048 
0049 #define DPSW_CMDID_IF_ADD_REFLECTION        DPSW_CMD_ID(0x037)
0050 #define DPSW_CMDID_IF_REMOVE_REFLECTION     DPSW_CMD_ID(0x038)
0051 
0052 #define DPSW_CMDID_IF_ENABLE                DPSW_CMD_ID(0x03D)
0053 #define DPSW_CMDID_IF_DISABLE               DPSW_CMD_ID(0x03E)
0054 
0055 #define DPSW_CMDID_IF_GET_ATTR              DPSW_CMD_ID(0x042)
0056 
0057 #define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH  DPSW_CMD_ID(0x044)
0058 
0059 #define DPSW_CMDID_IF_GET_LINK_STATE        DPSW_CMD_ID(0x046)
0060 
0061 #define DPSW_CMDID_IF_GET_TCI               DPSW_CMD_ID(0x04A)
0062 
0063 #define DPSW_CMDID_IF_SET_LINK_CFG          DPSW_CMD_ID(0x04C)
0064 
0065 #define DPSW_CMDID_VLAN_ADD                 DPSW_CMD_ID(0x060)
0066 #define DPSW_CMDID_VLAN_ADD_IF              DPSW_CMD_V2(0x061)
0067 #define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED     DPSW_CMD_ID(0x062)
0068 
0069 #define DPSW_CMDID_VLAN_REMOVE_IF           DPSW_CMD_ID(0x064)
0070 #define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED  DPSW_CMD_ID(0x065)
0071 #define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING  DPSW_CMD_ID(0x066)
0072 #define DPSW_CMDID_VLAN_REMOVE              DPSW_CMD_ID(0x067)
0073 
0074 #define DPSW_CMDID_FDB_ADD                  DPSW_CMD_ID(0x082)
0075 #define DPSW_CMDID_FDB_REMOVE               DPSW_CMD_ID(0x083)
0076 #define DPSW_CMDID_FDB_ADD_UNICAST          DPSW_CMD_ID(0x084)
0077 #define DPSW_CMDID_FDB_REMOVE_UNICAST       DPSW_CMD_ID(0x085)
0078 #define DPSW_CMDID_FDB_ADD_MULTICAST        DPSW_CMD_ID(0x086)
0079 #define DPSW_CMDID_FDB_REMOVE_MULTICAST     DPSW_CMD_ID(0x087)
0080 #define DPSW_CMDID_FDB_DUMP                 DPSW_CMD_ID(0x08A)
0081 
0082 #define DPSW_CMDID_ACL_ADD                  DPSW_CMD_ID(0x090)
0083 #define DPSW_CMDID_ACL_REMOVE               DPSW_CMD_ID(0x091)
0084 #define DPSW_CMDID_ACL_ADD_ENTRY            DPSW_CMD_ID(0x092)
0085 #define DPSW_CMDID_ACL_REMOVE_ENTRY         DPSW_CMD_ID(0x093)
0086 #define DPSW_CMDID_ACL_ADD_IF               DPSW_CMD_ID(0x094)
0087 #define DPSW_CMDID_ACL_REMOVE_IF            DPSW_CMD_ID(0x095)
0088 
0089 #define DPSW_CMDID_IF_GET_PORT_MAC_ADDR     DPSW_CMD_ID(0x0A7)
0090 
0091 #define DPSW_CMDID_CTRL_IF_GET_ATTR         DPSW_CMD_ID(0x0A0)
0092 #define DPSW_CMDID_CTRL_IF_SET_POOLS        DPSW_CMD_ID(0x0A1)
0093 #define DPSW_CMDID_CTRL_IF_ENABLE           DPSW_CMD_ID(0x0A2)
0094 #define DPSW_CMDID_CTRL_IF_DISABLE          DPSW_CMD_ID(0x0A3)
0095 #define DPSW_CMDID_CTRL_IF_SET_QUEUE        DPSW_CMD_ID(0x0A6)
0096 
0097 #define DPSW_CMDID_SET_EGRESS_FLOOD         DPSW_CMD_ID(0x0AC)
0098 #define DPSW_CMDID_IF_SET_LEARNING_MODE     DPSW_CMD_ID(0x0AD)
0099 
0100 /* Macros for accessing command fields smaller than 1byte */
0101 #define DPSW_MASK(field)        \
0102     GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
0103         DPSW_##field##_SHIFT)
0104 #define dpsw_set_field(var, field, val) \
0105     ((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field)))
0106 #define dpsw_get_field(var, field)      \
0107     (((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT)
0108 #define dpsw_get_bit(var, bit) \
0109     (((var)  >> (bit)) & GENMASK(0, 0))
0110 
0111 #pragma pack(push, 1)
0112 struct dpsw_cmd_open {
0113     __le32 dpsw_id;
0114 };
0115 
0116 #define DPSW_COMPONENT_TYPE_SHIFT   0
0117 #define DPSW_COMPONENT_TYPE_SIZE    4
0118 
0119 struct dpsw_cmd_create {
0120     /* cmd word 0 */
0121     __le16 num_ifs;
0122     u8 max_fdbs;
0123     u8 max_meters_per_if;
0124     /* from LSB: only the first 4 bits */
0125     u8 component_type;
0126     u8 pad[3];
0127     /* cmd word 1 */
0128     __le16 max_vlans;
0129     __le16 max_fdb_entries;
0130     __le16 fdb_aging_time;
0131     __le16 max_fdb_mc_groups;
0132     /* cmd word 2 */
0133     __le64 options;
0134 };
0135 
0136 struct dpsw_cmd_destroy {
0137     __le32 dpsw_id;
0138 };
0139 
0140 #define DPSW_ENABLE_SHIFT 0
0141 #define DPSW_ENABLE_SIZE  1
0142 
0143 struct dpsw_rsp_is_enabled {
0144     /* from LSB: enable:1 */
0145     u8 enabled;
0146 };
0147 
0148 struct dpsw_cmd_set_irq_enable {
0149     u8 enable_state;
0150     u8 pad[3];
0151     u8 irq_index;
0152 };
0153 
0154 struct dpsw_cmd_get_irq_enable {
0155     __le32 pad;
0156     u8 irq_index;
0157 };
0158 
0159 struct dpsw_rsp_get_irq_enable {
0160     u8 enable_state;
0161 };
0162 
0163 struct dpsw_cmd_set_irq_mask {
0164     __le32 mask;
0165     u8 irq_index;
0166 };
0167 
0168 struct dpsw_cmd_get_irq_mask {
0169     __le32 pad;
0170     u8 irq_index;
0171 };
0172 
0173 struct dpsw_rsp_get_irq_mask {
0174     __le32 mask;
0175 };
0176 
0177 struct dpsw_cmd_get_irq_status {
0178     __le32 status;
0179     u8 irq_index;
0180 };
0181 
0182 struct dpsw_rsp_get_irq_status {
0183     __le32 status;
0184 };
0185 
0186 struct dpsw_cmd_clear_irq_status {
0187     __le32 status;
0188     u8 irq_index;
0189 };
0190 
0191 #define DPSW_COMPONENT_TYPE_SHIFT   0
0192 #define DPSW_COMPONENT_TYPE_SIZE    4
0193 
0194 #define DPSW_FLOODING_CFG_SHIFT     0
0195 #define DPSW_FLOODING_CFG_SIZE      4
0196 
0197 #define DPSW_BROADCAST_CFG_SHIFT    4
0198 #define DPSW_BROADCAST_CFG_SIZE     4
0199 
0200 struct dpsw_rsp_get_attr {
0201     /* cmd word 0 */
0202     __le16 num_ifs;
0203     u8 max_fdbs;
0204     u8 num_fdbs;
0205     __le16 max_vlans;
0206     __le16 num_vlans;
0207     /* cmd word 1 */
0208     __le16 max_fdb_entries;
0209     __le16 fdb_aging_time;
0210     __le32 dpsw_id;
0211     /* cmd word 2 */
0212     __le16 mem_size;
0213     __le16 max_fdb_mc_groups;
0214     u8 max_meters_per_if;
0215     /* from LSB only the first 4 bits */
0216     u8 component_type;
0217     /* [0:3] - flooding configuration
0218      * [4:7] - broadcast configuration
0219      */
0220     u8 repl_cfg;
0221     u8 pad;
0222     /* cmd word 3 */
0223     __le64 options;
0224 };
0225 
0226 #define DPSW_VLAN_ID_SHIFT  0
0227 #define DPSW_VLAN_ID_SIZE   12
0228 #define DPSW_DEI_SHIFT      12
0229 #define DPSW_DEI_SIZE       1
0230 #define DPSW_PCP_SHIFT      13
0231 #define DPSW_PCP_SIZE       3
0232 
0233 struct dpsw_cmd_if_set_tci {
0234     __le16 if_id;
0235     /* from LSB: VLAN_ID:12 DEI:1 PCP:3 */
0236     __le16 conf;
0237 };
0238 
0239 struct dpsw_cmd_if_get_tci {
0240     __le16 if_id;
0241 };
0242 
0243 struct dpsw_rsp_if_get_tci {
0244     __le16 pad;
0245     __le16 vlan_id;
0246     u8 dei;
0247     u8 pcp;
0248 };
0249 
0250 #define DPSW_STATE_SHIFT    0
0251 #define DPSW_STATE_SIZE     4
0252 
0253 struct dpsw_cmd_if_set_stp {
0254     __le16 if_id;
0255     __le16 vlan_id;
0256     /* only the first LSB 4 bits */
0257     u8 state;
0258 };
0259 
0260 #define DPSW_COUNTER_TYPE_SHIFT     0
0261 #define DPSW_COUNTER_TYPE_SIZE      5
0262 
0263 struct dpsw_cmd_if_get_counter {
0264     __le16 if_id;
0265     /* from LSB: type:5 */
0266     u8 type;
0267 };
0268 
0269 struct dpsw_rsp_if_get_counter {
0270     __le64 pad;
0271     __le64 counter;
0272 };
0273 
0274 struct dpsw_cmd_if {
0275     __le16 if_id;
0276 };
0277 
0278 #define DPSW_ADMIT_UNTAGGED_SHIFT   0
0279 #define DPSW_ADMIT_UNTAGGED_SIZE    4
0280 #define DPSW_ENABLED_SHIFT      5
0281 #define DPSW_ENABLED_SIZE       1
0282 #define DPSW_ACCEPT_ALL_VLAN_SHIFT  6
0283 #define DPSW_ACCEPT_ALL_VLAN_SIZE   1
0284 
0285 struct dpsw_rsp_if_get_attr {
0286     /* cmd word 0 */
0287     /* from LSB: admit_untagged:4 enabled:1 accept_all_vlan:1 */
0288     u8 conf;
0289     u8 pad1;
0290     u8 num_tcs;
0291     u8 pad2;
0292     __le16 qdid;
0293     /* cmd word 1 */
0294     __le32 options;
0295     __le32 pad3;
0296     /* cmd word 2 */
0297     __le32 rate;
0298 };
0299 
0300 struct dpsw_cmd_if_set_max_frame_length {
0301     __le16 if_id;
0302     __le16 frame_length;
0303 };
0304 
0305 struct dpsw_cmd_if_set_link_cfg {
0306     /* cmd word 0 */
0307     __le16 if_id;
0308     u8 pad[6];
0309     /* cmd word 1 */
0310     __le32 rate;
0311     __le32 pad1;
0312     /* cmd word 2 */
0313     __le64 options;
0314 };
0315 
0316 struct dpsw_cmd_if_get_link_state {
0317     __le16 if_id;
0318 };
0319 
0320 #define DPSW_UP_SHIFT   0
0321 #define DPSW_UP_SIZE    1
0322 
0323 struct dpsw_rsp_if_get_link_state {
0324     /* cmd word 0 */
0325     __le32 pad0;
0326     u8 up;
0327     u8 pad1[3];
0328     /* cmd word 1 */
0329     __le32 rate;
0330     __le32 pad2;
0331     /* cmd word 2 */
0332     __le64 options;
0333 };
0334 
0335 struct dpsw_vlan_add {
0336     __le16 fdb_id;
0337     __le16 vlan_id;
0338 };
0339 
0340 struct dpsw_cmd_vlan_add_if {
0341     /* cmd word 0 */
0342     __le16 options;
0343     __le16 vlan_id;
0344     __le16 fdb_id;
0345     __le16 pad0;
0346     /* cmd word 1-4 */
0347     __le64 if_id;
0348 };
0349 
0350 struct dpsw_cmd_vlan_manage_if {
0351     /* cmd word 0 */
0352     __le16 pad0;
0353     __le16 vlan_id;
0354     __le32 pad1;
0355     /* cmd word 1-4 */
0356     __le64 if_id;
0357 };
0358 
0359 struct dpsw_cmd_vlan_remove {
0360     __le16 pad;
0361     __le16 vlan_id;
0362 };
0363 
0364 struct dpsw_cmd_fdb_add {
0365     __le32 pad;
0366     __le16 fdb_ageing_time;
0367     __le16 num_fdb_entries;
0368 };
0369 
0370 struct dpsw_rsp_fdb_add {
0371     __le16 fdb_id;
0372 };
0373 
0374 struct dpsw_cmd_fdb_remove {
0375     __le16 fdb_id;
0376 };
0377 
0378 #define DPSW_ENTRY_TYPE_SHIFT   0
0379 #define DPSW_ENTRY_TYPE_SIZE    4
0380 
0381 struct dpsw_cmd_fdb_unicast_op {
0382     /* cmd word 0 */
0383     __le16 fdb_id;
0384     u8 mac_addr[6];
0385     /* cmd word 1 */
0386     __le16 if_egress;
0387     /* only the first 4 bits from LSB */
0388     u8 type;
0389 };
0390 
0391 struct dpsw_cmd_fdb_multicast_op {
0392     /* cmd word 0 */
0393     __le16 fdb_id;
0394     __le16 num_ifs;
0395     /* only the first 4 bits from LSB */
0396     u8 type;
0397     u8 pad[3];
0398     /* cmd word 1 */
0399     u8 mac_addr[6];
0400     __le16 pad2;
0401     /* cmd word 2-5 */
0402     __le64 if_id;
0403 };
0404 
0405 struct dpsw_cmd_fdb_dump {
0406     __le16 fdb_id;
0407     __le16 pad0;
0408     __le32 pad1;
0409     __le64 iova_addr;
0410     __le32 iova_size;
0411 };
0412 
0413 struct dpsw_rsp_fdb_dump {
0414     __le16 num_entries;
0415 };
0416 
0417 struct dpsw_rsp_ctrl_if_get_attr {
0418     __le64 pad;
0419     __le32 rx_fqid;
0420     __le32 rx_err_fqid;
0421     __le32 tx_err_conf_fqid;
0422 };
0423 
0424 #define DPSW_BACKUP_POOL(val, order)    (((val) & 0x1) << (order))
0425 struct dpsw_cmd_ctrl_if_set_pools {
0426     u8 num_dpbp;
0427     u8 backup_pool_mask;
0428     __le16 pad;
0429     __le32 dpbp_id[DPSW_MAX_DPBP];
0430     __le16 buffer_size[DPSW_MAX_DPBP];
0431 };
0432 
0433 #define DPSW_DEST_TYPE_SHIFT    0
0434 #define DPSW_DEST_TYPE_SIZE 4
0435 
0436 struct dpsw_cmd_ctrl_if_set_queue {
0437     __le32 dest_id;
0438     u8 dest_priority;
0439     u8 pad;
0440     /* from LSB: dest_type:4 */
0441     u8 dest_type;
0442     u8 qtype;
0443     __le64 user_ctx;
0444     __le32 options;
0445 };
0446 
0447 struct dpsw_rsp_get_api_version {
0448     __le16 version_major;
0449     __le16 version_minor;
0450 };
0451 
0452 struct dpsw_rsp_if_get_mac_addr {
0453     __le16 pad;
0454     u8 mac_addr[6];
0455 };
0456 
0457 struct dpsw_cmd_set_egress_flood {
0458     __le16 fdb_id;
0459     u8 flood_type;
0460     u8 pad[5];
0461     __le64 if_id;
0462 };
0463 
0464 #define DPSW_LEARNING_MODE_SHIFT    0
0465 #define DPSW_LEARNING_MODE_SIZE     4
0466 
0467 struct dpsw_cmd_if_set_learning_mode {
0468     __le16 if_id;
0469     /* only the first 4 bits from LSB */
0470     u8 mode;
0471 };
0472 
0473 struct dpsw_cmd_acl_add {
0474     __le16 pad;
0475     __le16 max_entries;
0476 };
0477 
0478 struct dpsw_rsp_acl_add {
0479     __le16 acl_id;
0480 };
0481 
0482 struct dpsw_cmd_acl_remove {
0483     __le16 acl_id;
0484 };
0485 
0486 struct dpsw_cmd_acl_if {
0487     __le16 acl_id;
0488     __le16 num_ifs;
0489     __le32 pad;
0490     __le64 if_id;
0491 };
0492 
0493 struct dpsw_prep_acl_entry {
0494     u8 match_l2_dest_mac[6];
0495     __le16 match_l2_tpid;
0496 
0497     u8 match_l2_source_mac[6];
0498     __le16 match_l2_vlan_id;
0499 
0500     __le32 match_l3_dest_ip;
0501     __le32 match_l3_source_ip;
0502 
0503     __le16 match_l4_dest_port;
0504     __le16 match_l4_source_port;
0505     __le16 match_l2_ether_type;
0506     u8 match_l2_pcp_dei;
0507     u8 match_l3_dscp;
0508 
0509     u8 mask_l2_dest_mac[6];
0510     __le16 mask_l2_tpid;
0511 
0512     u8 mask_l2_source_mac[6];
0513     __le16 mask_l2_vlan_id;
0514 
0515     __le32 mask_l3_dest_ip;
0516     __le32 mask_l3_source_ip;
0517 
0518     __le16 mask_l4_dest_port;
0519     __le16 mask_l4_source_port;
0520     __le16 mask_l2_ether_type;
0521     u8 mask_l2_pcp_dei;
0522     u8 mask_l3_dscp;
0523 
0524     u8 match_l3_protocol;
0525     u8 mask_l3_protocol;
0526 };
0527 
0528 #define DPSW_RESULT_ACTION_SHIFT    0
0529 #define DPSW_RESULT_ACTION_SIZE     4
0530 
0531 struct dpsw_cmd_acl_entry {
0532     __le16 acl_id;
0533     __le16 result_if_id;
0534     __le32 precedence;
0535     /* from LSB only the first 4 bits */
0536     u8 result_action;
0537     u8 pad[7];
0538     __le64 pad2[4];
0539     __le64 key_iova;
0540 };
0541 
0542 struct dpsw_cmd_set_reflection_if {
0543     __le16 if_id;
0544 };
0545 
0546 #define DPSW_FILTER_SHIFT   0
0547 #define DPSW_FILTER_SIZE    2
0548 
0549 struct dpsw_cmd_if_reflection {
0550     __le16 if_id;
0551     __le16 vlan_id;
0552     /* only 2 bits from the LSB */
0553     u8 filter;
0554 };
0555 #pragma pack(pop)
0556 #endif /* __FSL_DPSW_CMD_H */