freescale/dpaa2/dpaa2-switch.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * DPAA2 Ethernet Switch declarations
0004  *
0005  * Copyright 2014-2016 Freescale Semiconductor Inc.
0006  * Copyright 2017-2021 NXP
0007  *
0008  */
0009
0010 #ifndef __ETHSW_H
0011 #define __ETHSW_H
0012
0013 #include <linux/netdevice.h>
0014 #include <linux/etherdevice.h>
0015 #include <linux/rtnetlink.h>
0016 #include <linux/if_vlan.h>
0017 #include <uapi/linux/if_bridge.h>
0018 #include <net/switchdev.h>
0019 #include <linux/if_bridge.h>
0020 #include <linux/fsl/mc.h>
0021 #include <net/pkt_cls.h>
0022 #include <soc/fsl/dpaa2-io.h>
0023
0024 #include "dpaa2-mac.h"
0025 #include "dpsw.h"
0026
0027 /* Number of IRQs supported */
0028 #define DPSW_IRQ_NUM    2
0029
0030 /* Port is member of VLAN */
0031 #define ETHSW_VLAN_MEMBER   1
0032 /* VLAN to be treated as untagged on egress */
0033 #define ETHSW_VLAN_UNTAGGED 2
0034 /* Untagged frames will be assigned to this VLAN */
0035 #define ETHSW_VLAN_PVID     4
0036 /* VLAN configured on the switch */
0037 #define ETHSW_VLAN_GLOBAL   8
0038
0039 /* Maximum Frame Length supported by HW (currently 10k) */
0040 #define DPAA2_MFL       (10 * 1024)
0041 #define ETHSW_MAX_FRAME_LENGTH  (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
0042 #define ETHSW_L2_MAX_FRM(mtu)   ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
0043
0044 #define ETHSW_FEATURE_MAC_ADDR  BIT(0)
0045
0046 /* Number of receive queues (one RX and one TX_CONF) */
0047 #define DPAA2_SWITCH_RX_NUM_FQS 2
0048
0049 /* Hardware requires alignment for ingress/egress buffer addresses */
0050 #define DPAA2_SWITCH_RX_BUF_RAW_SIZE    PAGE_SIZE
0051 #define DPAA2_SWITCH_RX_BUF_TAILROOM \
0052     SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
0053 #define DPAA2_SWITCH_RX_BUF_SIZE \
0054     (DPAA2_SWITCH_RX_BUF_RAW_SIZE - DPAA2_SWITCH_RX_BUF_TAILROOM)
0055
0056 #define DPAA2_SWITCH_STORE_SIZE 16
0057
0058 /* Buffer management */
0059 #define BUFS_PER_CMD            7
0060 #define DPAA2_ETHSW_NUM_BUFS        (1024 * BUFS_PER_CMD)
0061 #define DPAA2_ETHSW_REFILL_THRESH   (DPAA2_ETHSW_NUM_BUFS * 5 / 6)
0062
0063 /* Number of times to retry DPIO portal operations while waiting
0064  * for portal to finish executing current command and become
0065  * available. We want to avoid being stuck in a while loop in case
0066  * hardware becomes unresponsive, but not give up too easily if
0067  * the portal really is busy for valid reasons
0068  */
0069 #define DPAA2_SWITCH_SWP_BUSY_RETRIES       1000
0070
0071 /* Hardware annotation buffer size */
0072 #define DPAA2_SWITCH_HWA_SIZE           64
0073 /* Software annotation buffer size */
0074 #define DPAA2_SWITCH_SWA_SIZE           64
0075
0076 #define DPAA2_SWITCH_TX_BUF_ALIGN       64
0077
0078 #define DPAA2_SWITCH_TX_DATA_OFFSET \
0079     (DPAA2_SWITCH_HWA_SIZE + DPAA2_SWITCH_SWA_SIZE)
0080
0081 #define DPAA2_SWITCH_NEEDED_HEADROOM \
0082     (DPAA2_SWITCH_TX_DATA_OFFSET + DPAA2_SWITCH_TX_BUF_ALIGN)
0083
0084 #define DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES    16
0085 #define DPAA2_ETHSW_PORT_DEFAULT_TRAPS      1
0086
0087 #define DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE   256
0088
0089 extern const struct ethtool_ops dpaa2_switch_port_ethtool_ops;
0090
0091 struct ethsw_core;
0092
0093 struct dpaa2_switch_fq {
0094     struct ethsw_core *ethsw;
0095     enum dpsw_queue_type type;
0096     struct dpaa2_io_store *store;
0097     struct dpaa2_io_notification_ctx nctx;
0098     struct napi_struct napi;
0099     u32 fqid;
0100 };
0101
0102 struct dpaa2_switch_fdb {
0103     struct net_device   *bridge_dev;
0104     u16         fdb_id;
0105     bool            in_use;
0106 };
0107
0108 struct dpaa2_switch_acl_entry {
0109     struct list_head    list;
0110     u16         prio;
0111     unsigned long       cookie;
0112
0113     struct dpsw_acl_entry_cfg cfg;
0114     struct dpsw_acl_key key;
0115 };
0116
0117 struct dpaa2_switch_mirror_entry {
0118     struct list_head    list;
0119     struct dpsw_reflection_cfg cfg;
0120     unsigned long       cookie;
0121     u16 if_id;
0122 };
0123
0124 struct dpaa2_switch_filter_block {
0125     struct ethsw_core   *ethsw;
0126     u64         ports;
0127     bool            in_use;
0128
0129     struct list_head    acl_entries;
0130     u16         acl_id;
0131     u8          num_acl_rules;
0132
0133     struct list_head    mirror_entries;
0134 };
0135
0136 static inline bool
0137 dpaa2_switch_acl_tbl_is_full(struct dpaa2_switch_filter_block *filter_block)
0138 {
0139     if ((filter_block->num_acl_rules + DPAA2_ETHSW_PORT_DEFAULT_TRAPS) >=
0140         DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES)
0141         return true;
0142     return false;
0143 }
0144
0145 /* Per port private data */
0146 struct ethsw_port_priv {
0147     struct net_device   *netdev;
0148     u16         idx;
0149     struct ethsw_core   *ethsw_data;
0150     u8          link_state;
0151     u8          stp_state;
0152
0153     u8          vlans[VLAN_VID_MASK + 1];
0154     u16         pvid;
0155     u16         tx_qdid;
0156
0157     struct dpaa2_switch_fdb *fdb;
0158     bool            bcast_flood;
0159     bool            ucast_flood;
0160     bool            learn_ena;
0161
0162     struct dpaa2_switch_filter_block *filter_block;
0163     struct dpaa2_mac    *mac;
0164 };
0165
0166 /* Switch data */
0167 struct ethsw_core {
0168     struct device           *dev;
0169     struct fsl_mc_io        *mc_io;
0170     u16             dpsw_handle;
0171     struct dpsw_attr        sw_attr;
0172     u16             major, minor;
0173     unsigned long           features;
0174     int             dev_id;
0175     struct ethsw_port_priv      **ports;
0176     struct iommu_domain     *iommu_domain;
0177
0178     u8              vlans[VLAN_VID_MASK + 1];
0179
0180     struct workqueue_struct     *workqueue;
0181
0182     struct dpaa2_switch_fq      fq[DPAA2_SWITCH_RX_NUM_FQS];
0183     struct fsl_mc_device        *dpbp_dev;
0184     int             buf_count;
0185     u16             bpid;
0186     int             napi_users;
0187
0188     struct dpaa2_switch_fdb     *fdbs;
0189     struct dpaa2_switch_filter_block *filter_blocks;
0190     u16             mirror_port;
0191 };
0192
0193 static inline int dpaa2_switch_get_index(struct ethsw_core *ethsw,
0194                      struct net_device *netdev)
0195 {
0196     int i;
0197
0198     for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
0199         if (ethsw->ports[i]->netdev == netdev)
0200             return ethsw->ports[i]->idx;
0201
0202     return -EINVAL;
0203 }
0204
0205 static inline bool dpaa2_switch_supports_cpu_traffic(struct ethsw_core *ethsw)
0206 {
0207     if (ethsw->sw_attr.options & DPSW_OPT_CTRL_IF_DIS) {
0208         dev_err(ethsw->dev, "Control Interface is disabled, cannot probe\n");
0209         return false;
0210     }
0211
0212     if (ethsw->sw_attr.flooding_cfg != DPSW_FLOODING_PER_FDB) {
0213         dev_err(ethsw->dev, "Flooding domain is not per FDB, cannot probe\n");
0214         return false;
0215     }
0216
0217     if (ethsw->sw_attr.broadcast_cfg != DPSW_BROADCAST_PER_FDB) {
0218         dev_err(ethsw->dev, "Broadcast domain is not per FDB, cannot probe\n");
0219         return false;
0220     }
0221
0222     if (ethsw->sw_attr.max_fdbs < ethsw->sw_attr.num_ifs) {
0223         dev_err(ethsw->dev, "The number of FDBs is lower than the number of ports, cannot probe\n");
0224         return false;
0225     }
0226
0227     return true;
0228 }
0229
0230 static inline bool
0231 dpaa2_switch_port_is_type_phy(struct ethsw_port_priv *port_priv)
0232 {
0233     if (port_priv->mac &&
0234         (port_priv->mac->attr.link_type == DPMAC_LINK_TYPE_PHY ||
0235          port_priv->mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE))
0236         return true;
0237
0238     return false;
0239 }
0240
0241 static inline bool dpaa2_switch_port_has_mac(struct ethsw_port_priv *port_priv)
0242 {
0243     return port_priv->mac ? true : false;
0244 }
0245
0246 bool dpaa2_switch_port_dev_check(const struct net_device *netdev);
0247
0248 int dpaa2_switch_port_vlans_add(struct net_device *netdev,
0249                 const struct switchdev_obj_port_vlan *vlan);
0250
0251 int dpaa2_switch_port_vlans_del(struct net_device *netdev,
0252                 const struct switchdev_obj_port_vlan *vlan);
0253
0254 typedef int dpaa2_switch_fdb_cb_t(struct ethsw_port_priv *port_priv,
0255                   struct fdb_dump_entry *fdb_entry,
0256                   void *data);
0257
0258 /* TC offload */
0259
0260 int dpaa2_switch_cls_flower_replace(struct dpaa2_switch_filter_block *block,
0261                     struct flow_cls_offload *cls);
0262
0263 int dpaa2_switch_cls_flower_destroy(struct dpaa2_switch_filter_block *block,
0264                     struct flow_cls_offload *cls);
0265
0266 int dpaa2_switch_cls_matchall_replace(struct dpaa2_switch_filter_block *block,
0267                       struct tc_cls_matchall_offload *cls);
0268
0269 int dpaa2_switch_cls_matchall_destroy(struct dpaa2_switch_filter_block *block,
0270                       struct tc_cls_matchall_offload *cls);
0271
0272 int dpaa2_switch_acl_entry_add(struct dpaa2_switch_filter_block *block,
0273                    struct dpaa2_switch_acl_entry *entry);
0274
0275 int dpaa2_switch_block_offload_mirror(struct dpaa2_switch_filter_block *block,
0276                       struct ethsw_port_priv *port_priv);
0277
0278 int dpaa2_switch_block_unoffload_mirror(struct dpaa2_switch_filter_block *block,
0279                     struct ethsw_port_priv *port_priv);
0280 #endif  /* __ETHSW_H */