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0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /* Copyright 2014-2016 Freescale Semiconductor Inc.
0003  * Copyright 2016-2020 NXP
0004  */
0005 
0006 #ifndef __DPAA2_ETH_H
0007 #define __DPAA2_ETH_H
0008 
0009 #include <linux/dcbnl.h>
0010 #include <linux/netdevice.h>
0011 #include <linux/if_vlan.h>
0012 #include <linux/fsl/mc.h>
0013 #include <linux/net_tstamp.h>
0014 #include <net/devlink.h>
0015 
0016 #include <soc/fsl/dpaa2-io.h>
0017 #include <soc/fsl/dpaa2-fd.h>
0018 #include "dpni.h"
0019 #include "dpni-cmd.h"
0020 
0021 #include "dpaa2-eth-trace.h"
0022 #include "dpaa2-eth-debugfs.h"
0023 #include "dpaa2-mac.h"
0024 
0025 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
0026 
0027 #define DPAA2_ETH_STORE_SIZE        16
0028 
0029 /* Maximum number of scatter-gather entries in an ingress frame,
0030  * considering the maximum receive frame size is 64K
0031  */
0032 #define DPAA2_ETH_MAX_SG_ENTRIES    ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
0033 
0034 /* Maximum acceptable MTU value. It is in direct relation with the hardware
0035  * enforced Max Frame Length (currently 10k).
0036  */
0037 #define DPAA2_ETH_MFL           (10 * 1024)
0038 #define DPAA2_ETH_MAX_MTU       (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
0039 /* Convert L3 MTU to L2 MFL */
0040 #define DPAA2_ETH_L2_MAX_FRM(mtu)   ((mtu) + VLAN_ETH_HLEN)
0041 
0042 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large
0043  * enough number of jumbo frames in the Rx queues (length of the current
0044  * frame is not taken into account when making the taildrop decision)
0045  */
0046 #define DPAA2_ETH_FQ_TAILDROP_THRESH    (1024 * 1024)
0047 
0048 /* Maximum burst size value for Tx shaping */
0049 #define DPAA2_ETH_MAX_BURST_SIZE    0xF7FF
0050 
0051 /* Maximum number of Tx confirmation frames to be processed
0052  * in a single NAPI call
0053  */
0054 #define DPAA2_ETH_TXCONF_PER_NAPI   256
0055 
0056 /* Buffer qouta per channel. We want to keep in check number of ingress frames
0057  * in flight: for small sized frames, congestion group taildrop may kick in
0058  * first; for large sizes, Rx FQ taildrop threshold will ensure only a
0059  * reasonable number of frames will be pending at any given time.
0060  * Ingress frame drop due to buffer pool depletion should be a corner case only
0061  */
0062 #define DPAA2_ETH_NUM_BUFS      1280
0063 #define DPAA2_ETH_REFILL_THRESH \
0064     (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
0065 
0066 /* Congestion group taildrop threshold: number of frames allowed to accumulate
0067  * at any moment in a group of Rx queues belonging to the same traffic class.
0068  * Choose value such that we don't risk depleting the buffer pool before the
0069  * taildrop kicks in
0070  */
0071 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv)              \
0072     (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
0073 
0074 /* Congestion group notification threshold: when this many frames accumulate
0075  * on the Rx queues belonging to the same TC, the MAC is instructed to send
0076  * PFC frames for that TC.
0077  * When number of pending frames drops below exit threshold transmission of
0078  * PFC frames is stopped.
0079  */
0080 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
0081     (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
0082 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \
0083     (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
0084 
0085 /* Maximum number of buffers that can be acquired/released through a single
0086  * QBMan command
0087  */
0088 #define DPAA2_ETH_BUFS_PER_CMD      7
0089 
0090 /* Hardware requires alignment for ingress/egress buffer addresses */
0091 #define DPAA2_ETH_TX_BUF_ALIGN      64
0092 
0093 #define DPAA2_ETH_RX_BUF_RAW_SIZE   PAGE_SIZE
0094 #define DPAA2_ETH_RX_BUF_TAILROOM \
0095     SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
0096 #define DPAA2_ETH_RX_BUF_SIZE \
0097     (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
0098 
0099 /* Hardware annotation area in RX/TX buffers */
0100 #define DPAA2_ETH_RX_HWA_SIZE       64
0101 #define DPAA2_ETH_TX_HWA_SIZE       128
0102 
0103 /* PTP nominal frequency 1GHz */
0104 #define DPAA2_PTP_CLK_PERIOD_NS     1
0105 
0106 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
0107  * to 256B. For newer revisions, the requirement is only for 64B alignment
0108  */
0109 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
0110 #define DPAA2_ETH_RX_BUF_ALIGN      64
0111 
0112 /* We are accommodating a skb backpointer and some S/G info
0113  * in the frame's software annotation. The hardware
0114  * options are either 0 or 64, so we choose the latter.
0115  */
0116 #define DPAA2_ETH_SWA_SIZE      64
0117 
0118 /* We store different information in the software annotation area of a Tx frame
0119  * based on what type of frame it is
0120  */
0121 enum dpaa2_eth_swa_type {
0122     DPAA2_ETH_SWA_SINGLE,
0123     DPAA2_ETH_SWA_SG,
0124     DPAA2_ETH_SWA_XDP,
0125     DPAA2_ETH_SWA_SW_TSO,
0126 };
0127 
0128 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
0129 struct dpaa2_eth_swa {
0130     enum dpaa2_eth_swa_type type;
0131     union {
0132         struct {
0133             struct sk_buff *skb;
0134             int sgt_size;
0135         } single;
0136         struct {
0137             struct sk_buff *skb;
0138             struct scatterlist *scl;
0139             int num_sg;
0140             int sgt_size;
0141         } sg;
0142         struct {
0143             int dma_size;
0144             struct xdp_frame *xdpf;
0145         } xdp;
0146         struct {
0147             struct sk_buff *skb;
0148             int num_sg;
0149             int sgt_size;
0150             int is_last_fd;
0151         } tso;
0152     };
0153 };
0154 
0155 /* Annotation valid bits in FD FRC */
0156 #define DPAA2_FD_FRC_FASV       0x8000
0157 #define DPAA2_FD_FRC_FAEADV     0x4000
0158 #define DPAA2_FD_FRC_FAPRV      0x2000
0159 #define DPAA2_FD_FRC_FAIADV     0x1000
0160 #define DPAA2_FD_FRC_FASWOV     0x0800
0161 #define DPAA2_FD_FRC_FAICFDV        0x0400
0162 
0163 /* Error bits in FD CTRL */
0164 #define DPAA2_FD_RX_ERR_MASK        (FD_CTRL_SBE | FD_CTRL_FAERR)
0165 #define DPAA2_FD_TX_ERR_MASK        (FD_CTRL_UFD    | \
0166                      FD_CTRL_SBE    | \
0167                      FD_CTRL_FSE    | \
0168                      FD_CTRL_FAERR)
0169 
0170 /* Annotation bits in FD CTRL */
0171 #define DPAA2_FD_CTRL_ASAL      0x00020000  /* ASAL = 128B */
0172 
0173 /* Frame annotation status */
0174 struct dpaa2_fas {
0175     u8 reserved;
0176     u8 ppid;
0177     __le16 ifpid;
0178     __le32 status;
0179 };
0180 
0181 /* Frame annotation status word is located in the first 8 bytes
0182  * of the buffer's hardware annoatation area
0183  */
0184 #define DPAA2_FAS_OFFSET        0
0185 #define DPAA2_FAS_SIZE          (sizeof(struct dpaa2_fas))
0186 
0187 /* Timestamp is located in the next 8 bytes of the buffer's
0188  * hardware annotation area
0189  */
0190 #define DPAA2_TS_OFFSET         0x8
0191 
0192 /* Frame annotation parse results */
0193 struct dpaa2_fapr {
0194     /* 64-bit word 1 */
0195     __le32 faf_lo;
0196     __le16 faf_ext;
0197     __le16 nxt_hdr;
0198     /* 64-bit word 2 */
0199     __le64 faf_hi;
0200     /* 64-bit word 3 */
0201     u8 last_ethertype_offset;
0202     u8 vlan_tci_offset_n;
0203     u8 vlan_tci_offset_1;
0204     u8 llc_snap_offset;
0205     u8 eth_offset;
0206     u8 ip1_pid_offset;
0207     u8 shim_offset_2;
0208     u8 shim_offset_1;
0209     /* 64-bit word 4 */
0210     u8 l5_offset;
0211     u8 l4_offset;
0212     u8 gre_offset;
0213     u8 l3_offset_n;
0214     u8 l3_offset_1;
0215     u8 mpls_offset_n;
0216     u8 mpls_offset_1;
0217     u8 pppoe_offset;
0218     /* 64-bit word 5 */
0219     __le16 running_sum;
0220     __le16 gross_running_sum;
0221     u8 ipv6_frag_offset;
0222     u8 nxt_hdr_offset;
0223     u8 routing_hdr_offset_2;
0224     u8 routing_hdr_offset_1;
0225     /* 64-bit word 6 */
0226     u8 reserved[5]; /* Soft-parsing context */
0227     u8 ip_proto_offset_n;
0228     u8 nxt_hdr_frag_offset;
0229     u8 parse_error_code;
0230 };
0231 
0232 #define DPAA2_FAPR_OFFSET       0x10
0233 #define DPAA2_FAPR_SIZE         sizeof((struct dpaa2_fapr))
0234 
0235 /* Frame annotation egress action descriptor */
0236 #define DPAA2_FAEAD_OFFSET      0x58
0237 
0238 struct dpaa2_faead {
0239     __le32 conf_fqid;
0240     __le32 ctrl;
0241 };
0242 
0243 #define DPAA2_FAEAD_A2V         0x20000000
0244 #define DPAA2_FAEAD_A4V         0x08000000
0245 #define DPAA2_FAEAD_UPDV        0x00001000
0246 #define DPAA2_FAEAD_EBDDV       0x00002000
0247 #define DPAA2_FAEAD_UPD         0x00000010
0248 
0249 struct ptp_tstamp {
0250     u16 sec_msb;
0251     u32 sec_lsb;
0252     u32 nsec;
0253 };
0254 
0255 static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
0256 {
0257     u64 sec, nsec;
0258 
0259     sec = ns;
0260     nsec = do_div(sec, 1000000000);
0261 
0262     tstamp->sec_lsb = sec & 0xFFFFFFFF;
0263     tstamp->sec_msb = (sec >> 32) & 0xFFFF;
0264     tstamp->nsec = nsec;
0265 }
0266 
0267 /* Accessors for the hardware annotation fields that we use */
0268 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
0269 {
0270     return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
0271 }
0272 
0273 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
0274 {
0275     return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
0276 }
0277 
0278 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
0279 {
0280     return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
0281 }
0282 
0283 static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
0284 {
0285     return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
0286 }
0287 
0288 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
0289 {
0290     return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
0291 }
0292 
0293 /* Error and status bits in the frame annotation status word */
0294 /* Debug frame, otherwise supposed to be discarded */
0295 #define DPAA2_FAS_DISC          0x80000000
0296 /* MACSEC frame */
0297 #define DPAA2_FAS_MS            0x40000000
0298 #define DPAA2_FAS_PTP           0x08000000
0299 /* Ethernet multicast frame */
0300 #define DPAA2_FAS_MC            0x04000000
0301 /* Ethernet broadcast frame */
0302 #define DPAA2_FAS_BC            0x02000000
0303 #define DPAA2_FAS_KSE           0x00040000
0304 #define DPAA2_FAS_EOFHE         0x00020000
0305 #define DPAA2_FAS_MNLE          0x00010000
0306 #define DPAA2_FAS_TIDE          0x00008000
0307 #define DPAA2_FAS_PIEE          0x00004000
0308 /* Frame length error */
0309 #define DPAA2_FAS_FLE           0x00002000
0310 /* Frame physical error */
0311 #define DPAA2_FAS_FPE           0x00001000
0312 #define DPAA2_FAS_PTE           0x00000080
0313 #define DPAA2_FAS_ISP           0x00000040
0314 #define DPAA2_FAS_PHE           0x00000020
0315 #define DPAA2_FAS_BLE           0x00000010
0316 /* L3 csum validation performed */
0317 #define DPAA2_FAS_L3CV          0x00000008
0318 /* L3 csum error */
0319 #define DPAA2_FAS_L3CE          0x00000004
0320 /* L4 csum validation performed */
0321 #define DPAA2_FAS_L4CV          0x00000002
0322 /* L4 csum error */
0323 #define DPAA2_FAS_L4CE          0x00000001
0324 /* Possible errors on the ingress path */
0325 #define DPAA2_FAS_RX_ERR_MASK       (DPAA2_FAS_KSE      | \
0326                      DPAA2_FAS_EOFHE    | \
0327                      DPAA2_FAS_MNLE     | \
0328                      DPAA2_FAS_TIDE     | \
0329                      DPAA2_FAS_PIEE     | \
0330                      DPAA2_FAS_FLE      | \
0331                      DPAA2_FAS_FPE      | \
0332                      DPAA2_FAS_PTE      | \
0333                      DPAA2_FAS_ISP      | \
0334                      DPAA2_FAS_PHE      | \
0335                      DPAA2_FAS_BLE      | \
0336                      DPAA2_FAS_L3CE     | \
0337                      DPAA2_FAS_L4CE)
0338 
0339 /* Time in milliseconds between link state updates */
0340 #define DPAA2_ETH_LINK_STATE_REFRESH    1000
0341 
0342 /* Number of times to retry a frame enqueue before giving up.
0343  * Value determined empirically, in order to minimize the number
0344  * of frames dropped on Tx
0345  */
0346 #define DPAA2_ETH_ENQUEUE_RETRIES   10
0347 
0348 /* Number of times to retry DPIO portal operations while waiting
0349  * for portal to finish executing current command and become
0350  * available. We want to avoid being stuck in a while loop in case
0351  * hardware becomes unresponsive, but not give up too easily if
0352  * the portal really is busy for valid reasons
0353  */
0354 #define DPAA2_ETH_SWP_BUSY_RETRIES  1000
0355 
0356 /* Driver statistics, other than those in struct rtnl_link_stats64.
0357  * These are usually collected per-CPU and aggregated by ethtool.
0358  */
0359 struct dpaa2_eth_drv_stats {
0360     __u64   tx_conf_frames;
0361     __u64   tx_conf_bytes;
0362     __u64   tx_sg_frames;
0363     __u64   tx_sg_bytes;
0364     __u64   tx_tso_frames;
0365     __u64   tx_tso_bytes;
0366     __u64   rx_sg_frames;
0367     __u64   rx_sg_bytes;
0368     /* Linear skbs sent as a S/G FD due to insufficient headroom */
0369     __u64   tx_converted_sg_frames;
0370     __u64   tx_converted_sg_bytes;
0371     /* Enqueues retried due to portal busy */
0372     __u64   tx_portal_busy;
0373 };
0374 
0375 /* Per-FQ statistics */
0376 struct dpaa2_eth_fq_stats {
0377     /* Number of frames received on this queue */
0378     __u64 frames;
0379 };
0380 
0381 /* Per-channel statistics */
0382 struct dpaa2_eth_ch_stats {
0383     /* Volatile dequeues retried due to portal busy */
0384     __u64 dequeue_portal_busy;
0385     /* Pull errors */
0386     __u64 pull_err;
0387     /* Number of CDANs; useful to estimate avg NAPI len */
0388     __u64 cdan;
0389     /* XDP counters */
0390     __u64 xdp_drop;
0391     __u64 xdp_tx;
0392     __u64 xdp_tx_err;
0393     __u64 xdp_redirect;
0394     /* Must be last, does not show up in ethtool stats */
0395     __u64 frames;
0396     __u64 frames_per_cdan;
0397     __u64 bytes_per_cdan;
0398 };
0399 
0400 #define DPAA2_ETH_CH_STATS  7
0401 
0402 /* Maximum number of queues associated with a DPNI */
0403 #define DPAA2_ETH_MAX_TCS       8
0404 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC  16
0405 #define DPAA2_ETH_MAX_RX_QUEUES     \
0406     (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
0407 #define DPAA2_ETH_MAX_TX_QUEUES     16
0408 #define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
0409 #define DPAA2_ETH_MAX_QUEUES        (DPAA2_ETH_MAX_RX_QUEUES + \
0410                     DPAA2_ETH_MAX_TX_QUEUES + \
0411                     DPAA2_ETH_MAX_RX_ERR_QUEUES)
0412 #define DPAA2_ETH_MAX_NETDEV_QUEUES \
0413     (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
0414 
0415 #define DPAA2_ETH_MAX_DPCONS        16
0416 
0417 enum dpaa2_eth_fq_type {
0418     DPAA2_RX_FQ = 0,
0419     DPAA2_TX_CONF_FQ,
0420     DPAA2_RX_ERR_FQ
0421 };
0422 
0423 struct dpaa2_eth_priv;
0424 
0425 struct dpaa2_eth_xdp_fds {
0426     struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
0427     ssize_t num;
0428 };
0429 
0430 struct dpaa2_eth_fq {
0431     u32 fqid;
0432     u32 tx_qdbin;
0433     u32 tx_fqid[DPAA2_ETH_MAX_TCS];
0434     u16 flowid;
0435     u8 tc;
0436     int target_cpu;
0437     u32 dq_frames;
0438     u32 dq_bytes;
0439     struct dpaa2_eth_channel *channel;
0440     enum dpaa2_eth_fq_type type;
0441 
0442     void (*consume)(struct dpaa2_eth_priv *priv,
0443             struct dpaa2_eth_channel *ch,
0444             const struct dpaa2_fd *fd,
0445             struct dpaa2_eth_fq *fq);
0446     struct dpaa2_eth_fq_stats stats;
0447 
0448     struct dpaa2_eth_xdp_fds xdp_redirect_fds;
0449     struct dpaa2_eth_xdp_fds xdp_tx_fds;
0450 };
0451 
0452 struct dpaa2_eth_ch_xdp {
0453     struct bpf_prog *prog;
0454     unsigned int res;
0455 };
0456 
0457 struct dpaa2_eth_channel {
0458     struct dpaa2_io_notification_ctx nctx;
0459     struct fsl_mc_device *dpcon;
0460     int dpcon_id;
0461     int ch_id;
0462     struct napi_struct napi;
0463     struct dpaa2_io *dpio;
0464     struct dpaa2_io_store *store;
0465     struct dpaa2_eth_priv *priv;
0466     int buf_count;
0467     struct dpaa2_eth_ch_stats stats;
0468     struct dpaa2_eth_ch_xdp xdp;
0469     struct xdp_rxq_info xdp_rxq;
0470     struct list_head *rx_list;
0471 
0472     /* Buffers to be recycled back in the buffer pool */
0473     u64 recycled_bufs[DPAA2_ETH_BUFS_PER_CMD];
0474     int recycled_bufs_cnt;
0475 };
0476 
0477 struct dpaa2_eth_dist_fields {
0478     u64 rxnfc_field;
0479     enum net_prot cls_prot;
0480     int cls_field;
0481     int size;
0482     u64 id;
0483 };
0484 
0485 struct dpaa2_eth_cls_rule {
0486     struct ethtool_rx_flow_spec fs;
0487     u8 in_use;
0488 };
0489 
0490 #define DPAA2_ETH_SGT_CACHE_SIZE    256
0491 struct dpaa2_eth_sgt_cache {
0492     void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
0493     u16 count;
0494 };
0495 
0496 struct dpaa2_eth_trap_item {
0497     void *trap_ctx;
0498 };
0499 
0500 struct dpaa2_eth_trap_data {
0501     struct dpaa2_eth_trap_item *trap_items_arr;
0502     struct dpaa2_eth_priv *priv;
0503 };
0504 
0505 #define DPAA2_ETH_SG_ENTRIES_MAX    (PAGE_SIZE / sizeof(struct scatterlist))
0506 
0507 #define DPAA2_ETH_DEFAULT_COPYBREAK 512
0508 
0509 #define DPAA2_ETH_ENQUEUE_MAX_FDS   200
0510 struct dpaa2_eth_fds {
0511     struct dpaa2_fd array[DPAA2_ETH_ENQUEUE_MAX_FDS];
0512 };
0513 
0514 /* Driver private data */
0515 struct dpaa2_eth_priv {
0516     struct net_device *net_dev;
0517 
0518     u8 num_fqs;
0519     struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
0520     int (*enqueue)(struct dpaa2_eth_priv *priv,
0521                struct dpaa2_eth_fq *fq,
0522                struct dpaa2_fd *fd, u8 prio,
0523                u32 num_frames,
0524                int *frames_enqueued);
0525 
0526     u8 num_channels;
0527     struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
0528     struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
0529     unsigned long features;
0530     struct dpni_attr dpni_attrs;
0531     u16 dpni_ver_major;
0532     u16 dpni_ver_minor;
0533     u16 tx_data_offset;
0534     void __iomem *onestep_reg_base;
0535     u8 ptp_correction_off;
0536     void (*dpaa2_set_onestep_params_cb)(struct dpaa2_eth_priv *priv,
0537                         u32 offset, u8 udp);
0538     struct fsl_mc_device *dpbp_dev;
0539     u16 rx_buf_size;
0540     u16 bpid;
0541     struct iommu_domain *iommu_domain;
0542 
0543     enum hwtstamp_tx_types tx_tstamp_type;  /* Tx timestamping type */
0544     bool rx_tstamp;             /* Rx timestamping enabled */
0545 
0546     u16 tx_qdid;
0547     struct fsl_mc_io *mc_io;
0548     /* Cores which have an affine DPIO/DPCON.
0549      * This is the cpu set on which Rx and Tx conf frames are processed
0550      */
0551     struct cpumask dpio_cpumask;
0552 
0553     /* Standard statistics */
0554     struct rtnl_link_stats64 __percpu *percpu_stats;
0555     /* Extra stats, in addition to the ones known by the kernel */
0556     struct dpaa2_eth_drv_stats __percpu *percpu_extras;
0557 
0558     u16 mc_token;
0559     u8 rx_fqtd_enabled;
0560     u8 rx_cgtd_enabled;
0561 
0562     struct dpni_link_state link_state;
0563     bool do_link_poll;
0564     struct task_struct *poll_thread;
0565 
0566     /* enabled ethtool hashing bits */
0567     u64 rx_hash_fields;
0568     u64 rx_cls_fields;
0569     struct dpaa2_eth_cls_rule *cls_rules;
0570     u8 rx_cls_enabled;
0571     u8 vlan_cls_enabled;
0572     u8 pfc_enabled;
0573 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
0574     u8 dcbx_mode;
0575     struct ieee_pfc pfc;
0576 #endif
0577     struct bpf_prog *xdp_prog;
0578 #ifdef CONFIG_DEBUG_FS
0579     struct dpaa2_debugfs dbg;
0580 #endif
0581 
0582     struct dpaa2_mac *mac;
0583     struct workqueue_struct *dpaa2_ptp_wq;
0584     struct work_struct  tx_onestep_tstamp;
0585     struct sk_buff_head tx_skbs;
0586     /* The one-step timestamping configuration on hardware
0587      * registers could only be done when no one-step
0588      * timestamping frames are in flight. So we use a mutex
0589      * lock here to make sure the lock is released by last
0590      * one-step timestamping packet through TX confirmation
0591      * queue before transmit current packet.
0592      */
0593     struct mutex        onestep_tstamp_lock;
0594     struct devlink *devlink;
0595     struct dpaa2_eth_trap_data *trap_data;
0596     struct devlink_port devlink_port;
0597 
0598     u32 rx_copybreak;
0599 
0600     struct dpaa2_eth_fds __percpu *fd;
0601 };
0602 
0603 struct dpaa2_eth_devlink_priv {
0604     struct dpaa2_eth_priv *dpaa2_priv;
0605 };
0606 
0607 #define TX_TSTAMP       0x1
0608 #define TX_TSTAMP_ONESTEP_SYNC  0x2
0609 
0610 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
0611                 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
0612                 | RXH_L4_B_2_3)
0613 
0614 /* default Rx hash options, set during probing */
0615 #define DPAA2_RXH_DEFAULT   (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
0616                  RXH_L4_B_0_1 | RXH_L4_B_2_3)
0617 
0618 #define dpaa2_eth_hash_enabled(priv)    \
0619     ((priv)->dpni_attrs.num_queues > 1)
0620 
0621 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
0622 #define DPAA2_CLASSIFIER_DMA_SIZE 256
0623 
0624 extern const struct ethtool_ops dpaa2_ethtool_ops;
0625 extern int dpaa2_phc_index;
0626 extern struct ptp_qoriq *dpaa2_ptp;
0627 
0628 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
0629                      u16 ver_major, u16 ver_minor)
0630 {
0631     if (priv->dpni_ver_major == ver_major)
0632         return priv->dpni_ver_minor - ver_minor;
0633     return priv->dpni_ver_major - ver_major;
0634 }
0635 
0636 /* Minimum firmware version that supports a more flexible API
0637  * for configuring the Rx flow hash key
0638  */
0639 #define DPNI_RX_DIST_KEY_VER_MAJOR  7
0640 #define DPNI_RX_DIST_KEY_VER_MINOR  5
0641 
0642 #define dpaa2_eth_has_legacy_dist(priv)                 \
0643     (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
0644                 DPNI_RX_DIST_KEY_VER_MINOR) < 0)
0645 
0646 #define dpaa2_eth_fs_enabled(priv)  \
0647     (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
0648 
0649 #define dpaa2_eth_fs_mask_enabled(priv) \
0650     ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
0651 
0652 #define dpaa2_eth_fs_count(priv)        \
0653     ((priv)->dpni_attrs.fs_entries)
0654 
0655 #define dpaa2_eth_tc_count(priv)    \
0656     ((priv)->dpni_attrs.num_tcs)
0657 
0658 /* We have exactly one {Rx, Tx conf} queue per channel */
0659 #define dpaa2_eth_queue_count(priv)     \
0660     ((priv)->num_channels)
0661 
0662 enum dpaa2_eth_rx_dist {
0663     DPAA2_ETH_RX_DIST_HASH,
0664     DPAA2_ETH_RX_DIST_CLS
0665 };
0666 
0667 /* Unique IDs for the supported Rx classification header fields */
0668 #define DPAA2_ETH_DIST_ETHDST       BIT(0)
0669 #define DPAA2_ETH_DIST_ETHSRC       BIT(1)
0670 #define DPAA2_ETH_DIST_ETHTYPE      BIT(2)
0671 #define DPAA2_ETH_DIST_VLAN     BIT(3)
0672 #define DPAA2_ETH_DIST_IPSRC        BIT(4)
0673 #define DPAA2_ETH_DIST_IPDST        BIT(5)
0674 #define DPAA2_ETH_DIST_IPPROTO      BIT(6)
0675 #define DPAA2_ETH_DIST_L4SRC        BIT(7)
0676 #define DPAA2_ETH_DIST_L4DST        BIT(8)
0677 #define DPAA2_ETH_DIST_ALL      (~0ULL)
0678 
0679 #define DPNI_PTP_ONESTEP_VER_MAJOR 8
0680 #define DPNI_PTP_ONESTEP_VER_MINOR 2
0681 #define DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT BIT(0)
0682 #define DPAA2_PTP_SINGLE_STEP_ENABLE    BIT(31)
0683 #define DPAA2_PTP_SINGLE_STEP_CH    BIT(7)
0684 #define DPAA2_PTP_SINGLE_CORRECTION_OFF(v) ((v) << 8)
0685 
0686 #define DPNI_PAUSE_VER_MAJOR        7
0687 #define DPNI_PAUSE_VER_MINOR        13
0688 #define dpaa2_eth_has_pause_support(priv)           \
0689     (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR,   \
0690                 DPNI_PAUSE_VER_MINOR) >= 0)
0691 
0692 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
0693 {
0694     return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
0695            !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
0696 }
0697 
0698 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
0699 {
0700     return !!(link_options & DPNI_LINK_OPT_PAUSE);
0701 }
0702 
0703 static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
0704 {
0705     unsigned int headroom = DPAA2_ETH_SWA_SIZE;
0706 
0707     /* If we don't have an skb (e.g. XDP buffer), we only need space for
0708      * the software annotation area
0709      */
0710     if (!skb)
0711         return headroom;
0712 
0713     /* For non-linear skbs we have no headroom requirement, as we build a
0714      * SG frame with a newly allocated SGT buffer
0715      */
0716     if (skb_is_nonlinear(skb))
0717         return 0;
0718 
0719     /* If we have Tx timestamping, need 128B hardware annotation */
0720     if (skb->cb[0])
0721         headroom += DPAA2_ETH_TX_HWA_SIZE;
0722 
0723     return headroom;
0724 }
0725 
0726 /* Extra headroom space requested to hardware, in order to make sure there's
0727  * no realloc'ing in forwarding scenarios
0728  */
0729 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
0730 {
0731     return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
0732 }
0733 
0734 static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv)
0735 {
0736     if (priv->mac &&
0737         (priv->mac->attr.link_type == DPMAC_LINK_TYPE_PHY ||
0738          priv->mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE))
0739         return true;
0740 
0741     return false;
0742 }
0743 
0744 static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv)
0745 {
0746     return priv->mac ? true : false;
0747 }
0748 
0749 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
0750 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
0751 int dpaa2_eth_cls_key_size(u64 key);
0752 int dpaa2_eth_cls_fld_off(int prot, int field);
0753 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
0754 
0755 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
0756                    bool tx_pause, bool pfc);
0757 
0758 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
0759 
0760 int dpaa2_eth_dl_alloc(struct dpaa2_eth_priv *priv);
0761 void dpaa2_eth_dl_free(struct dpaa2_eth_priv *priv);
0762 
0763 void dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
0764 void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
0765 
0766 int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
0767 void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
0768 
0769 int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
0770 void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
0771 
0772 struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
0773                           struct dpaa2_fapr *fapr);
0774 #endif  /* __DPAA2_H */
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