ethernet/faraday/ftmac100.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Faraday FTMAC100 10/100 Ethernet
0004  *
0005  * (C) Copyright 2009-2011 Faraday Technology
0006  * Po-Yu Chuang <ratbert@faraday-tech.com>
0007  */
0008
0009 #ifndef __FTMAC100_H
0010 #define __FTMAC100_H
0011
0012 #define FTMAC100_OFFSET_ISR     0x00
0013 #define FTMAC100_OFFSET_IMR     0x04
0014 #define FTMAC100_OFFSET_MAC_MADR    0x08
0015 #define FTMAC100_OFFSET_MAC_LADR    0x0c
0016 #define FTMAC100_OFFSET_MAHT0       0x10
0017 #define FTMAC100_OFFSET_MAHT1       0x14
0018 #define FTMAC100_OFFSET_TXPD        0x18
0019 #define FTMAC100_OFFSET_RXPD        0x1c
0020 #define FTMAC100_OFFSET_TXR_BADR    0x20
0021 #define FTMAC100_OFFSET_RXR_BADR    0x24
0022 #define FTMAC100_OFFSET_ITC     0x28
0023 #define FTMAC100_OFFSET_APTC        0x2c
0024 #define FTMAC100_OFFSET_DBLAC       0x30
0025 #define FTMAC100_OFFSET_MACCR       0x88
0026 #define FTMAC100_OFFSET_MACSR       0x8c
0027 #define FTMAC100_OFFSET_PHYCR       0x90
0028 #define FTMAC100_OFFSET_PHYWDATA    0x94
0029 #define FTMAC100_OFFSET_FCR     0x98
0030 #define FTMAC100_OFFSET_BPR     0x9c
0031 #define FTMAC100_OFFSET_TS      0xc4
0032 #define FTMAC100_OFFSET_DMAFIFOS    0xc8
0033 #define FTMAC100_OFFSET_TM      0xcc
0034 #define FTMAC100_OFFSET_TX_MCOL_SCOL    0xd4
0035 #define FTMAC100_OFFSET_RPF_AEP     0xd8
0036 #define FTMAC100_OFFSET_XM_PG       0xdc
0037 #define FTMAC100_OFFSET_RUNT_TLCC   0xe0
0038 #define FTMAC100_OFFSET_CRCER_FTL   0xe4
0039 #define FTMAC100_OFFSET_RLC_RCC     0xe8
0040 #define FTMAC100_OFFSET_BROC        0xec
0041 #define FTMAC100_OFFSET_MULCA       0xf0
0042 #define FTMAC100_OFFSET_RP      0xf4
0043 #define FTMAC100_OFFSET_XP      0xf8
0044
0045 /*
0046  * Interrupt status register & interrupt mask register
0047  */
0048 #define FTMAC100_INT_RPKT_FINISH    (1 << 0)
0049 #define FTMAC100_INT_NORXBUF        (1 << 1)
0050 #define FTMAC100_INT_XPKT_FINISH    (1 << 2)
0051 #define FTMAC100_INT_NOTXBUF        (1 << 3)
0052 #define FTMAC100_INT_XPKT_OK        (1 << 4)
0053 #define FTMAC100_INT_XPKT_LOST      (1 << 5)
0054 #define FTMAC100_INT_RPKT_SAV       (1 << 6)
0055 #define FTMAC100_INT_RPKT_LOST      (1 << 7)
0056 #define FTMAC100_INT_AHB_ERR        (1 << 8)
0057 #define FTMAC100_INT_PHYSTS_CHG     (1 << 9)
0058
0059 /*
0060  * Interrupt timer control register
0061  */
0062 #define FTMAC100_ITC_RXINT_CNT(x)   (((x) & 0xf) << 0)
0063 #define FTMAC100_ITC_RXINT_THR(x)   (((x) & 0x7) << 4)
0064 #define FTMAC100_ITC_RXINT_TIME_SEL (1 << 7)
0065 #define FTMAC100_ITC_TXINT_CNT(x)   (((x) & 0xf) << 8)
0066 #define FTMAC100_ITC_TXINT_THR(x)   (((x) & 0x7) << 12)
0067 #define FTMAC100_ITC_TXINT_TIME_SEL (1 << 15)
0068
0069 /*
0070  * Automatic polling timer control register
0071  */
0072 #define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
0073 #define FTMAC100_APTC_RXPOLL_TIME_SEL   (1 << 4)
0074 #define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
0075 #define FTMAC100_APTC_TXPOLL_TIME_SEL   (1 << 12)
0076
0077 /*
0078  * DMA burst length and arbitration control register
0079  */
0080 #define FTMAC100_DBLAC_INCR4_EN     (1 << 0)
0081 #define FTMAC100_DBLAC_INCR8_EN     (1 << 1)
0082 #define FTMAC100_DBLAC_INCR16_EN    (1 << 2)
0083 #define FTMAC100_DBLAC_RXFIFO_LTHR(x)   (((x) & 0x7) << 3)
0084 #define FTMAC100_DBLAC_RXFIFO_HTHR(x)   (((x) & 0x7) << 6)
0085 #define FTMAC100_DBLAC_RX_THR_EN    (1 << 9)
0086
0087 /*
0088  * MAC control register
0089  */
0090 #define FTMAC100_MACCR_XDMA_EN      (1 << 0)
0091 #define FTMAC100_MACCR_RDMA_EN      (1 << 1)
0092 #define FTMAC100_MACCR_SW_RST       (1 << 2)
0093 #define FTMAC100_MACCR_LOOP_EN      (1 << 3)
0094 #define FTMAC100_MACCR_CRC_DIS      (1 << 4)
0095 #define FTMAC100_MACCR_XMT_EN       (1 << 5)
0096 #define FTMAC100_MACCR_ENRX_IN_HALFTX   (1 << 6)
0097 #define FTMAC100_MACCR_RCV_EN       (1 << 8)
0098 #define FTMAC100_MACCR_HT_MULTI_EN  (1 << 9)
0099 #define FTMAC100_MACCR_RX_RUNT      (1 << 10)
0100 #define FTMAC100_MACCR_RX_FTL       (1 << 11)
0101 #define FTMAC100_MACCR_RCV_ALL      (1 << 12)
0102 #define FTMAC100_MACCR_CRC_APD      (1 << 14)
0103 #define FTMAC100_MACCR_FULLDUP      (1 << 15)
0104 #define FTMAC100_MACCR_RX_MULTIPKT  (1 << 16)
0105 #define FTMAC100_MACCR_RX_BROADPKT  (1 << 17)
0106
0107 /*
0108  * PHY control register
0109  */
0110 #define FTMAC100_PHYCR_MIIRDATA     0xffff
0111 #define FTMAC100_PHYCR_PHYAD(x)     (((x) & 0x1f) << 16)
0112 #define FTMAC100_PHYCR_REGAD(x)     (((x) & 0x1f) << 21)
0113 #define FTMAC100_PHYCR_MIIRD        (1 << 26)
0114 #define FTMAC100_PHYCR_MIIWR        (1 << 27)
0115
0116 /*
0117  * PHY write data register
0118  */
0119 #define FTMAC100_PHYWDATA_MIIWDATA(x)   ((x) & 0xffff)
0120
0121 /*
0122  * Transmit descriptor, aligned to 16 bytes
0123  */
0124 struct ftmac100_txdes {
0125     unsigned int    txdes0;
0126     unsigned int    txdes1;
0127     unsigned int    txdes2; /* TXBUF_BADR */
0128     unsigned int    txdes3; /* not used by HW */
0129 } __attribute__ ((aligned(16)));
0130
0131 #define FTMAC100_TXDES0_TXPKT_LATECOL   (1 << 0)
0132 #define FTMAC100_TXDES0_TXPKT_EXSCOL    (1 << 1)
0133 #define FTMAC100_TXDES0_TXDMA_OWN   (1 << 31)
0134
0135 #define FTMAC100_TXDES1_TXBUF_SIZE(x)   ((x) & 0x7ff)
0136 #define FTMAC100_TXDES1_LTS     (1 << 27)
0137 #define FTMAC100_TXDES1_FTS     (1 << 28)
0138 #define FTMAC100_TXDES1_TX2FIC      (1 << 29)
0139 #define FTMAC100_TXDES1_TXIC        (1 << 30)
0140 #define FTMAC100_TXDES1_EDOTR       (1 << 31)
0141
0142 /*
0143  * Receive descriptor, aligned to 16 bytes
0144  */
0145 struct ftmac100_rxdes {
0146     unsigned int    rxdes0;
0147     unsigned int    rxdes1;
0148     unsigned int    rxdes2; /* RXBUF_BADR */
0149     unsigned int    rxdes3; /* not used by HW */
0150 } __attribute__ ((aligned(16)));
0151
0152 #define FTMAC100_RXDES0_RFL     0x7ff
0153 #define FTMAC100_RXDES0_MULTICAST   (1 << 16)
0154 #define FTMAC100_RXDES0_BROADCAST   (1 << 17)
0155 #define FTMAC100_RXDES0_RX_ERR      (1 << 18)
0156 #define FTMAC100_RXDES0_CRC_ERR     (1 << 19)
0157 #define FTMAC100_RXDES0_FTL     (1 << 20)
0158 #define FTMAC100_RXDES0_RUNT        (1 << 21)
0159 #define FTMAC100_RXDES0_RX_ODD_NB   (1 << 22)
0160 #define FTMAC100_RXDES0_LRS     (1 << 28)
0161 #define FTMAC100_RXDES0_FRS     (1 << 29)
0162 #define FTMAC100_RXDES0_RXDMA_OWN   (1 << 31)
0163
0164 #define FTMAC100_RXDES1_RXBUF_SIZE(x)   ((x) & 0x7ff)
0165 #define FTMAC100_RXDES1_EDORR       (1 << 31)
0166
0167 #endif /* __FTMAC100_H */