ethernet/faraday/ftgmac100.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Faraday FTGMAC100 Gigabit Ethernet
0004  *
0005  * (C) Copyright 2009-2011 Faraday Technology
0006  * Po-Yu Chuang <ratbert@faraday-tech.com>
0007  */
0008
0009 #ifndef __FTGMAC100_H
0010 #define __FTGMAC100_H
0011
0012 #define FTGMAC100_OFFSET_ISR        0x00
0013 #define FTGMAC100_OFFSET_IER        0x04
0014 #define FTGMAC100_OFFSET_MAC_MADR   0x08
0015 #define FTGMAC100_OFFSET_MAC_LADR   0x0c
0016 #define FTGMAC100_OFFSET_MAHT0      0x10
0017 #define FTGMAC100_OFFSET_MAHT1      0x14
0018 #define FTGMAC100_OFFSET_NPTXPD     0x18
0019 #define FTGMAC100_OFFSET_RXPD       0x1c
0020 #define FTGMAC100_OFFSET_NPTXR_BADR 0x20
0021 #define FTGMAC100_OFFSET_RXR_BADR   0x24
0022 #define FTGMAC100_OFFSET_HPTXPD     0x28
0023 #define FTGMAC100_OFFSET_HPTXR_BADR 0x2c
0024 #define FTGMAC100_OFFSET_ITC        0x30
0025 #define FTGMAC100_OFFSET_APTC       0x34
0026 #define FTGMAC100_OFFSET_DBLAC      0x38
0027 #define FTGMAC100_OFFSET_DMAFIFOS   0x3c
0028 #define FTGMAC100_OFFSET_REVR       0x40
0029 #define FTGMAC100_OFFSET_FEAR       0x44
0030 #define FTGMAC100_OFFSET_TPAFCR     0x48
0031 #define FTGMAC100_OFFSET_RBSR       0x4c
0032 #define FTGMAC100_OFFSET_MACCR      0x50
0033 #define FTGMAC100_OFFSET_MACSR      0x54
0034 #define FTGMAC100_OFFSET_TM     0x58
0035 #define FTGMAC100_OFFSET_PHYCR      0x60
0036 #define FTGMAC100_OFFSET_PHYDATA    0x64
0037 #define FTGMAC100_OFFSET_FCR        0x68
0038 #define FTGMAC100_OFFSET_BPR        0x6c
0039 #define FTGMAC100_OFFSET_WOLCR      0x70
0040 #define FTGMAC100_OFFSET_WOLSR      0x74
0041 #define FTGMAC100_OFFSET_WFCRC      0x78
0042 #define FTGMAC100_OFFSET_WFBM1      0x80
0043 #define FTGMAC100_OFFSET_WFBM2      0x84
0044 #define FTGMAC100_OFFSET_WFBM3      0x88
0045 #define FTGMAC100_OFFSET_WFBM4      0x8c
0046 #define FTGMAC100_OFFSET_NPTXR_PTR  0x90
0047 #define FTGMAC100_OFFSET_HPTXR_PTR  0x94
0048 #define FTGMAC100_OFFSET_RXR_PTR    0x98
0049 #define FTGMAC100_OFFSET_TX     0xa0
0050 #define FTGMAC100_OFFSET_TX_MCOL_SCOL   0xa4
0051 #define FTGMAC100_OFFSET_TX_ECOL_FAIL   0xa8
0052 #define FTGMAC100_OFFSET_TX_LCOL_UND    0xac
0053 #define FTGMAC100_OFFSET_RX     0xb0
0054 #define FTGMAC100_OFFSET_RX_BC      0xb4
0055 #define FTGMAC100_OFFSET_RX_MC      0xb8
0056 #define FTGMAC100_OFFSET_RX_PF_AEP  0xbc
0057 #define FTGMAC100_OFFSET_RX_RUNT    0xc0
0058 #define FTGMAC100_OFFSET_RX_CRCER_FTL   0xc4
0059 #define FTGMAC100_OFFSET_RX_COL_LOST    0xc8
0060
0061 /*
0062  * Interrupt status register & interrupt enable register
0063  */
0064 #define FTGMAC100_INT_RPKT_BUF      (1 << 0)
0065 #define FTGMAC100_INT_RPKT_FIFO     (1 << 1)
0066 #define FTGMAC100_INT_NO_RXBUF      (1 << 2)
0067 #define FTGMAC100_INT_RPKT_LOST     (1 << 3)
0068 #define FTGMAC100_INT_XPKT_ETH      (1 << 4)
0069 #define FTGMAC100_INT_XPKT_FIFO     (1 << 5)
0070 #define FTGMAC100_INT_NO_NPTXBUF    (1 << 6)
0071 #define FTGMAC100_INT_XPKT_LOST     (1 << 7)
0072 #define FTGMAC100_INT_AHB_ERR       (1 << 8)
0073 #define FTGMAC100_INT_PHYSTS_CHG    (1 << 9)
0074 #define FTGMAC100_INT_NO_HPTXBUF    (1 << 10)
0075
0076 /* Interrupts we care about in NAPI mode */
0077 #define FTGMAC100_INT_BAD  (FTGMAC100_INT_RPKT_LOST | \
0078                 FTGMAC100_INT_XPKT_LOST | \
0079                 FTGMAC100_INT_AHB_ERR   | \
0080                 FTGMAC100_INT_NO_RXBUF)
0081
0082 /* Normal RX/TX interrupts, enabled when NAPI off */
0083 #define FTGMAC100_INT_RXTX (FTGMAC100_INT_XPKT_ETH  | \
0084                 FTGMAC100_INT_RPKT_BUF)
0085
0086 /* All the interrupts we care about */
0087 #define FTGMAC100_INT_ALL (FTGMAC100_INT_RPKT_BUF  |  \
0088                FTGMAC100_INT_BAD)
0089
0090 /*
0091  * Interrupt timer control register
0092  */
0093 #define FTGMAC100_ITC_RXINT_CNT(x)  (((x) & 0xf) << 0)
0094 #define FTGMAC100_ITC_RXINT_THR(x)  (((x) & 0x7) << 4)
0095 #define FTGMAC100_ITC_RXINT_TIME_SEL    (1 << 7)
0096 #define FTGMAC100_ITC_TXINT_CNT(x)  (((x) & 0xf) << 8)
0097 #define FTGMAC100_ITC_TXINT_THR(x)  (((x) & 0x7) << 12)
0098 #define FTGMAC100_ITC_TXINT_TIME_SEL    (1 << 15)
0099
0100 /*
0101  * Automatic polling timer control register
0102  */
0103 #define FTGMAC100_APTC_RXPOLL_CNT(x)    (((x) & 0xf) << 0)
0104 #define FTGMAC100_APTC_RXPOLL_TIME_SEL  (1 << 4)
0105 #define FTGMAC100_APTC_TXPOLL_CNT(x)    (((x) & 0xf) << 8)
0106 #define FTGMAC100_APTC_TXPOLL_TIME_SEL  (1 << 12)
0107
0108 /*
0109  * DMA burst length and arbitration control register
0110  */
0111 #define FTGMAC100_DBLAC_RXFIFO_LTHR(x)  (((x) & 0x7) << 0)
0112 #define FTGMAC100_DBLAC_RXFIFO_HTHR(x)  (((x) & 0x7) << 3)
0113 #define FTGMAC100_DBLAC_RX_THR_EN   (1 << 6)
0114 #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
0115 #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
0116 #define FTGMAC100_DBLAC_RXDES_SIZE(x)   (((x) & 0xf) << 12)
0117 #define FTGMAC100_DBLAC_TXDES_SIZE(x)   (((x) & 0xf) << 16)
0118 #define FTGMAC100_DBLAC_IFG_CNT(x)  (((x) & 0x7) << 20)
0119 #define FTGMAC100_DBLAC_IFG_INC     (1 << 23)
0120
0121 /*
0122  * DMA FIFO status register
0123  */
0124 #define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos)  ((dmafifos) & 0xf)
0125 #define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos)  (((dmafifos) >> 4) & 0xf)
0126 #define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos)  (((dmafifos) >> 8) & 0x7)
0127 #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos)  (((dmafifos) >> 12) & 0xf)
0128 #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos)  (((dmafifos) >> 16) & 0x3)
0129 #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos)  (((dmafifos) >> 18) & 0xf)
0130 #define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY     (1 << 26)
0131 #define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY     (1 << 27)
0132 #define FTGMAC100_DMAFIFOS_RXDMA_GRANT      (1 << 28)
0133 #define FTGMAC100_DMAFIFOS_TXDMA_GRANT      (1 << 29)
0134 #define FTGMAC100_DMAFIFOS_RXDMA_REQ        (1 << 30)
0135 #define FTGMAC100_DMAFIFOS_TXDMA_REQ        (1 << 31)
0136
0137 /*
0138  * Feature Register
0139  */
0140 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE   BIT(31)
0141
0142 /*
0143  * Receive buffer size register
0144  */
0145 #define FTGMAC100_RBSR_SIZE(x)      ((x) & 0x3fff)
0146
0147 /*
0148  * MAC control register
0149  */
0150 #define FTGMAC100_MACCR_TXDMA_EN    (1 << 0)
0151 #define FTGMAC100_MACCR_RXDMA_EN    (1 << 1)
0152 #define FTGMAC100_MACCR_TXMAC_EN    (1 << 2)
0153 #define FTGMAC100_MACCR_RXMAC_EN    (1 << 3)
0154 #define FTGMAC100_MACCR_RM_VLAN     (1 << 4)
0155 #define FTGMAC100_MACCR_HPTXR_EN    (1 << 5)
0156 #define FTGMAC100_MACCR_LOOP_EN     (1 << 6)
0157 #define FTGMAC100_MACCR_ENRX_IN_HALFTX  (1 << 7)
0158 #define FTGMAC100_MACCR_FULLDUP     (1 << 8)
0159 #define FTGMAC100_MACCR_GIGA_MODE   (1 << 9)
0160 #define FTGMAC100_MACCR_CRC_APD     (1 << 10)
0161 #define FTGMAC100_MACCR_PHY_LINK_LEVEL  (1 << 11)
0162 #define FTGMAC100_MACCR_RX_RUNT     (1 << 12)
0163 #define FTGMAC100_MACCR_JUMBO_LF    (1 << 13)
0164 #define FTGMAC100_MACCR_RX_ALL      (1 << 14)
0165 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
0166 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
0167 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
0168 #define FTGMAC100_MACCR_DISCARD_CRCERR  (1 << 18)
0169 #define FTGMAC100_MACCR_FAST_MODE   (1 << 19)
0170 #define FTGMAC100_MACCR_SW_RST      (1 << 31)
0171
0172 /*
0173  * test mode control register
0174  */
0175 #define FTGMAC100_TM_RQ_TX_VALID_DIS (1 << 28)
0176 #define FTGMAC100_TM_RQ_RR_IDLE_PREV (1 << 27)
0177 #define FTGMAC100_TM_DEFAULT                                                   \
0178     (FTGMAC100_TM_RQ_TX_VALID_DIS | FTGMAC100_TM_RQ_RR_IDLE_PREV)
0179
0180 /*
0181  * PHY control register
0182  */
0183 #define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
0184 #define FTGMAC100_PHYCR_MDC_CYCTHR(x)   ((x) & 0x3f)
0185 #define FTGMAC100_PHYCR_PHYAD(x)    (((x) & 0x1f) << 16)
0186 #define FTGMAC100_PHYCR_REGAD(x)    (((x) & 0x1f) << 21)
0187 #define FTGMAC100_PHYCR_MIIRD       (1 << 26)
0188 #define FTGMAC100_PHYCR_MIIWR       (1 << 27)
0189
0190 /*
0191  * PHY data register
0192  */
0193 #define FTGMAC100_PHYDATA_MIIWDATA(x)       ((x) & 0xffff)
0194 #define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
0195
0196 /*
0197  * Flow control register
0198  */
0199 #define FTGMAC100_FCR_FC_EN     (1 << 0)
0200 #define FTGMAC100_FCR_FCTHR_EN      (1 << 2)
0201 #define FTGMAC100_FCR_PAUSE_TIME(x) (((x) & 0xffff) << 16)
0202
0203 /*
0204  * Transmit descriptor, aligned to 16 bytes
0205  */
0206 struct ftgmac100_txdes {
0207     __le32  txdes0; /* Control & status bits */
0208     __le32  txdes1; /* Irq, checksum and vlan control */
0209     __le32  txdes2; /* Reserved */
0210     __le32  txdes3; /* DMA buffer address */
0211 } __attribute__ ((aligned(16)));
0212
0213 #define FTGMAC100_TXDES0_TXBUF_SIZE(x)  ((x) & 0x3fff)
0214 #define FTGMAC100_TXDES0_CRC_ERR    (1 << 19)
0215 #define FTGMAC100_TXDES0_LTS        (1 << 28)
0216 #define FTGMAC100_TXDES0_FTS        (1 << 29)
0217 #define FTGMAC100_TXDES0_TXDMA_OWN  (1 << 31)
0218
0219 #define FTGMAC100_TXDES1_VLANTAG_CI(x)  ((x) & 0xffff)
0220 #define FTGMAC100_TXDES1_INS_VLANTAG    (1 << 16)
0221 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
0222 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
0223 #define FTGMAC100_TXDES1_IP_CHKSUM  (1 << 19)
0224 #define FTGMAC100_TXDES1_LLC        (1 << 22)
0225 #define FTGMAC100_TXDES1_TX2FIC     (1 << 30)
0226 #define FTGMAC100_TXDES1_TXIC       (1 << 31)
0227
0228 /*
0229  * Receive descriptor, aligned to 16 bytes
0230  */
0231 struct ftgmac100_rxdes {
0232     __le32  rxdes0; /* Control & status bits */
0233     __le32  rxdes1; /* Checksum and vlan status */
0234     __le32  rxdes2; /* length/type on AST2500 */
0235     __le32  rxdes3; /* DMA buffer address */
0236 } __attribute__ ((aligned(16)));
0237
0238 #define FTGMAC100_RXDES0_VDBC       0x3fff
0239 #define FTGMAC100_RXDES0_MULTICAST  (1 << 16)
0240 #define FTGMAC100_RXDES0_BROADCAST  (1 << 17)
0241 #define FTGMAC100_RXDES0_RX_ERR     (1 << 18)
0242 #define FTGMAC100_RXDES0_CRC_ERR    (1 << 19)
0243 #define FTGMAC100_RXDES0_FTL        (1 << 20)
0244 #define FTGMAC100_RXDES0_RUNT       (1 << 21)
0245 #define FTGMAC100_RXDES0_RX_ODD_NB  (1 << 22)
0246 #define FTGMAC100_RXDES0_FIFO_FULL  (1 << 23)
0247 #define FTGMAC100_RXDES0_PAUSE_OPCODE   (1 << 24)
0248 #define FTGMAC100_RXDES0_PAUSE_FRAME    (1 << 25)
0249 #define FTGMAC100_RXDES0_LRS        (1 << 28)
0250 #define FTGMAC100_RXDES0_FRS        (1 << 29)
0251 #define FTGMAC100_RXDES0_RXPKT_RDY  (1 << 31)
0252
0253 /* Errors we care about for dropping packets */
0254 #define RXDES0_ANY_ERROR        ( \
0255     FTGMAC100_RXDES0_RX_ERR     | \
0256     FTGMAC100_RXDES0_CRC_ERR    | \
0257     FTGMAC100_RXDES0_FTL        | \
0258     FTGMAC100_RXDES0_RUNT       | \
0259     FTGMAC100_RXDES0_RX_ODD_NB)
0260
0261 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
0262 #define FTGMAC100_RXDES1_PROT_MASK  (0x3 << 20)
0263 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
0264 #define FTGMAC100_RXDES1_PROT_IP    (0x1 << 20)
0265 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
0266 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
0267 #define FTGMAC100_RXDES1_LLC        (1 << 22)
0268 #define FTGMAC100_RXDES1_DF     (1 << 23)
0269 #define FTGMAC100_RXDES1_VLANTAG_AVAIL  (1 << 24)
0270 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
0271 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
0272 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR  (1 << 27)
0273
0274 #endif /* __FTGMAC100_H */