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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Faraday FTGMAC100 Gigabit Ethernet
0004  *
0005  * (C) Copyright 2009-2011 Faraday Technology
0006  * Po-Yu Chuang <ratbert@faraday-tech.com>
0007  */
0008 
0009 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0010 
0011 #include <linux/clk.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/etherdevice.h>
0014 #include <linux/ethtool.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/module.h>
0018 #include <linux/netdevice.h>
0019 #include <linux/of.h>
0020 #include <linux/of_mdio.h>
0021 #include <linux/phy.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/property.h>
0024 #include <linux/crc32.h>
0025 #include <linux/if_vlan.h>
0026 #include <linux/of_net.h>
0027 #include <net/ip.h>
0028 #include <net/ncsi.h>
0029 
0030 #include "ftgmac100.h"
0031 
0032 #define DRV_NAME    "ftgmac100"
0033 
0034 /* Arbitrary values, I am not sure the HW has limits */
0035 #define MAX_RX_QUEUE_ENTRIES    1024
0036 #define MAX_TX_QUEUE_ENTRIES    1024
0037 #define MIN_RX_QUEUE_ENTRIES    32
0038 #define MIN_TX_QUEUE_ENTRIES    32
0039 
0040 /* Defaults */
0041 #define DEF_RX_QUEUE_ENTRIES    128
0042 #define DEF_TX_QUEUE_ENTRIES    128
0043 
0044 #define MAX_PKT_SIZE        1536
0045 #define RX_BUF_SIZE     MAX_PKT_SIZE    /* must be smaller than 0x3fff */
0046 
0047 /* Min number of tx ring entries before stopping queue */
0048 #define TX_THRESHOLD        (MAX_SKB_FRAGS + 1)
0049 
0050 #define FTGMAC_100MHZ       100000000
0051 #define FTGMAC_25MHZ        25000000
0052 
0053 struct ftgmac100 {
0054     /* Registers */
0055     struct resource *res;
0056     void __iomem *base;
0057 
0058     /* Rx ring */
0059     unsigned int rx_q_entries;
0060     struct ftgmac100_rxdes *rxdes;
0061     dma_addr_t rxdes_dma;
0062     struct sk_buff **rx_skbs;
0063     unsigned int rx_pointer;
0064     u32 rxdes0_edorr_mask;
0065 
0066     /* Tx ring */
0067     unsigned int tx_q_entries;
0068     struct ftgmac100_txdes *txdes;
0069     dma_addr_t txdes_dma;
0070     struct sk_buff **tx_skbs;
0071     unsigned int tx_clean_pointer;
0072     unsigned int tx_pointer;
0073     u32 txdes0_edotr_mask;
0074 
0075     /* Used to signal the reset task of ring change request */
0076     unsigned int new_rx_q_entries;
0077     unsigned int new_tx_q_entries;
0078 
0079     /* Scratch page to use when rx skb alloc fails */
0080     void *rx_scratch;
0081     dma_addr_t rx_scratch_dma;
0082 
0083     /* Component structures */
0084     struct net_device *netdev;
0085     struct device *dev;
0086     struct ncsi_dev *ndev;
0087     struct napi_struct napi;
0088     struct work_struct reset_task;
0089     struct mii_bus *mii_bus;
0090     struct clk *clk;
0091 
0092     /* AST2500/AST2600 RMII ref clock gate */
0093     struct clk *rclk;
0094 
0095     /* Link management */
0096     int cur_speed;
0097     int cur_duplex;
0098     bool use_ncsi;
0099 
0100     /* Multicast filter settings */
0101     u32 maht0;
0102     u32 maht1;
0103 
0104     /* Flow control settings */
0105     bool tx_pause;
0106     bool rx_pause;
0107     bool aneg_pause;
0108 
0109     /* Misc */
0110     bool need_mac_restart;
0111     bool is_aspeed;
0112 };
0113 
0114 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
0115 {
0116     struct net_device *netdev = priv->netdev;
0117     int i;
0118 
0119     /* NOTE: reset clears all registers */
0120     iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
0121     iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
0122           priv->base + FTGMAC100_OFFSET_MACCR);
0123     for (i = 0; i < 200; i++) {
0124         unsigned int maccr;
0125 
0126         maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
0127         if (!(maccr & FTGMAC100_MACCR_SW_RST))
0128             return 0;
0129 
0130         udelay(1);
0131     }
0132 
0133     netdev_err(netdev, "Hardware reset failed\n");
0134     return -EIO;
0135 }
0136 
0137 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
0138 {
0139     u32 maccr = 0;
0140 
0141     switch (priv->cur_speed) {
0142     case SPEED_10:
0143     case 0: /* no link */
0144         break;
0145 
0146     case SPEED_100:
0147         maccr |= FTGMAC100_MACCR_FAST_MODE;
0148         break;
0149 
0150     case SPEED_1000:
0151         maccr |= FTGMAC100_MACCR_GIGA_MODE;
0152         break;
0153     default:
0154         netdev_err(priv->netdev, "Unknown speed %d !\n",
0155                priv->cur_speed);
0156         break;
0157     }
0158 
0159     /* (Re)initialize the queue pointers */
0160     priv->rx_pointer = 0;
0161     priv->tx_clean_pointer = 0;
0162     priv->tx_pointer = 0;
0163 
0164     /* The doc says reset twice with 10us interval */
0165     if (ftgmac100_reset_mac(priv, maccr))
0166         return -EIO;
0167     usleep_range(10, 1000);
0168     return ftgmac100_reset_mac(priv, maccr);
0169 }
0170 
0171 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
0172 {
0173     unsigned int maddr = mac[0] << 8 | mac[1];
0174     unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
0175 
0176     iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
0177     iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
0178 }
0179 
0180 static void ftgmac100_initial_mac(struct ftgmac100 *priv)
0181 {
0182     u8 mac[ETH_ALEN];
0183     unsigned int m;
0184     unsigned int l;
0185 
0186     if (!device_get_ethdev_address(priv->dev, priv->netdev)) {
0187         dev_info(priv->dev, "Read MAC address %pM from device tree\n",
0188              priv->netdev->dev_addr);
0189         return;
0190     }
0191 
0192     m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
0193     l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
0194 
0195     mac[0] = (m >> 8) & 0xff;
0196     mac[1] = m & 0xff;
0197     mac[2] = (l >> 24) & 0xff;
0198     mac[3] = (l >> 16) & 0xff;
0199     mac[4] = (l >> 8) & 0xff;
0200     mac[5] = l & 0xff;
0201 
0202     if (is_valid_ether_addr(mac)) {
0203         eth_hw_addr_set(priv->netdev, mac);
0204         dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
0205     } else {
0206         eth_hw_addr_random(priv->netdev);
0207         dev_info(priv->dev, "Generated random MAC address %pM\n",
0208              priv->netdev->dev_addr);
0209     }
0210 }
0211 
0212 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
0213 {
0214     int ret;
0215 
0216     ret = eth_prepare_mac_addr_change(dev, p);
0217     if (ret < 0)
0218         return ret;
0219 
0220     eth_commit_mac_addr_change(dev, p);
0221     ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
0222 
0223     return 0;
0224 }
0225 
0226 static void ftgmac100_config_pause(struct ftgmac100 *priv)
0227 {
0228     u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
0229 
0230     /* Throttle tx queue when receiving pause frames */
0231     if (priv->rx_pause)
0232         fcr |= FTGMAC100_FCR_FC_EN;
0233 
0234     /* Enables sending pause frames when the RX queue is past a
0235      * certain threshold.
0236      */
0237     if (priv->tx_pause)
0238         fcr |= FTGMAC100_FCR_FCTHR_EN;
0239 
0240     iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
0241 }
0242 
0243 static void ftgmac100_init_hw(struct ftgmac100 *priv)
0244 {
0245     u32 reg, rfifo_sz, tfifo_sz;
0246 
0247     /* Clear stale interrupts */
0248     reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
0249     iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
0250 
0251     /* Setup RX ring buffer base */
0252     iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
0253 
0254     /* Setup TX ring buffer base */
0255     iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
0256 
0257     /* Configure RX buffer size */
0258     iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
0259           priv->base + FTGMAC100_OFFSET_RBSR);
0260 
0261     /* Set RX descriptor autopoll */
0262     iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
0263           priv->base + FTGMAC100_OFFSET_APTC);
0264 
0265     /* Write MAC address */
0266     ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
0267 
0268     /* Write multicast filter */
0269     iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
0270     iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
0271 
0272     /* Configure descriptor sizes and increase burst sizes according
0273      * to values in Aspeed SDK. The FIFO arbitration is enabled and
0274      * the thresholds set based on the recommended values in the
0275      * AST2400 specification.
0276      */
0277     iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) |   /* 2*8 bytes RX descs */
0278           FTGMAC100_DBLAC_TXDES_SIZE(2) |   /* 2*8 bytes TX descs */
0279           FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
0280           FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
0281           FTGMAC100_DBLAC_RX_THR_EN |       /* Enable fifo threshold arb */
0282           FTGMAC100_DBLAC_RXFIFO_HTHR(6) |  /* 6/8 of FIFO high threshold */
0283           FTGMAC100_DBLAC_RXFIFO_LTHR(2),   /* 2/8 of FIFO low threshold */
0284           priv->base + FTGMAC100_OFFSET_DBLAC);
0285 
0286     /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
0287      * mitigation doesn't seem to provide any benefit with NAPI so leave
0288      * it at that.
0289      */
0290     iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
0291           FTGMAC100_ITC_TXINT_THR(1),
0292           priv->base + FTGMAC100_OFFSET_ITC);
0293 
0294     /* Configure FIFO sizes in the TPAFCR register */
0295     reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
0296     rfifo_sz = reg & 0x00000007;
0297     tfifo_sz = (reg >> 3) & 0x00000007;
0298     reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
0299     reg &= ~0x3f000000;
0300     reg |= (tfifo_sz << 27);
0301     reg |= (rfifo_sz << 24);
0302     iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
0303 }
0304 
0305 static void ftgmac100_start_hw(struct ftgmac100 *priv)
0306 {
0307     u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
0308 
0309     /* Keep the original GMAC and FAST bits */
0310     maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
0311 
0312     /* Add all the main enable bits */
0313     maccr |= FTGMAC100_MACCR_TXDMA_EN   |
0314          FTGMAC100_MACCR_RXDMA_EN   |
0315          FTGMAC100_MACCR_TXMAC_EN   |
0316          FTGMAC100_MACCR_RXMAC_EN   |
0317          FTGMAC100_MACCR_CRC_APD    |
0318          FTGMAC100_MACCR_PHY_LINK_LEVEL |
0319          FTGMAC100_MACCR_RX_RUNT    |
0320          FTGMAC100_MACCR_RX_BROADPKT;
0321 
0322     /* Add other bits as needed */
0323     if (priv->cur_duplex == DUPLEX_FULL)
0324         maccr |= FTGMAC100_MACCR_FULLDUP;
0325     if (priv->netdev->flags & IFF_PROMISC)
0326         maccr |= FTGMAC100_MACCR_RX_ALL;
0327     if (priv->netdev->flags & IFF_ALLMULTI)
0328         maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
0329     else if (netdev_mc_count(priv->netdev))
0330         maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
0331 
0332     /* Vlan filtering enabled */
0333     if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
0334         maccr |= FTGMAC100_MACCR_RM_VLAN;
0335 
0336     /* Hit the HW */
0337     iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
0338 }
0339 
0340 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
0341 {
0342     iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
0343 }
0344 
0345 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
0346 {
0347     struct netdev_hw_addr *ha;
0348 
0349     priv->maht1 = 0;
0350     priv->maht0 = 0;
0351     netdev_for_each_mc_addr(ha, priv->netdev) {
0352         u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
0353 
0354         crc_val = (~(crc_val >> 2)) & 0x3f;
0355         if (crc_val >= 32)
0356             priv->maht1 |= 1ul << (crc_val - 32);
0357         else
0358             priv->maht0 |= 1ul << (crc_val);
0359     }
0360 }
0361 
0362 static void ftgmac100_set_rx_mode(struct net_device *netdev)
0363 {
0364     struct ftgmac100 *priv = netdev_priv(netdev);
0365 
0366     /* Setup the hash filter */
0367     ftgmac100_calc_mc_hash(priv);
0368 
0369     /* Interface down ? that's all there is to do */
0370     if (!netif_running(netdev))
0371         return;
0372 
0373     /* Update the HW */
0374     iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
0375     iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
0376 
0377     /* Reconfigure MACCR */
0378     ftgmac100_start_hw(priv);
0379 }
0380 
0381 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
0382                   struct ftgmac100_rxdes *rxdes, gfp_t gfp)
0383 {
0384     struct net_device *netdev = priv->netdev;
0385     struct sk_buff *skb;
0386     dma_addr_t map;
0387     int err = 0;
0388 
0389     skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
0390     if (unlikely(!skb)) {
0391         if (net_ratelimit())
0392             netdev_warn(netdev, "failed to allocate rx skb\n");
0393         err = -ENOMEM;
0394         map = priv->rx_scratch_dma;
0395     } else {
0396         map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
0397                      DMA_FROM_DEVICE);
0398         if (unlikely(dma_mapping_error(priv->dev, map))) {
0399             if (net_ratelimit())
0400                 netdev_err(netdev, "failed to map rx page\n");
0401             dev_kfree_skb_any(skb);
0402             map = priv->rx_scratch_dma;
0403             skb = NULL;
0404             err = -ENOMEM;
0405         }
0406     }
0407 
0408     /* Store skb */
0409     priv->rx_skbs[entry] = skb;
0410 
0411     /* Store DMA address into RX desc */
0412     rxdes->rxdes3 = cpu_to_le32(map);
0413 
0414     /* Ensure the above is ordered vs clearing the OWN bit */
0415     dma_wmb();
0416 
0417     /* Clean status (which resets own bit) */
0418     if (entry == (priv->rx_q_entries - 1))
0419         rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
0420     else
0421         rxdes->rxdes0 = 0;
0422 
0423     return err;
0424 }
0425 
0426 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
0427                           unsigned int pointer)
0428 {
0429     return (pointer + 1) & (priv->rx_q_entries - 1);
0430 }
0431 
0432 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
0433 {
0434     struct net_device *netdev = priv->netdev;
0435 
0436     if (status & FTGMAC100_RXDES0_RX_ERR)
0437         netdev->stats.rx_errors++;
0438 
0439     if (status & FTGMAC100_RXDES0_CRC_ERR)
0440         netdev->stats.rx_crc_errors++;
0441 
0442     if (status & (FTGMAC100_RXDES0_FTL |
0443               FTGMAC100_RXDES0_RUNT |
0444               FTGMAC100_RXDES0_RX_ODD_NB))
0445         netdev->stats.rx_length_errors++;
0446 }
0447 
0448 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
0449 {
0450     struct net_device *netdev = priv->netdev;
0451     struct ftgmac100_rxdes *rxdes;
0452     struct sk_buff *skb;
0453     unsigned int pointer, size;
0454     u32 status, csum_vlan;
0455     dma_addr_t map;
0456 
0457     /* Grab next RX descriptor */
0458     pointer = priv->rx_pointer;
0459     rxdes = &priv->rxdes[pointer];
0460 
0461     /* Grab descriptor status */
0462     status = le32_to_cpu(rxdes->rxdes0);
0463 
0464     /* Do we have a packet ? */
0465     if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
0466         return false;
0467 
0468     /* Order subsequent reads with the test for the ready bit */
0469     dma_rmb();
0470 
0471     /* We don't cope with fragmented RX packets */
0472     if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
0473              !(status & FTGMAC100_RXDES0_LRS)))
0474         goto drop;
0475 
0476     /* Grab received size and csum vlan field in the descriptor */
0477     size = status & FTGMAC100_RXDES0_VDBC;
0478     csum_vlan = le32_to_cpu(rxdes->rxdes1);
0479 
0480     /* Any error (other than csum offload) flagged ? */
0481     if (unlikely(status & RXDES0_ANY_ERROR)) {
0482         /* Correct for incorrect flagging of runt packets
0483          * with vlan tags... Just accept a runt packet that
0484          * has been flagged as vlan and whose size is at
0485          * least 60 bytes.
0486          */
0487         if ((status & FTGMAC100_RXDES0_RUNT) &&
0488             (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
0489             (size >= 60))
0490             status &= ~FTGMAC100_RXDES0_RUNT;
0491 
0492         /* Any error still in there ? */
0493         if (status & RXDES0_ANY_ERROR) {
0494             ftgmac100_rx_packet_error(priv, status);
0495             goto drop;
0496         }
0497     }
0498 
0499     /* If the packet had no skb (failed to allocate earlier)
0500      * then try to allocate one and skip
0501      */
0502     skb = priv->rx_skbs[pointer];
0503     if (!unlikely(skb)) {
0504         ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
0505         goto drop;
0506     }
0507 
0508     if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
0509         netdev->stats.multicast++;
0510 
0511     /* If the HW found checksum errors, bounce it to software.
0512      *
0513      * If we didn't, we need to see if the packet was recognized
0514      * by HW as one of the supported checksummed protocols before
0515      * we accept the HW test results.
0516      */
0517     if (netdev->features & NETIF_F_RXCSUM) {
0518         u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
0519             FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
0520             FTGMAC100_RXDES1_IP_CHKSUM_ERR;
0521         if ((csum_vlan & err_bits) ||
0522             !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
0523             skb->ip_summed = CHECKSUM_NONE;
0524         else
0525             skb->ip_summed = CHECKSUM_UNNECESSARY;
0526     }
0527 
0528     /* Transfer received size to skb */
0529     skb_put(skb, size);
0530 
0531     /* Extract vlan tag */
0532     if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
0533         (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
0534         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
0535                        csum_vlan & 0xffff);
0536 
0537     /* Tear down DMA mapping, do necessary cache management */
0538     map = le32_to_cpu(rxdes->rxdes3);
0539 
0540 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
0541     /* When we don't have an iommu, we can save cycles by not
0542      * invalidating the cache for the part of the packet that
0543      * wasn't received.
0544      */
0545     dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
0546 #else
0547     dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
0548 #endif
0549 
0550 
0551     /* Resplenish rx ring */
0552     ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
0553     priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
0554 
0555     skb->protocol = eth_type_trans(skb, netdev);
0556 
0557     netdev->stats.rx_packets++;
0558     netdev->stats.rx_bytes += size;
0559 
0560     /* push packet to protocol stack */
0561     if (skb->ip_summed == CHECKSUM_NONE)
0562         netif_receive_skb(skb);
0563     else
0564         napi_gro_receive(&priv->napi, skb);
0565 
0566     (*processed)++;
0567     return true;
0568 
0569  drop:
0570     /* Clean rxdes0 (which resets own bit) */
0571     rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
0572     priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
0573     netdev->stats.rx_dropped++;
0574     return true;
0575 }
0576 
0577 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
0578                      unsigned int index)
0579 {
0580     if (index == (priv->tx_q_entries - 1))
0581         return priv->txdes0_edotr_mask;
0582     else
0583         return 0;
0584 }
0585 
0586 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
0587                           unsigned int pointer)
0588 {
0589     return (pointer + 1) & (priv->tx_q_entries - 1);
0590 }
0591 
0592 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
0593 {
0594     /* Returns the number of available slots in the TX queue
0595      *
0596      * This always leaves one free slot so we don't have to
0597      * worry about empty vs. full, and this simplifies the
0598      * test for ftgmac100_tx_buf_cleanable() below
0599      */
0600     return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
0601         (priv->tx_q_entries - 1);
0602 }
0603 
0604 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
0605 {
0606     return priv->tx_pointer != priv->tx_clean_pointer;
0607 }
0608 
0609 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
0610                      unsigned int pointer,
0611                      struct sk_buff *skb,
0612                      struct ftgmac100_txdes *txdes,
0613                      u32 ctl_stat)
0614 {
0615     dma_addr_t map = le32_to_cpu(txdes->txdes3);
0616     size_t len;
0617 
0618     if (ctl_stat & FTGMAC100_TXDES0_FTS) {
0619         len = skb_headlen(skb);
0620         dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
0621     } else {
0622         len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
0623         dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
0624     }
0625 
0626     /* Free SKB on last segment */
0627     if (ctl_stat & FTGMAC100_TXDES0_LTS)
0628         dev_kfree_skb(skb);
0629     priv->tx_skbs[pointer] = NULL;
0630 }
0631 
0632 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
0633 {
0634     struct net_device *netdev = priv->netdev;
0635     struct ftgmac100_txdes *txdes;
0636     struct sk_buff *skb;
0637     unsigned int pointer;
0638     u32 ctl_stat;
0639 
0640     pointer = priv->tx_clean_pointer;
0641     txdes = &priv->txdes[pointer];
0642 
0643     ctl_stat = le32_to_cpu(txdes->txdes0);
0644     if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
0645         return false;
0646 
0647     skb = priv->tx_skbs[pointer];
0648     netdev->stats.tx_packets++;
0649     netdev->stats.tx_bytes += skb->len;
0650     ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
0651     txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
0652 
0653     priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
0654 
0655     return true;
0656 }
0657 
0658 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
0659 {
0660     struct net_device *netdev = priv->netdev;
0661 
0662     /* Process all completed packets */
0663     while (ftgmac100_tx_buf_cleanable(priv) &&
0664            ftgmac100_tx_complete_packet(priv))
0665         ;
0666 
0667     /* Restart queue if needed */
0668     smp_mb();
0669     if (unlikely(netif_queue_stopped(netdev) &&
0670              ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
0671         struct netdev_queue *txq;
0672 
0673         txq = netdev_get_tx_queue(netdev, 0);
0674         __netif_tx_lock(txq, smp_processor_id());
0675         if (netif_queue_stopped(netdev) &&
0676             ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
0677             netif_wake_queue(netdev);
0678         __netif_tx_unlock(txq);
0679     }
0680 }
0681 
0682 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
0683 {
0684     if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
0685         u8 ip_proto = ip_hdr(skb)->protocol;
0686 
0687         *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
0688         switch(ip_proto) {
0689         case IPPROTO_TCP:
0690             *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
0691             return true;
0692         case IPPROTO_UDP:
0693             *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
0694             return true;
0695         case IPPROTO_IP:
0696             return true;
0697         }
0698     }
0699     return skb_checksum_help(skb) == 0;
0700 }
0701 
0702 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
0703                          struct net_device *netdev)
0704 {
0705     struct ftgmac100 *priv = netdev_priv(netdev);
0706     struct ftgmac100_txdes *txdes, *first;
0707     unsigned int pointer, nfrags, len, i, j;
0708     u32 f_ctl_stat, ctl_stat, csum_vlan;
0709     dma_addr_t map;
0710 
0711     /* The HW doesn't pad small frames */
0712     if (eth_skb_pad(skb)) {
0713         netdev->stats.tx_dropped++;
0714         return NETDEV_TX_OK;
0715     }
0716 
0717     /* Reject oversize packets */
0718     if (unlikely(skb->len > MAX_PKT_SIZE)) {
0719         if (net_ratelimit())
0720             netdev_dbg(netdev, "tx packet too big\n");
0721         goto drop;
0722     }
0723 
0724     /* Do we have a limit on #fragments ? I yet have to get a reply
0725      * from Aspeed. If there's one I haven't hit it.
0726      */
0727     nfrags = skb_shinfo(skb)->nr_frags;
0728 
0729     /* Setup HW checksumming */
0730     csum_vlan = 0;
0731     if (skb->ip_summed == CHECKSUM_PARTIAL &&
0732         !ftgmac100_prep_tx_csum(skb, &csum_vlan))
0733         goto drop;
0734 
0735     /* Add VLAN tag */
0736     if (skb_vlan_tag_present(skb)) {
0737         csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
0738         csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
0739     }
0740 
0741     /* Get header len */
0742     len = skb_headlen(skb);
0743 
0744     /* Map the packet head */
0745     map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
0746     if (dma_mapping_error(priv->dev, map)) {
0747         if (net_ratelimit())
0748             netdev_err(netdev, "map tx packet head failed\n");
0749         goto drop;
0750     }
0751 
0752     /* Grab the next free tx descriptor */
0753     pointer = priv->tx_pointer;
0754     txdes = first = &priv->txdes[pointer];
0755 
0756     /* Setup it up with the packet head. Don't write the head to the
0757      * ring just yet
0758      */
0759     priv->tx_skbs[pointer] = skb;
0760     f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
0761     f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
0762     f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
0763     f_ctl_stat |= FTGMAC100_TXDES0_FTS;
0764     if (nfrags == 0)
0765         f_ctl_stat |= FTGMAC100_TXDES0_LTS;
0766     txdes->txdes3 = cpu_to_le32(map);
0767     txdes->txdes1 = cpu_to_le32(csum_vlan);
0768 
0769     /* Next descriptor */
0770     pointer = ftgmac100_next_tx_pointer(priv, pointer);
0771 
0772     /* Add the fragments */
0773     for (i = 0; i < nfrags; i++) {
0774         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0775 
0776         len = skb_frag_size(frag);
0777 
0778         /* Map it */
0779         map = skb_frag_dma_map(priv->dev, frag, 0, len,
0780                        DMA_TO_DEVICE);
0781         if (dma_mapping_error(priv->dev, map))
0782             goto dma_err;
0783 
0784         /* Setup descriptor */
0785         priv->tx_skbs[pointer] = skb;
0786         txdes = &priv->txdes[pointer];
0787         ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
0788         ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
0789         ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
0790         if (i == (nfrags - 1))
0791             ctl_stat |= FTGMAC100_TXDES0_LTS;
0792         txdes->txdes0 = cpu_to_le32(ctl_stat);
0793         txdes->txdes1 = 0;
0794         txdes->txdes3 = cpu_to_le32(map);
0795 
0796         /* Next one */
0797         pointer = ftgmac100_next_tx_pointer(priv, pointer);
0798     }
0799 
0800     /* Order the previous packet and descriptor udpates
0801      * before setting the OWN bit on the first descriptor.
0802      */
0803     dma_wmb();
0804     first->txdes0 = cpu_to_le32(f_ctl_stat);
0805 
0806     /* Update next TX pointer */
0807     priv->tx_pointer = pointer;
0808 
0809     /* If there isn't enough room for all the fragments of a new packet
0810      * in the TX ring, stop the queue. The sequence below is race free
0811      * vs. a concurrent restart in ftgmac100_poll()
0812      */
0813     if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
0814         netif_stop_queue(netdev);
0815         /* Order the queue stop with the test below */
0816         smp_mb();
0817         if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
0818             netif_wake_queue(netdev);
0819     }
0820 
0821     /* Poke transmitter to read the updated TX descriptors */
0822     iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
0823 
0824     return NETDEV_TX_OK;
0825 
0826  dma_err:
0827     if (net_ratelimit())
0828         netdev_err(netdev, "map tx fragment failed\n");
0829 
0830     /* Free head */
0831     pointer = priv->tx_pointer;
0832     ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
0833     first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
0834 
0835     /* Then all fragments */
0836     for (j = 0; j < i; j++) {
0837         pointer = ftgmac100_next_tx_pointer(priv, pointer);
0838         txdes = &priv->txdes[pointer];
0839         ctl_stat = le32_to_cpu(txdes->txdes0);
0840         ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
0841         txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
0842     }
0843 
0844     /* This cannot be reached if we successfully mapped the
0845      * last fragment, so we know ftgmac100_free_tx_packet()
0846      * hasn't freed the skb yet.
0847      */
0848  drop:
0849     /* Drop the packet */
0850     dev_kfree_skb_any(skb);
0851     netdev->stats.tx_dropped++;
0852 
0853     return NETDEV_TX_OK;
0854 }
0855 
0856 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
0857 {
0858     int i;
0859 
0860     /* Free all RX buffers */
0861     for (i = 0; i < priv->rx_q_entries; i++) {
0862         struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
0863         struct sk_buff *skb = priv->rx_skbs[i];
0864         dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
0865 
0866         if (!skb)
0867             continue;
0868 
0869         priv->rx_skbs[i] = NULL;
0870         dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
0871         dev_kfree_skb_any(skb);
0872     }
0873 
0874     /* Free all TX buffers */
0875     for (i = 0; i < priv->tx_q_entries; i++) {
0876         struct ftgmac100_txdes *txdes = &priv->txdes[i];
0877         struct sk_buff *skb = priv->tx_skbs[i];
0878 
0879         if (!skb)
0880             continue;
0881         ftgmac100_free_tx_packet(priv, i, skb, txdes,
0882                      le32_to_cpu(txdes->txdes0));
0883     }
0884 }
0885 
0886 static void ftgmac100_free_rings(struct ftgmac100 *priv)
0887 {
0888     /* Free skb arrays */
0889     kfree(priv->rx_skbs);
0890     kfree(priv->tx_skbs);
0891 
0892     /* Free descriptors */
0893     if (priv->rxdes)
0894         dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
0895                   sizeof(struct ftgmac100_rxdes),
0896                   priv->rxdes, priv->rxdes_dma);
0897     priv->rxdes = NULL;
0898 
0899     if (priv->txdes)
0900         dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
0901                   sizeof(struct ftgmac100_txdes),
0902                   priv->txdes, priv->txdes_dma);
0903     priv->txdes = NULL;
0904 
0905     /* Free scratch packet buffer */
0906     if (priv->rx_scratch)
0907         dma_free_coherent(priv->dev, RX_BUF_SIZE,
0908                   priv->rx_scratch, priv->rx_scratch_dma);
0909 }
0910 
0911 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
0912 {
0913     /* Allocate skb arrays */
0914     priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
0915                 GFP_KERNEL);
0916     if (!priv->rx_skbs)
0917         return -ENOMEM;
0918     priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
0919                 GFP_KERNEL);
0920     if (!priv->tx_skbs)
0921         return -ENOMEM;
0922 
0923     /* Allocate descriptors */
0924     priv->rxdes = dma_alloc_coherent(priv->dev,
0925                      MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
0926                      &priv->rxdes_dma, GFP_KERNEL);
0927     if (!priv->rxdes)
0928         return -ENOMEM;
0929     priv->txdes = dma_alloc_coherent(priv->dev,
0930                      MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
0931                      &priv->txdes_dma, GFP_KERNEL);
0932     if (!priv->txdes)
0933         return -ENOMEM;
0934 
0935     /* Allocate scratch packet buffer */
0936     priv->rx_scratch = dma_alloc_coherent(priv->dev,
0937                           RX_BUF_SIZE,
0938                           &priv->rx_scratch_dma,
0939                           GFP_KERNEL);
0940     if (!priv->rx_scratch)
0941         return -ENOMEM;
0942 
0943     return 0;
0944 }
0945 
0946 static void ftgmac100_init_rings(struct ftgmac100 *priv)
0947 {
0948     struct ftgmac100_rxdes *rxdes = NULL;
0949     struct ftgmac100_txdes *txdes = NULL;
0950     int i;
0951 
0952     /* Update entries counts */
0953     priv->rx_q_entries = priv->new_rx_q_entries;
0954     priv->tx_q_entries = priv->new_tx_q_entries;
0955 
0956     if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
0957         return;
0958 
0959     /* Initialize RX ring */
0960     for (i = 0; i < priv->rx_q_entries; i++) {
0961         rxdes = &priv->rxdes[i];
0962         rxdes->rxdes0 = 0;
0963         rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
0964     }
0965     /* Mark the end of the ring */
0966     rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
0967 
0968     if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
0969         return;
0970 
0971     /* Initialize TX ring */
0972     for (i = 0; i < priv->tx_q_entries; i++) {
0973         txdes = &priv->txdes[i];
0974         txdes->txdes0 = 0;
0975     }
0976     txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
0977 }
0978 
0979 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
0980 {
0981     int i;
0982 
0983     for (i = 0; i < priv->rx_q_entries; i++) {
0984         struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
0985 
0986         if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
0987             return -ENOMEM;
0988     }
0989     return 0;
0990 }
0991 
0992 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
0993 {
0994     struct net_device *netdev = bus->priv;
0995     struct ftgmac100 *priv = netdev_priv(netdev);
0996     unsigned int phycr;
0997     int i;
0998 
0999     phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1000 
1001     /* preserve MDC cycle threshold */
1002     phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1003 
1004     phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1005          FTGMAC100_PHYCR_REGAD(regnum) |
1006          FTGMAC100_PHYCR_MIIRD;
1007 
1008     iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1009 
1010     for (i = 0; i < 10; i++) {
1011         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1012 
1013         if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1014             int data;
1015 
1016             data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1017             return FTGMAC100_PHYDATA_MIIRDATA(data);
1018         }
1019 
1020         udelay(100);
1021     }
1022 
1023     netdev_err(netdev, "mdio read timed out\n");
1024     return -EIO;
1025 }
1026 
1027 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1028                    int regnum, u16 value)
1029 {
1030     struct net_device *netdev = bus->priv;
1031     struct ftgmac100 *priv = netdev_priv(netdev);
1032     unsigned int phycr;
1033     int data;
1034     int i;
1035 
1036     phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1037 
1038     /* preserve MDC cycle threshold */
1039     phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1040 
1041     phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1042          FTGMAC100_PHYCR_REGAD(regnum) |
1043          FTGMAC100_PHYCR_MIIWR;
1044 
1045     data = FTGMAC100_PHYDATA_MIIWDATA(value);
1046 
1047     iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1048     iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1049 
1050     for (i = 0; i < 10; i++) {
1051         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1052 
1053         if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1054             return 0;
1055 
1056         udelay(100);
1057     }
1058 
1059     netdev_err(netdev, "mdio write timed out\n");
1060     return -EIO;
1061 }
1062 
1063 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1064                   struct ethtool_drvinfo *info)
1065 {
1066     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1067     strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1068 }
1069 
1070 static void
1071 ftgmac100_get_ringparam(struct net_device *netdev,
1072             struct ethtool_ringparam *ering,
1073             struct kernel_ethtool_ringparam *kernel_ering,
1074             struct netlink_ext_ack *extack)
1075 {
1076     struct ftgmac100 *priv = netdev_priv(netdev);
1077 
1078     memset(ering, 0, sizeof(*ering));
1079     ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1080     ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1081     ering->rx_pending = priv->rx_q_entries;
1082     ering->tx_pending = priv->tx_q_entries;
1083 }
1084 
1085 static int
1086 ftgmac100_set_ringparam(struct net_device *netdev,
1087             struct ethtool_ringparam *ering,
1088             struct kernel_ethtool_ringparam *kernel_ering,
1089             struct netlink_ext_ack *extack)
1090 {
1091     struct ftgmac100 *priv = netdev_priv(netdev);
1092 
1093     if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1094         ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1095         ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1096         ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1097         !is_power_of_2(ering->rx_pending) ||
1098         !is_power_of_2(ering->tx_pending))
1099         return -EINVAL;
1100 
1101     priv->new_rx_q_entries = ering->rx_pending;
1102     priv->new_tx_q_entries = ering->tx_pending;
1103     if (netif_running(netdev))
1104         schedule_work(&priv->reset_task);
1105 
1106     return 0;
1107 }
1108 
1109 static void ftgmac100_get_pauseparam(struct net_device *netdev,
1110                      struct ethtool_pauseparam *pause)
1111 {
1112     struct ftgmac100 *priv = netdev_priv(netdev);
1113 
1114     pause->autoneg = priv->aneg_pause;
1115     pause->tx_pause = priv->tx_pause;
1116     pause->rx_pause = priv->rx_pause;
1117 }
1118 
1119 static int ftgmac100_set_pauseparam(struct net_device *netdev,
1120                     struct ethtool_pauseparam *pause)
1121 {
1122     struct ftgmac100 *priv = netdev_priv(netdev);
1123     struct phy_device *phydev = netdev->phydev;
1124 
1125     priv->aneg_pause = pause->autoneg;
1126     priv->tx_pause = pause->tx_pause;
1127     priv->rx_pause = pause->rx_pause;
1128 
1129     if (phydev)
1130         phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1131 
1132     if (netif_running(netdev)) {
1133         if (!(phydev && priv->aneg_pause))
1134             ftgmac100_config_pause(priv);
1135     }
1136 
1137     return 0;
1138 }
1139 
1140 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1141     .get_drvinfo        = ftgmac100_get_drvinfo,
1142     .get_link       = ethtool_op_get_link,
1143     .get_link_ksettings = phy_ethtool_get_link_ksettings,
1144     .set_link_ksettings = phy_ethtool_set_link_ksettings,
1145     .nway_reset     = phy_ethtool_nway_reset,
1146     .get_ringparam      = ftgmac100_get_ringparam,
1147     .set_ringparam      = ftgmac100_set_ringparam,
1148     .get_pauseparam     = ftgmac100_get_pauseparam,
1149     .set_pauseparam     = ftgmac100_set_pauseparam,
1150 };
1151 
1152 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1153 {
1154     struct net_device *netdev = dev_id;
1155     struct ftgmac100 *priv = netdev_priv(netdev);
1156     unsigned int status, new_mask = FTGMAC100_INT_BAD;
1157 
1158     /* Fetch and clear interrupt bits, process abnormal ones */
1159     status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1160     iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1161     if (unlikely(status & FTGMAC100_INT_BAD)) {
1162 
1163         /* RX buffer unavailable */
1164         if (status & FTGMAC100_INT_NO_RXBUF)
1165             netdev->stats.rx_over_errors++;
1166 
1167         /* received packet lost due to RX FIFO full */
1168         if (status & FTGMAC100_INT_RPKT_LOST)
1169             netdev->stats.rx_fifo_errors++;
1170 
1171         /* sent packet lost due to excessive TX collision */
1172         if (status & FTGMAC100_INT_XPKT_LOST)
1173             netdev->stats.tx_fifo_errors++;
1174 
1175         /* AHB error -> Reset the chip */
1176         if (status & FTGMAC100_INT_AHB_ERR) {
1177             if (net_ratelimit())
1178                 netdev_warn(netdev,
1179                        "AHB bus error ! Resetting chip.\n");
1180             iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1181             schedule_work(&priv->reset_task);
1182             return IRQ_HANDLED;
1183         }
1184 
1185         /* We may need to restart the MAC after such errors, delay
1186          * this until after we have freed some Rx buffers though
1187          */
1188         priv->need_mac_restart = true;
1189 
1190         /* Disable those errors until we restart */
1191         new_mask &= ~status;
1192     }
1193 
1194     /* Only enable "bad" interrupts while NAPI is on */
1195     iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1196 
1197     /* Schedule NAPI bh */
1198     napi_schedule_irqoff(&priv->napi);
1199 
1200     return IRQ_HANDLED;
1201 }
1202 
1203 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1204 {
1205     struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1206 
1207     /* Do we have a packet ? */
1208     return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1209 }
1210 
1211 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1212 {
1213     struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1214     int work_done = 0;
1215     bool more;
1216 
1217     /* Handle TX completions */
1218     if (ftgmac100_tx_buf_cleanable(priv))
1219         ftgmac100_tx_complete(priv);
1220 
1221     /* Handle RX packets */
1222     do {
1223         more = ftgmac100_rx_packet(priv, &work_done);
1224     } while (more && work_done < budget);
1225 
1226 
1227     /* The interrupt is telling us to kick the MAC back to life
1228      * after an RX overflow
1229      */
1230     if (unlikely(priv->need_mac_restart)) {
1231         ftgmac100_start_hw(priv);
1232         priv->need_mac_restart = false;
1233 
1234         /* Re-enable "bad" interrupts */
1235         iowrite32(FTGMAC100_INT_BAD,
1236               priv->base + FTGMAC100_OFFSET_IER);
1237     }
1238 
1239     /* As long as we are waiting for transmit packets to be
1240      * completed we keep NAPI going
1241      */
1242     if (ftgmac100_tx_buf_cleanable(priv))
1243         work_done = budget;
1244 
1245     if (work_done < budget) {
1246         /* We are about to re-enable all interrupts. However
1247          * the HW has been latching RX/TX packet interrupts while
1248          * they were masked. So we clear them first, then we need
1249          * to re-check if there's something to process
1250          */
1251         iowrite32(FTGMAC100_INT_RXTX,
1252               priv->base + FTGMAC100_OFFSET_ISR);
1253 
1254         /* Push the above (and provides a barrier vs. subsequent
1255          * reads of the descriptor).
1256          */
1257         ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1258 
1259         /* Check RX and TX descriptors for more work to do */
1260         if (ftgmac100_check_rx(priv) ||
1261             ftgmac100_tx_buf_cleanable(priv))
1262             return budget;
1263 
1264         /* deschedule NAPI */
1265         napi_complete(napi);
1266 
1267         /* enable all interrupts */
1268         iowrite32(FTGMAC100_INT_ALL,
1269               priv->base + FTGMAC100_OFFSET_IER);
1270     }
1271 
1272     return work_done;
1273 }
1274 
1275 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1276 {
1277     int err = 0;
1278 
1279     /* Re-init descriptors (adjust queue sizes) */
1280     ftgmac100_init_rings(priv);
1281 
1282     /* Realloc rx descriptors */
1283     err = ftgmac100_alloc_rx_buffers(priv);
1284     if (err && !ignore_alloc_err)
1285         return err;
1286 
1287     /* Reinit and restart HW */
1288     ftgmac100_init_hw(priv);
1289     ftgmac100_config_pause(priv);
1290     ftgmac100_start_hw(priv);
1291 
1292     /* Re-enable the device */
1293     napi_enable(&priv->napi);
1294     netif_start_queue(priv->netdev);
1295 
1296     /* Enable all interrupts */
1297     iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1298 
1299     return err;
1300 }
1301 
1302 static void ftgmac100_reset(struct ftgmac100 *priv)
1303 {
1304     struct net_device *netdev = priv->netdev;
1305     int err;
1306 
1307     netdev_dbg(netdev, "Resetting NIC...\n");
1308 
1309     /* Lock the world */
1310     rtnl_lock();
1311     if (netdev->phydev)
1312         mutex_lock(&netdev->phydev->lock);
1313     if (priv->mii_bus)
1314         mutex_lock(&priv->mii_bus->mdio_lock);
1315 
1316 
1317     /* Check if the interface is still up */
1318     if (!netif_running(netdev))
1319         goto bail;
1320 
1321     /* Stop the network stack */
1322     netif_trans_update(netdev);
1323     napi_disable(&priv->napi);
1324     netif_tx_disable(netdev);
1325 
1326     /* Stop and reset the MAC */
1327     ftgmac100_stop_hw(priv);
1328     err = ftgmac100_reset_and_config_mac(priv);
1329     if (err) {
1330         /* Not much we can do ... it might come back... */
1331         netdev_err(netdev, "attempting to continue...\n");
1332     }
1333 
1334     /* Free all rx and tx buffers */
1335     ftgmac100_free_buffers(priv);
1336 
1337     /* Setup everything again and restart chip */
1338     ftgmac100_init_all(priv, true);
1339 
1340     netdev_dbg(netdev, "Reset done !\n");
1341  bail:
1342     if (priv->mii_bus)
1343         mutex_unlock(&priv->mii_bus->mdio_lock);
1344     if (netdev->phydev)
1345         mutex_unlock(&netdev->phydev->lock);
1346     rtnl_unlock();
1347 }
1348 
1349 static void ftgmac100_reset_task(struct work_struct *work)
1350 {
1351     struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1352                           reset_task);
1353 
1354     ftgmac100_reset(priv);
1355 }
1356 
1357 static void ftgmac100_adjust_link(struct net_device *netdev)
1358 {
1359     struct ftgmac100 *priv = netdev_priv(netdev);
1360     struct phy_device *phydev = netdev->phydev;
1361     bool tx_pause, rx_pause;
1362     int new_speed;
1363 
1364     /* We store "no link" as speed 0 */
1365     if (!phydev->link)
1366         new_speed = 0;
1367     else
1368         new_speed = phydev->speed;
1369 
1370     /* Grab pause settings from PHY if configured to do so */
1371     if (priv->aneg_pause) {
1372         rx_pause = tx_pause = phydev->pause;
1373         if (phydev->asym_pause)
1374             tx_pause = !rx_pause;
1375     } else {
1376         rx_pause = priv->rx_pause;
1377         tx_pause = priv->tx_pause;
1378     }
1379 
1380     /* Link hasn't changed, do nothing */
1381     if (phydev->speed == priv->cur_speed &&
1382         phydev->duplex == priv->cur_duplex &&
1383         rx_pause == priv->rx_pause &&
1384         tx_pause == priv->tx_pause)
1385         return;
1386 
1387     /* Print status if we have a link or we had one and just lost it,
1388      * don't print otherwise.
1389      */
1390     if (new_speed || priv->cur_speed)
1391         phy_print_status(phydev);
1392 
1393     priv->cur_speed = new_speed;
1394     priv->cur_duplex = phydev->duplex;
1395     priv->rx_pause = rx_pause;
1396     priv->tx_pause = tx_pause;
1397 
1398     /* Link is down, do nothing else */
1399     if (!new_speed)
1400         return;
1401 
1402     /* Disable all interrupts */
1403     iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1404 
1405     /* Release phy lock to allow ftgmac100_reset to aquire it, keeping lock
1406      * order consistent to prevent dead lock.
1407      */
1408     if (netdev->phydev)
1409         mutex_unlock(&netdev->phydev->lock);
1410 
1411     ftgmac100_reset(priv);
1412 
1413     if (netdev->phydev)
1414         mutex_lock(&netdev->phydev->lock);
1415 
1416 }
1417 
1418 static int ftgmac100_mii_probe(struct net_device *netdev)
1419 {
1420     struct ftgmac100 *priv = netdev_priv(netdev);
1421     struct platform_device *pdev = to_platform_device(priv->dev);
1422     struct device_node *np = pdev->dev.of_node;
1423     struct phy_device *phydev;
1424     phy_interface_t phy_intf;
1425     int err;
1426 
1427     /* Default to RGMII. It's a gigabit part after all */
1428     err = of_get_phy_mode(np, &phy_intf);
1429     if (err)
1430         phy_intf = PHY_INTERFACE_MODE_RGMII;
1431 
1432     /* Aspeed only supports these. I don't know about other IP
1433      * block vendors so I'm going to just let them through for
1434      * now. Note that this is only a warning if for some obscure
1435      * reason the DT really means to lie about it or it's a newer
1436      * part we don't know about.
1437      *
1438      * On the Aspeed SoC there are additionally straps and SCU
1439      * control bits that could tell us what the interface is
1440      * (or allow us to configure it while the IP block is held
1441      * in reset). For now I chose to keep this driver away from
1442      * those SoC specific bits and assume the device-tree is
1443      * right and the SCU has been configured properly by pinmux
1444      * or the firmware.
1445      */
1446     if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) {
1447         netdev_warn(netdev,
1448                 "Unsupported PHY mode %s !\n",
1449                 phy_modes(phy_intf));
1450     }
1451 
1452     phydev = phy_find_first(priv->mii_bus);
1453     if (!phydev) {
1454         netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1455         return -ENODEV;
1456     }
1457 
1458     phydev = phy_connect(netdev, phydev_name(phydev),
1459                  &ftgmac100_adjust_link, phy_intf);
1460 
1461     if (IS_ERR(phydev)) {
1462         netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1463         return PTR_ERR(phydev);
1464     }
1465 
1466     /* Indicate that we support PAUSE frames (see comment in
1467      * Documentation/networking/phy.rst)
1468      */
1469     phy_support_asym_pause(phydev);
1470 
1471     /* Display what we found */
1472     phy_attached_info(phydev);
1473 
1474     return 0;
1475 }
1476 
1477 static int ftgmac100_open(struct net_device *netdev)
1478 {
1479     struct ftgmac100 *priv = netdev_priv(netdev);
1480     int err;
1481 
1482     /* Allocate ring buffers  */
1483     err = ftgmac100_alloc_rings(priv);
1484     if (err) {
1485         netdev_err(netdev, "Failed to allocate descriptors\n");
1486         return err;
1487     }
1488 
1489     /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1490      *
1491      * Otherwise we leave it set to 0 (no link), the link
1492      * message from the PHY layer will handle setting it up to
1493      * something else if needed.
1494      */
1495     if (priv->use_ncsi) {
1496         priv->cur_duplex = DUPLEX_FULL;
1497         priv->cur_speed = SPEED_100;
1498     } else {
1499         priv->cur_duplex = 0;
1500         priv->cur_speed = 0;
1501     }
1502 
1503     /* Reset the hardware */
1504     err = ftgmac100_reset_and_config_mac(priv);
1505     if (err)
1506         goto err_hw;
1507 
1508     /* Initialize NAPI */
1509     netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1510 
1511     /* Grab our interrupt */
1512     err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1513     if (err) {
1514         netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1515         goto err_irq;
1516     }
1517 
1518     /* Start things up */
1519     err = ftgmac100_init_all(priv, false);
1520     if (err) {
1521         netdev_err(netdev, "Failed to allocate packet buffers\n");
1522         goto err_alloc;
1523     }
1524 
1525     if (netdev->phydev) {
1526         /* If we have a PHY, start polling */
1527         phy_start(netdev->phydev);
1528     } else if (priv->use_ncsi) {
1529         /* If using NC-SI, set our carrier on and start the stack */
1530         netif_carrier_on(netdev);
1531 
1532         /* Start the NCSI device */
1533         err = ncsi_start_dev(priv->ndev);
1534         if (err)
1535             goto err_ncsi;
1536     }
1537 
1538     return 0;
1539 
1540  err_ncsi:
1541     napi_disable(&priv->napi);
1542     netif_stop_queue(netdev);
1543  err_alloc:
1544     ftgmac100_free_buffers(priv);
1545     free_irq(netdev->irq, netdev);
1546  err_irq:
1547     netif_napi_del(&priv->napi);
1548  err_hw:
1549     iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1550     ftgmac100_free_rings(priv);
1551     return err;
1552 }
1553 
1554 static int ftgmac100_stop(struct net_device *netdev)
1555 {
1556     struct ftgmac100 *priv = netdev_priv(netdev);
1557 
1558     /* Note about the reset task: We are called with the rtnl lock
1559      * held, so we are synchronized against the core of the reset
1560      * task. We must not try to synchronously cancel it otherwise
1561      * we can deadlock. But since it will test for netif_running()
1562      * which has already been cleared by the net core, we don't
1563      * anything special to do.
1564      */
1565 
1566     /* disable all interrupts */
1567     iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1568 
1569     netif_stop_queue(netdev);
1570     napi_disable(&priv->napi);
1571     netif_napi_del(&priv->napi);
1572     if (netdev->phydev)
1573         phy_stop(netdev->phydev);
1574     else if (priv->use_ncsi)
1575         ncsi_stop_dev(priv->ndev);
1576 
1577     ftgmac100_stop_hw(priv);
1578     free_irq(netdev->irq, netdev);
1579     ftgmac100_free_buffers(priv);
1580     ftgmac100_free_rings(priv);
1581 
1582     return 0;
1583 }
1584 
1585 static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1586 {
1587     struct ftgmac100 *priv = netdev_priv(netdev);
1588 
1589     /* Disable all interrupts */
1590     iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1591 
1592     /* Do the reset outside of interrupt context */
1593     schedule_work(&priv->reset_task);
1594 }
1595 
1596 static int ftgmac100_set_features(struct net_device *netdev,
1597                   netdev_features_t features)
1598 {
1599     struct ftgmac100 *priv = netdev_priv(netdev);
1600     netdev_features_t changed = netdev->features ^ features;
1601 
1602     if (!netif_running(netdev))
1603         return 0;
1604 
1605     /* Update the vlan filtering bit */
1606     if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1607         u32 maccr;
1608 
1609         maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1610         if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1611             maccr |= FTGMAC100_MACCR_RM_VLAN;
1612         else
1613             maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1614         iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1615     }
1616 
1617     return 0;
1618 }
1619 
1620 #ifdef CONFIG_NET_POLL_CONTROLLER
1621 static void ftgmac100_poll_controller(struct net_device *netdev)
1622 {
1623     unsigned long flags;
1624 
1625     local_irq_save(flags);
1626     ftgmac100_interrupt(netdev->irq, netdev);
1627     local_irq_restore(flags);
1628 }
1629 #endif
1630 
1631 static const struct net_device_ops ftgmac100_netdev_ops = {
1632     .ndo_open       = ftgmac100_open,
1633     .ndo_stop       = ftgmac100_stop,
1634     .ndo_start_xmit     = ftgmac100_hard_start_xmit,
1635     .ndo_set_mac_address    = ftgmac100_set_mac_addr,
1636     .ndo_validate_addr  = eth_validate_addr,
1637     .ndo_eth_ioctl      = phy_do_ioctl,
1638     .ndo_tx_timeout     = ftgmac100_tx_timeout,
1639     .ndo_set_rx_mode    = ftgmac100_set_rx_mode,
1640     .ndo_set_features   = ftgmac100_set_features,
1641 #ifdef CONFIG_NET_POLL_CONTROLLER
1642     .ndo_poll_controller    = ftgmac100_poll_controller,
1643 #endif
1644     .ndo_vlan_rx_add_vid    = ncsi_vlan_rx_add_vid,
1645     .ndo_vlan_rx_kill_vid   = ncsi_vlan_rx_kill_vid,
1646 };
1647 
1648 static int ftgmac100_setup_mdio(struct net_device *netdev)
1649 {
1650     struct ftgmac100 *priv = netdev_priv(netdev);
1651     struct platform_device *pdev = to_platform_device(priv->dev);
1652     struct device_node *np = pdev->dev.of_node;
1653     struct device_node *mdio_np;
1654     int i, err = 0;
1655     u32 reg;
1656 
1657     /* initialize mdio bus */
1658     priv->mii_bus = mdiobus_alloc();
1659     if (!priv->mii_bus)
1660         return -EIO;
1661 
1662     if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1663         of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1664         /* The AST2600 has a separate MDIO controller */
1665 
1666         /* For the AST2400 and AST2500 this driver only supports the
1667          * old MDIO interface
1668          */
1669         reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1670         reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1671         iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1672     }
1673 
1674     priv->mii_bus->name = "ftgmac100_mdio";
1675     snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1676          pdev->name, pdev->id);
1677     priv->mii_bus->parent = priv->dev;
1678     priv->mii_bus->priv = priv->netdev;
1679     priv->mii_bus->read = ftgmac100_mdiobus_read;
1680     priv->mii_bus->write = ftgmac100_mdiobus_write;
1681 
1682     for (i = 0; i < PHY_MAX_ADDR; i++)
1683         priv->mii_bus->irq[i] = PHY_POLL;
1684 
1685     mdio_np = of_get_child_by_name(np, "mdio");
1686 
1687     err = of_mdiobus_register(priv->mii_bus, mdio_np);
1688     if (err) {
1689         dev_err(priv->dev, "Cannot register MDIO bus!\n");
1690         goto err_register_mdiobus;
1691     }
1692 
1693     of_node_put(mdio_np);
1694 
1695     return 0;
1696 
1697 err_register_mdiobus:
1698     mdiobus_free(priv->mii_bus);
1699     return err;
1700 }
1701 
1702 static void ftgmac100_phy_disconnect(struct net_device *netdev)
1703 {
1704     if (!netdev->phydev)
1705         return;
1706 
1707     phy_disconnect(netdev->phydev);
1708 }
1709 
1710 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1711 {
1712     struct ftgmac100 *priv = netdev_priv(netdev);
1713 
1714     if (!priv->mii_bus)
1715         return;
1716 
1717     mdiobus_unregister(priv->mii_bus);
1718     mdiobus_free(priv->mii_bus);
1719 }
1720 
1721 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1722 {
1723     if (unlikely(nd->state != ncsi_dev_state_functional))
1724         return;
1725 
1726     netdev_dbg(nd->dev, "NCSI interface %s\n",
1727            nd->link_up ? "up" : "down");
1728 }
1729 
1730 static int ftgmac100_setup_clk(struct ftgmac100 *priv)
1731 {
1732     struct clk *clk;
1733     int rc;
1734 
1735     clk = devm_clk_get(priv->dev, NULL /* MACCLK */);
1736     if (IS_ERR(clk))
1737         return PTR_ERR(clk);
1738     priv->clk = clk;
1739     rc = clk_prepare_enable(priv->clk);
1740     if (rc)
1741         return rc;
1742 
1743     /* Aspeed specifies a 100MHz clock is required for up to
1744      * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1745      * is sufficient
1746      */
1747     rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1748               FTGMAC_100MHZ);
1749     if (rc)
1750         goto cleanup_clk;
1751 
1752     /* RCLK is for RMII, typically used for NCSI. Optional because it's not
1753      * necessary if it's the AST2400 MAC, or the MAC is configured for
1754      * RGMII, or the controller is not an ASPEED-based controller.
1755      */
1756     priv->rclk = devm_clk_get_optional(priv->dev, "RCLK");
1757     rc = clk_prepare_enable(priv->rclk);
1758     if (!rc)
1759         return 0;
1760 
1761 cleanup_clk:
1762     clk_disable_unprepare(priv->clk);
1763 
1764     return rc;
1765 }
1766 
1767 static bool ftgmac100_has_child_node(struct device_node *np, const char *name)
1768 {
1769     struct device_node *child_np = of_get_child_by_name(np, name);
1770     bool ret = false;
1771 
1772     if (child_np) {
1773         ret = true;
1774         of_node_put(child_np);
1775     }
1776 
1777     return ret;
1778 }
1779 
1780 static int ftgmac100_probe(struct platform_device *pdev)
1781 {
1782     struct resource *res;
1783     int irq;
1784     struct net_device *netdev;
1785     struct ftgmac100 *priv;
1786     struct device_node *np;
1787     int err = 0;
1788 
1789     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1790     if (!res)
1791         return -ENXIO;
1792 
1793     irq = platform_get_irq(pdev, 0);
1794     if (irq < 0)
1795         return irq;
1796 
1797     /* setup net_device */
1798     netdev = alloc_etherdev(sizeof(*priv));
1799     if (!netdev) {
1800         err = -ENOMEM;
1801         goto err_alloc_etherdev;
1802     }
1803 
1804     SET_NETDEV_DEV(netdev, &pdev->dev);
1805 
1806     netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1807     netdev->netdev_ops = &ftgmac100_netdev_ops;
1808     netdev->watchdog_timeo = 5 * HZ;
1809 
1810     platform_set_drvdata(pdev, netdev);
1811 
1812     /* setup private data */
1813     priv = netdev_priv(netdev);
1814     priv->netdev = netdev;
1815     priv->dev = &pdev->dev;
1816     INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1817 
1818     /* map io memory */
1819     priv->res = request_mem_region(res->start, resource_size(res),
1820                        dev_name(&pdev->dev));
1821     if (!priv->res) {
1822         dev_err(&pdev->dev, "Could not reserve memory region\n");
1823         err = -ENOMEM;
1824         goto err_req_mem;
1825     }
1826 
1827     priv->base = ioremap(res->start, resource_size(res));
1828     if (!priv->base) {
1829         dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1830         err = -EIO;
1831         goto err_ioremap;
1832     }
1833 
1834     netdev->irq = irq;
1835 
1836     /* Enable pause */
1837     priv->tx_pause = true;
1838     priv->rx_pause = true;
1839     priv->aneg_pause = true;
1840 
1841     /* MAC address from chip or random one */
1842     ftgmac100_initial_mac(priv);
1843 
1844     np = pdev->dev.of_node;
1845     if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1846            of_device_is_compatible(np, "aspeed,ast2500-mac") ||
1847            of_device_is_compatible(np, "aspeed,ast2600-mac"))) {
1848         priv->rxdes0_edorr_mask = BIT(30);
1849         priv->txdes0_edotr_mask = BIT(30);
1850         priv->is_aspeed = true;
1851     } else {
1852         priv->rxdes0_edorr_mask = BIT(15);
1853         priv->txdes0_edotr_mask = BIT(15);
1854     }
1855 
1856     if (np && of_get_property(np, "use-ncsi", NULL)) {
1857         if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1858             dev_err(&pdev->dev, "NCSI stack not enabled\n");
1859             err = -EINVAL;
1860             goto err_phy_connect;
1861         }
1862 
1863         dev_info(&pdev->dev, "Using NCSI interface\n");
1864         priv->use_ncsi = true;
1865         priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1866         if (!priv->ndev) {
1867             err = -EINVAL;
1868             goto err_phy_connect;
1869         }
1870     } else if (np && of_get_property(np, "phy-handle", NULL)) {
1871         struct phy_device *phy;
1872 
1873         /* Support "mdio"/"phy" child nodes for ast2400/2500 with
1874          * an embedded MDIO controller. Automatically scan the DTS for
1875          * available PHYs and register them.
1876          */
1877         if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1878             of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1879             err = ftgmac100_setup_mdio(netdev);
1880             if (err)
1881                 goto err_setup_mdio;
1882         }
1883 
1884         phy = of_phy_get_and_connect(priv->netdev, np,
1885                          &ftgmac100_adjust_link);
1886         if (!phy) {
1887             dev_err(&pdev->dev, "Failed to connect to phy\n");
1888             err = -EINVAL;
1889             goto err_phy_connect;
1890         }
1891 
1892         /* Indicate that we support PAUSE frames (see comment in
1893          * Documentation/networking/phy.rst)
1894          */
1895         phy_support_asym_pause(phy);
1896 
1897         /* Display what we found */
1898         phy_attached_info(phy);
1899     } else if (np && !ftgmac100_has_child_node(np, "mdio")) {
1900         /* Support legacy ASPEED devicetree descriptions that decribe a
1901          * MAC with an embedded MDIO controller but have no "mdio"
1902          * child node. Automatically scan the MDIO bus for available
1903          * PHYs.
1904          */
1905         priv->use_ncsi = false;
1906         err = ftgmac100_setup_mdio(netdev);
1907         if (err)
1908             goto err_setup_mdio;
1909 
1910         err = ftgmac100_mii_probe(netdev);
1911         if (err) {
1912             dev_err(priv->dev, "MII probe failed!\n");
1913             goto err_ncsi_dev;
1914         }
1915 
1916     }
1917 
1918     if (priv->is_aspeed) {
1919         err = ftgmac100_setup_clk(priv);
1920         if (err)
1921             goto err_phy_connect;
1922 
1923         /* Disable ast2600 problematic HW arbitration */
1924         if (of_device_is_compatible(np, "aspeed,ast2600-mac"))
1925             iowrite32(FTGMAC100_TM_DEFAULT,
1926                   priv->base + FTGMAC100_OFFSET_TM);
1927     }
1928 
1929     /* Default ring sizes */
1930     priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1931     priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1932 
1933     /* Base feature set */
1934     netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1935         NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1936         NETIF_F_HW_VLAN_CTAG_TX;
1937 
1938     if (priv->use_ncsi)
1939         netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1940 
1941     /* AST2400  doesn't have working HW checksum generation */
1942     if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1943         netdev->hw_features &= ~NETIF_F_HW_CSUM;
1944 
1945     /* AST2600 tx checksum with NCSI is broken */
1946     if (priv->use_ncsi && of_device_is_compatible(np, "aspeed,ast2600-mac"))
1947         netdev->hw_features &= ~NETIF_F_HW_CSUM;
1948 
1949     if (np && of_get_property(np, "no-hw-checksum", NULL))
1950         netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1951     netdev->features |= netdev->hw_features;
1952 
1953     /* register network device */
1954     err = register_netdev(netdev);
1955     if (err) {
1956         dev_err(&pdev->dev, "Failed to register netdev\n");
1957         goto err_register_netdev;
1958     }
1959 
1960     netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1961 
1962     return 0;
1963 
1964 err_register_netdev:
1965     clk_disable_unprepare(priv->rclk);
1966     clk_disable_unprepare(priv->clk);
1967 err_phy_connect:
1968     ftgmac100_phy_disconnect(netdev);
1969 err_ncsi_dev:
1970     if (priv->ndev)
1971         ncsi_unregister_dev(priv->ndev);
1972     ftgmac100_destroy_mdio(netdev);
1973 err_setup_mdio:
1974     iounmap(priv->base);
1975 err_ioremap:
1976     release_resource(priv->res);
1977 err_req_mem:
1978     free_netdev(netdev);
1979 err_alloc_etherdev:
1980     return err;
1981 }
1982 
1983 static int ftgmac100_remove(struct platform_device *pdev)
1984 {
1985     struct net_device *netdev;
1986     struct ftgmac100 *priv;
1987 
1988     netdev = platform_get_drvdata(pdev);
1989     priv = netdev_priv(netdev);
1990 
1991     if (priv->ndev)
1992         ncsi_unregister_dev(priv->ndev);
1993     unregister_netdev(netdev);
1994 
1995     clk_disable_unprepare(priv->rclk);
1996     clk_disable_unprepare(priv->clk);
1997 
1998     /* There's a small chance the reset task will have been re-queued,
1999      * during stop, make sure it's gone before we free the structure.
2000      */
2001     cancel_work_sync(&priv->reset_task);
2002 
2003     ftgmac100_phy_disconnect(netdev);
2004     ftgmac100_destroy_mdio(netdev);
2005 
2006     iounmap(priv->base);
2007     release_resource(priv->res);
2008 
2009     netif_napi_del(&priv->napi);
2010     free_netdev(netdev);
2011     return 0;
2012 }
2013 
2014 static const struct of_device_id ftgmac100_of_match[] = {
2015     { .compatible = "faraday,ftgmac100" },
2016     { }
2017 };
2018 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
2019 
2020 static struct platform_driver ftgmac100_driver = {
2021     .probe  = ftgmac100_probe,
2022     .remove = ftgmac100_remove,
2023     .driver = {
2024         .name       = DRV_NAME,
2025         .of_match_table = ftgmac100_of_match,
2026     },
2027 };
2028 module_platform_driver(ftgmac100_driver);
2029 
2030 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
2031 MODULE_DESCRIPTION("FTGMAC100 driver");
2032 MODULE_LICENSE("GPL");
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