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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright(c) 2015 EZchip Technologies.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/etherdevice.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_irq.h>
0011 #include <linux/of_net.h>
0012 #include <linux/of_platform.h>
0013 #include "nps_enet.h"
0014 
0015 #define DRV_NAME            "nps_mgt_enet"
0016 
0017 static inline bool nps_enet_is_tx_pending(struct nps_enet_priv *priv)
0018 {
0019     u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
0020     u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
0021 
0022     return (!tx_ctrl_ct && priv->tx_skb);
0023 }
0024 
0025 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len)
0026 {
0027     struct nps_enet_priv *priv = netdev_priv(ndev);
0028     u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32));
0029 
0030     /* Empty Rx FIFO buffer by reading all words */
0031     for (i = 0; i < len; i++)
0032         nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
0033 }
0034 
0035 static void nps_enet_read_rx_fifo(struct net_device *ndev,
0036                   unsigned char *dst, u32 length)
0037 {
0038     struct nps_enet_priv *priv = netdev_priv(ndev);
0039     s32 i, last = length & (sizeof(u32) - 1);
0040     u32 *reg = (u32 *)dst, len = length / sizeof(u32);
0041     bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32));
0042 
0043     /* In case dst is not aligned we need an intermediate buffer */
0044     if (dst_is_aligned) {
0045         ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
0046         reg += len;
0047     } else { /* !dst_is_aligned */
0048         for (i = 0; i < len; i++, reg++) {
0049             u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
0050 
0051             put_unaligned_be32(buf, reg);
0052         }
0053     }
0054     /* copy last bytes (if any) */
0055     if (last) {
0056         u32 buf;
0057 
0058         ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
0059         memcpy((u8 *)reg, &buf, last);
0060     }
0061 }
0062 
0063 static u32 nps_enet_rx_handler(struct net_device *ndev)
0064 {
0065     u32 frame_len, err = 0;
0066     u32 work_done = 0;
0067     struct nps_enet_priv *priv = netdev_priv(ndev);
0068     struct sk_buff *skb;
0069     u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
0070     u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
0071     u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT;
0072     u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT;
0073 
0074     frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT;
0075 
0076     /* Check if we got RX */
0077     if (!rx_ctrl_cr)
0078         return work_done;
0079 
0080     /* If we got here there is a work for us */
0081     work_done++;
0082 
0083     /* Check Rx error */
0084     if (rx_ctrl_er) {
0085         ndev->stats.rx_errors++;
0086         err = 1;
0087     }
0088 
0089     /* Check Rx CRC error */
0090     if (rx_ctrl_crc) {
0091         ndev->stats.rx_crc_errors++;
0092         ndev->stats.rx_dropped++;
0093         err = 1;
0094     }
0095 
0096     /* Check Frame length Min 64b */
0097     if (unlikely(frame_len < ETH_ZLEN)) {
0098         ndev->stats.rx_length_errors++;
0099         ndev->stats.rx_dropped++;
0100         err = 1;
0101     }
0102 
0103     if (err)
0104         goto rx_irq_clean;
0105 
0106     /* Skb allocation */
0107     skb = netdev_alloc_skb_ip_align(ndev, frame_len);
0108     if (unlikely(!skb)) {
0109         ndev->stats.rx_errors++;
0110         ndev->stats.rx_dropped++;
0111         goto rx_irq_clean;
0112     }
0113 
0114     /* Copy frame from Rx fifo into the skb */
0115     nps_enet_read_rx_fifo(ndev, skb->data, frame_len);
0116 
0117     skb_put(skb, frame_len);
0118     skb->protocol = eth_type_trans(skb, ndev);
0119     skb->ip_summed = CHECKSUM_UNNECESSARY;
0120 
0121     ndev->stats.rx_packets++;
0122     ndev->stats.rx_bytes += frame_len;
0123     netif_receive_skb(skb);
0124 
0125     goto rx_irq_frame_done;
0126 
0127 rx_irq_clean:
0128     /* Clean Rx fifo */
0129     nps_enet_clean_rx_fifo(ndev, frame_len);
0130 
0131 rx_irq_frame_done:
0132     /* Ack Rx ctrl register */
0133     nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0);
0134 
0135     return work_done;
0136 }
0137 
0138 static void nps_enet_tx_handler(struct net_device *ndev)
0139 {
0140     struct nps_enet_priv *priv = netdev_priv(ndev);
0141     u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
0142     u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT;
0143     u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
0144 
0145     /* Check if we got TX */
0146     if (!nps_enet_is_tx_pending(priv))
0147         return;
0148 
0149     /* Ack Tx ctrl register */
0150     nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0);
0151 
0152     /* Check Tx transmit error */
0153     if (unlikely(tx_ctrl_et)) {
0154         ndev->stats.tx_errors++;
0155     } else {
0156         ndev->stats.tx_packets++;
0157         ndev->stats.tx_bytes += tx_ctrl_nt;
0158     }
0159 
0160     dev_kfree_skb(priv->tx_skb);
0161     priv->tx_skb = NULL;
0162 
0163     if (netif_queue_stopped(ndev))
0164         netif_wake_queue(ndev);
0165 }
0166 
0167 /**
0168  * nps_enet_poll - NAPI poll handler.
0169  * @napi:       Pointer to napi_struct structure.
0170  * @budget:     How many frames to process on one call.
0171  *
0172  * returns:     Number of processed frames
0173  */
0174 static int nps_enet_poll(struct napi_struct *napi, int budget)
0175 {
0176     struct net_device *ndev = napi->dev;
0177     struct nps_enet_priv *priv = netdev_priv(ndev);
0178     u32 work_done;
0179 
0180     nps_enet_tx_handler(ndev);
0181     work_done = nps_enet_rx_handler(ndev);
0182     if ((work_done < budget) && napi_complete_done(napi, work_done)) {
0183         u32 buf_int_enable_value = 0;
0184 
0185         /* set tx_done and rx_rdy bits */
0186         buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
0187         buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
0188 
0189         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
0190                  buf_int_enable_value);
0191 
0192         /* in case we will get a tx interrupt while interrupts
0193          * are masked, we will lose it since the tx is edge interrupt.
0194          * specifically, while executing the code section above,
0195          * between nps_enet_tx_handler and the interrupts enable, all
0196          * tx requests will be stuck until we will get an rx interrupt.
0197          * the two code lines below will solve this situation by
0198          * re-adding ourselves to the poll list.
0199          */
0200         if (nps_enet_is_tx_pending(priv)) {
0201             nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
0202             napi_reschedule(napi);
0203         }
0204     }
0205 
0206     return work_done;
0207 }
0208 
0209 /**
0210  * nps_enet_irq_handler - Global interrupt handler for ENET.
0211  * @irq:                irq number.
0212  * @dev_instance:       device instance.
0213  *
0214  * returns: IRQ_HANDLED for all cases.
0215  *
0216  * EZchip ENET has 2 interrupt causes, and depending on bits raised in
0217  * CTRL registers we may tell what is a reason for interrupt to fire up.
0218  * We got one for RX and the other for TX (completion).
0219  */
0220 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
0221 {
0222     struct net_device *ndev = dev_instance;
0223     struct nps_enet_priv *priv = netdev_priv(ndev);
0224     u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
0225     u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
0226 
0227     if (nps_enet_is_tx_pending(priv) || rx_ctrl_cr)
0228         if (likely(napi_schedule_prep(&priv->napi))) {
0229             nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
0230             __napi_schedule(&priv->napi);
0231         }
0232 
0233     return IRQ_HANDLED;
0234 }
0235 
0236 static void nps_enet_set_hw_mac_address(struct net_device *ndev)
0237 {
0238     struct nps_enet_priv *priv = netdev_priv(ndev);
0239     u32 ge_mac_cfg_1_value = 0;
0240     u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
0241 
0242     /* set MAC address in HW */
0243     ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT;
0244     ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT;
0245     ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT;
0246     ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT;
0247     *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK)
0248          | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT;
0249     *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK)
0250          | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT;
0251 
0252     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1,
0253              ge_mac_cfg_1_value);
0254 
0255     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
0256              *ge_mac_cfg_2_value);
0257 }
0258 
0259 /**
0260  * nps_enet_hw_reset - Reset the network device.
0261  * @ndev:       Pointer to the network device.
0262  *
0263  * This function reset the PCS and TX fifo.
0264  * The programming model is to set the relevant reset bits
0265  * wait for some time for this to propagate and then unset
0266  * the reset bits. This way we ensure that reset procedure
0267  * is done successfully by device.
0268  */
0269 static void nps_enet_hw_reset(struct net_device *ndev)
0270 {
0271     struct nps_enet_priv *priv = netdev_priv(ndev);
0272     u32 ge_rst_value = 0, phase_fifo_ctl_value = 0;
0273 
0274     /* Pcs reset sequence*/
0275     ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;
0276     nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
0277     usleep_range(10, 20);
0278     ge_rst_value = 0;
0279     nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
0280 
0281     /* Tx fifo reset sequence */
0282     phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;
0283     phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;
0284     nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
0285              phase_fifo_ctl_value);
0286     usleep_range(10, 20);
0287     phase_fifo_ctl_value = 0;
0288     nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
0289              phase_fifo_ctl_value);
0290 }
0291 
0292 static void nps_enet_hw_enable_control(struct net_device *ndev)
0293 {
0294     struct nps_enet_priv *priv = netdev_priv(ndev);
0295     u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0;
0296     u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
0297     u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value;
0298     s32 max_frame_length;
0299 
0300     /* Enable Rx and Tx statistics */
0301     *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK)
0302          | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT;
0303 
0304     /* Discard packets with different MAC address */
0305     *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
0306          | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
0307 
0308     /* Discard multicast packets */
0309     *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
0310          | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
0311 
0312     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
0313              *ge_mac_cfg_2_value);
0314 
0315     /* Discard Packets bigger than max frame length */
0316     max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN;
0317     if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) {
0318         *ge_mac_cfg_3_value =
0319              (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK)
0320              | max_frame_length << CFG_3_MAX_LEN_SHIFT;
0321     }
0322 
0323     /* Enable interrupts */
0324     buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
0325     buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
0326     nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
0327              buf_int_enable_value);
0328 
0329     /* Write device MAC address to HW */
0330     nps_enet_set_hw_mac_address(ndev);
0331 
0332     /* Rx and Tx HW features */
0333     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;
0334     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;
0335     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;
0336 
0337     /* IFG configuration */
0338     ge_mac_cfg_0_value |=
0339          NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT;
0340     ge_mac_cfg_0_value |=
0341          NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT;
0342 
0343     /* preamble configuration */
0344     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;
0345     ge_mac_cfg_0_value |=
0346          NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT;
0347 
0348     /* enable flow control frames */
0349     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;
0350     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;
0351     ge_mac_cfg_0_value |=
0352          NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT;
0353     *ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK)
0354          | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;
0355 
0356     /* Enable Rx and Tx */
0357     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;
0358     ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;
0359 
0360     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3,
0361              *ge_mac_cfg_3_value);
0362     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0,
0363              ge_mac_cfg_0_value);
0364 }
0365 
0366 static void nps_enet_hw_disable_control(struct net_device *ndev)
0367 {
0368     struct nps_enet_priv *priv = netdev_priv(ndev);
0369 
0370     /* Disable interrupts */
0371     nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
0372 
0373     /* Disable Rx and Tx */
0374     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0);
0375 }
0376 
0377 static void nps_enet_send_frame(struct net_device *ndev,
0378                 struct sk_buff *skb)
0379 {
0380     struct nps_enet_priv *priv = netdev_priv(ndev);
0381     u32 tx_ctrl_value = 0;
0382     short length = skb->len;
0383     u32 i, len = DIV_ROUND_UP(length, sizeof(u32));
0384     u32 *src = (void *)skb->data;
0385     bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32));
0386 
0387     /* In case src is not aligned we need an intermediate buffer */
0388     if (src_is_aligned)
0389         iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
0390     else /* !src_is_aligned */
0391         for (i = 0; i < len; i++, src++)
0392             nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF,
0393                      get_unaligned_be32(src));
0394 
0395     /* Write the length of the Frame */
0396     tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
0397 
0398     tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
0399     /* Send Frame */
0400     nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
0401 }
0402 
0403 /**
0404  * nps_enet_set_mac_address - Set the MAC address for this device.
0405  * @ndev:       Pointer to net_device structure.
0406  * @p:          6 byte Address to be written as MAC address.
0407  *
0408  * This function copies the HW address from the sockaddr structure to the
0409  * net_device structure and updates the address in HW.
0410  *
0411  * returns:     -EBUSY if the net device is busy or 0 if the address is set
0412  *              successfully.
0413  */
0414 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p)
0415 {
0416     struct sockaddr *addr = p;
0417     s32 res;
0418 
0419     if (netif_running(ndev))
0420         return -EBUSY;
0421 
0422     res = eth_mac_addr(ndev, p);
0423     if (!res) {
0424         eth_hw_addr_set(ndev, addr->sa_data);
0425         nps_enet_set_hw_mac_address(ndev);
0426     }
0427 
0428     return res;
0429 }
0430 
0431 /**
0432  * nps_enet_set_rx_mode - Change the receive filtering mode.
0433  * @ndev:       Pointer to the network device.
0434  *
0435  * This function enables/disables promiscuous mode
0436  */
0437 static void nps_enet_set_rx_mode(struct net_device *ndev)
0438 {
0439     struct nps_enet_priv *priv = netdev_priv(ndev);
0440     u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value;
0441 
0442     if (ndev->flags & IFF_PROMISC) {
0443         ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
0444              | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT;
0445         ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
0446              | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT;
0447 
0448     } else {
0449         ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
0450              | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
0451         ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
0452              | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
0453     }
0454 
0455     nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value);
0456 }
0457 
0458 /**
0459  * nps_enet_open - Open the network device.
0460  * @ndev:       Pointer to the network device.
0461  *
0462  * returns: 0, on success or non-zero error value on failure.
0463  *
0464  * This function sets the MAC address, requests and enables an IRQ
0465  * for the ENET device and starts the Tx queue.
0466  */
0467 static s32 nps_enet_open(struct net_device *ndev)
0468 {
0469     struct nps_enet_priv *priv = netdev_priv(ndev);
0470     s32 err;
0471 
0472     /* Reset private variables */
0473     priv->tx_skb = NULL;
0474     priv->ge_mac_cfg_2_value = 0;
0475     priv->ge_mac_cfg_3_value = 0;
0476 
0477     /* ge_mac_cfg_3 default values */
0478     priv->ge_mac_cfg_3_value |=
0479          NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT;
0480 
0481     priv->ge_mac_cfg_3_value |=
0482          NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT;
0483 
0484     /* Disable HW device */
0485     nps_enet_hw_disable_control(ndev);
0486 
0487     /* irq Rx allocation */
0488     err = request_irq(priv->irq, nps_enet_irq_handler,
0489               0, "enet-rx-tx", ndev);
0490     if (err)
0491         return err;
0492 
0493     napi_enable(&priv->napi);
0494 
0495     /* Enable HW device */
0496     nps_enet_hw_reset(ndev);
0497     nps_enet_hw_enable_control(ndev);
0498 
0499     netif_start_queue(ndev);
0500 
0501     return 0;
0502 }
0503 
0504 /**
0505  * nps_enet_stop - Close the network device.
0506  * @ndev:       Pointer to the network device.
0507  *
0508  * This function stops the Tx queue, disables interrupts for the ENET device.
0509  */
0510 static s32 nps_enet_stop(struct net_device *ndev)
0511 {
0512     struct nps_enet_priv *priv = netdev_priv(ndev);
0513 
0514     napi_disable(&priv->napi);
0515     netif_stop_queue(ndev);
0516     nps_enet_hw_disable_control(ndev);
0517     free_irq(priv->irq, ndev);
0518 
0519     return 0;
0520 }
0521 
0522 /**
0523  * nps_enet_start_xmit - Starts the data transmission.
0524  * @skb:        sk_buff pointer that contains data to be Transmitted.
0525  * @ndev:       Pointer to net_device structure.
0526  *
0527  * returns: NETDEV_TX_OK, on success
0528  *              NETDEV_TX_BUSY, if any of the descriptors are not free.
0529  *
0530  * This function is invoked from upper layers to initiate transmission.
0531  */
0532 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
0533                        struct net_device *ndev)
0534 {
0535     struct nps_enet_priv *priv = netdev_priv(ndev);
0536 
0537     /* This driver handles one frame at a time  */
0538     netif_stop_queue(ndev);
0539 
0540     priv->tx_skb = skb;
0541 
0542     /* make sure tx_skb is actually written to the memory
0543      * before the HW is informed and the IRQ is fired.
0544      */
0545     wmb();
0546 
0547     nps_enet_send_frame(ndev, skb);
0548 
0549     return NETDEV_TX_OK;
0550 }
0551 
0552 #ifdef CONFIG_NET_POLL_CONTROLLER
0553 static void nps_enet_poll_controller(struct net_device *ndev)
0554 {
0555     disable_irq(ndev->irq);
0556     nps_enet_irq_handler(ndev->irq, ndev);
0557     enable_irq(ndev->irq);
0558 }
0559 #endif
0560 
0561 static const struct net_device_ops nps_netdev_ops = {
0562     .ndo_open       = nps_enet_open,
0563     .ndo_stop       = nps_enet_stop,
0564     .ndo_start_xmit     = nps_enet_start_xmit,
0565     .ndo_set_mac_address    = nps_enet_set_mac_address,
0566     .ndo_set_rx_mode        = nps_enet_set_rx_mode,
0567 #ifdef CONFIG_NET_POLL_CONTROLLER
0568     .ndo_poll_controller    = nps_enet_poll_controller,
0569 #endif
0570 };
0571 
0572 static s32 nps_enet_probe(struct platform_device *pdev)
0573 {
0574     struct device *dev = &pdev->dev;
0575     struct net_device *ndev;
0576     struct nps_enet_priv *priv;
0577     s32 err = 0;
0578 
0579     if (!dev->of_node)
0580         return -ENODEV;
0581 
0582     ndev = alloc_etherdev(sizeof(struct nps_enet_priv));
0583     if (!ndev)
0584         return -ENOMEM;
0585 
0586     platform_set_drvdata(pdev, ndev);
0587     SET_NETDEV_DEV(ndev, dev);
0588     priv = netdev_priv(ndev);
0589 
0590     /* The EZ NET specific entries in the device structure. */
0591     ndev->netdev_ops = &nps_netdev_ops;
0592     ndev->watchdog_timeo = (400 * HZ / 1000);
0593     /* FIXME :: no multicast support yet */
0594     ndev->flags &= ~IFF_MULTICAST;
0595 
0596     priv->regs_base = devm_platform_ioremap_resource(pdev, 0);
0597     if (IS_ERR(priv->regs_base)) {
0598         err = PTR_ERR(priv->regs_base);
0599         goto out_netdev;
0600     }
0601     dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
0602 
0603     /* set kernel MAC address to dev */
0604     err = of_get_ethdev_address(dev->of_node, ndev);
0605     if (err)
0606         eth_hw_addr_random(ndev);
0607 
0608     /* Get IRQ number */
0609     priv->irq = platform_get_irq(pdev, 0);
0610     if (priv->irq < 0) {
0611         err = -ENODEV;
0612         goto out_netdev;
0613     }
0614 
0615     netif_napi_add_weight(ndev, &priv->napi, nps_enet_poll,
0616                   NPS_ENET_NAPI_POLL_WEIGHT);
0617 
0618     /* Register the driver. Should be the last thing in probe */
0619     err = register_netdev(ndev);
0620     if (err) {
0621         dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n",
0622             ndev->name, (s32)err);
0623         goto out_netif_api;
0624     }
0625 
0626     dev_info(dev, "(rx/tx=%d)\n", priv->irq);
0627     return 0;
0628 
0629 out_netif_api:
0630     netif_napi_del(&priv->napi);
0631 out_netdev:
0632     free_netdev(ndev);
0633 
0634     return err;
0635 }
0636 
0637 static s32 nps_enet_remove(struct platform_device *pdev)
0638 {
0639     struct net_device *ndev = platform_get_drvdata(pdev);
0640     struct nps_enet_priv *priv = netdev_priv(ndev);
0641 
0642     unregister_netdev(ndev);
0643     netif_napi_del(&priv->napi);
0644     free_netdev(ndev);
0645 
0646     return 0;
0647 }
0648 
0649 static const struct of_device_id nps_enet_dt_ids[] = {
0650     { .compatible = "ezchip,nps-mgt-enet" },
0651     { /* Sentinel */ }
0652 };
0653 MODULE_DEVICE_TABLE(of, nps_enet_dt_ids);
0654 
0655 static struct platform_driver nps_enet_driver = {
0656     .probe = nps_enet_probe,
0657     .remove = nps_enet_remove,
0658     .driver = {
0659         .name = DRV_NAME,
0660         .of_match_table  = nps_enet_dt_ids,
0661     },
0662 };
0663 
0664 module_platform_driver(nps_enet_driver);
0665 
0666 MODULE_AUTHOR("EZchip Semiconductor");
0667 MODULE_LICENSE("GPL v2");
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