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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Dave DNET Ethernet Controller driver
0004  *
0005  * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
0006  * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
0007  */
0008 #include <linux/io.h>
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/kernel.h>
0012 #include <linux/types.h>
0013 #include <linux/slab.h>
0014 #include <linux/delay.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/netdevice.h>
0017 #include <linux/etherdevice.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/phy.h>
0021 
0022 #include "dnet.h"
0023 
0024 #undef DEBUG
0025 
0026 /* function for reading internal MAC register */
0027 static u16 dnet_readw_mac(struct dnet *bp, u16 reg)
0028 {
0029     u16 data_read;
0030 
0031     /* issue a read */
0032     dnet_writel(bp, reg, MACREG_ADDR);
0033 
0034     /* since a read/write op to the MAC is very slow,
0035      * we must wait before reading the data */
0036     ndelay(500);
0037 
0038     /* read data read from the MAC register */
0039     data_read = dnet_readl(bp, MACREG_DATA);
0040 
0041     /* all done */
0042     return data_read;
0043 }
0044 
0045 /* function for writing internal MAC register */
0046 static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
0047 {
0048     /* load data to write */
0049     dnet_writel(bp, val, MACREG_DATA);
0050 
0051     /* issue a write */
0052     dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
0053 
0054     /* since a read/write op to the MAC is very slow,
0055      * we must wait before exiting */
0056     ndelay(500);
0057 }
0058 
0059 static void __dnet_set_hwaddr(struct dnet *bp)
0060 {
0061     u16 tmp;
0062 
0063     tmp = be16_to_cpup((const __be16 *)bp->dev->dev_addr);
0064     dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
0065     tmp = be16_to_cpup((const __be16 *)(bp->dev->dev_addr + 2));
0066     dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
0067     tmp = be16_to_cpup((const __be16 *)(bp->dev->dev_addr + 4));
0068     dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
0069 }
0070 
0071 static void dnet_get_hwaddr(struct dnet *bp)
0072 {
0073     u16 tmp;
0074     u8 addr[6];
0075 
0076     /*
0077      * from MAC docs:
0078      * "Note that the MAC address is stored in the registers in Hexadecimal
0079      * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
0080      * would require writing 0xAC (octet 0) to address 0x0B (high byte of
0081      * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
0082      * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
0083      * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
0084      * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
0085      * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
0086      * Mac_addr[15:0]).
0087      */
0088     tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
0089     *((__be16 *)addr) = cpu_to_be16(tmp);
0090     tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
0091     *((__be16 *)(addr + 2)) = cpu_to_be16(tmp);
0092     tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
0093     *((__be16 *)(addr + 4)) = cpu_to_be16(tmp);
0094 
0095     if (is_valid_ether_addr(addr))
0096         eth_hw_addr_set(bp->dev, addr);
0097 }
0098 
0099 static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
0100 {
0101     struct dnet *bp = bus->priv;
0102     u16 value;
0103 
0104     while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
0105                 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
0106         cpu_relax();
0107 
0108     /* only 5 bits allowed for phy-addr and reg_offset */
0109     mii_id &= 0x1f;
0110     regnum &= 0x1f;
0111 
0112     /* prepare reg_value for a read */
0113     value = (mii_id << 8);
0114     value |= regnum;
0115 
0116     /* write control word */
0117     dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
0118 
0119     /* wait for end of transfer */
0120     while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
0121                 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
0122         cpu_relax();
0123 
0124     value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
0125 
0126     pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
0127 
0128     return value;
0129 }
0130 
0131 static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
0132                u16 value)
0133 {
0134     struct dnet *bp = bus->priv;
0135     u16 tmp;
0136 
0137     pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
0138 
0139     while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
0140                 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
0141         cpu_relax();
0142 
0143     /* prepare for a write operation */
0144     tmp = (1 << 13);
0145 
0146     /* only 5 bits allowed for phy-addr and reg_offset */
0147     mii_id &= 0x1f;
0148     regnum &= 0x1f;
0149 
0150     /* only 16 bits on data */
0151     value &= 0xffff;
0152 
0153     /* prepare reg_value for a write */
0154     tmp |= (mii_id << 8);
0155     tmp |= regnum;
0156 
0157     /* write data to write first */
0158     dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
0159 
0160     /* write control word */
0161     dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
0162 
0163     while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
0164                 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
0165         cpu_relax();
0166 
0167     return 0;
0168 }
0169 
0170 static void dnet_handle_link_change(struct net_device *dev)
0171 {
0172     struct dnet *bp = netdev_priv(dev);
0173     struct phy_device *phydev = dev->phydev;
0174     unsigned long flags;
0175     u32 mode_reg, ctl_reg;
0176 
0177     int status_change = 0;
0178 
0179     spin_lock_irqsave(&bp->lock, flags);
0180 
0181     mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
0182     ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
0183 
0184     if (phydev->link) {
0185         if (bp->duplex != phydev->duplex) {
0186             if (phydev->duplex)
0187                 ctl_reg &=
0188                     ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
0189             else
0190                 ctl_reg |=
0191                     DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
0192 
0193             bp->duplex = phydev->duplex;
0194             status_change = 1;
0195         }
0196 
0197         if (bp->speed != phydev->speed) {
0198             status_change = 1;
0199             switch (phydev->speed) {
0200             case 1000:
0201                 mode_reg |= DNET_INTERNAL_MODE_GBITEN;
0202                 break;
0203             case 100:
0204             case 10:
0205                 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
0206                 break;
0207             default:
0208                 printk(KERN_WARNING
0209                        "%s: Ack!  Speed (%d) is not "
0210                        "10/100/1000!\n", dev->name,
0211                        phydev->speed);
0212                 break;
0213             }
0214             bp->speed = phydev->speed;
0215         }
0216     }
0217 
0218     if (phydev->link != bp->link) {
0219         if (phydev->link) {
0220             mode_reg |=
0221                 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
0222         } else {
0223             mode_reg &=
0224                 ~(DNET_INTERNAL_MODE_RXEN |
0225                   DNET_INTERNAL_MODE_TXEN);
0226             bp->speed = 0;
0227             bp->duplex = -1;
0228         }
0229         bp->link = phydev->link;
0230 
0231         status_change = 1;
0232     }
0233 
0234     if (status_change) {
0235         dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
0236         dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
0237     }
0238 
0239     spin_unlock_irqrestore(&bp->lock, flags);
0240 
0241     if (status_change) {
0242         if (phydev->link)
0243             printk(KERN_INFO "%s: link up (%d/%s)\n",
0244                    dev->name, phydev->speed,
0245                    DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
0246         else
0247             printk(KERN_INFO "%s: link down\n", dev->name);
0248     }
0249 }
0250 
0251 static int dnet_mii_probe(struct net_device *dev)
0252 {
0253     struct dnet *bp = netdev_priv(dev);
0254     struct phy_device *phydev = NULL;
0255 
0256     /* find the first phy */
0257     phydev = phy_find_first(bp->mii_bus);
0258 
0259     if (!phydev) {
0260         printk(KERN_ERR "%s: no PHY found\n", dev->name);
0261         return -ENODEV;
0262     }
0263 
0264     /* TODO : add pin_irq */
0265 
0266     /* attach the mac to the phy */
0267     if (bp->capabilities & DNET_HAS_RMII) {
0268         phydev = phy_connect(dev, phydev_name(phydev),
0269                      &dnet_handle_link_change,
0270                      PHY_INTERFACE_MODE_RMII);
0271     } else {
0272         phydev = phy_connect(dev, phydev_name(phydev),
0273                      &dnet_handle_link_change,
0274                      PHY_INTERFACE_MODE_MII);
0275     }
0276 
0277     if (IS_ERR(phydev)) {
0278         printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
0279         return PTR_ERR(phydev);
0280     }
0281 
0282     /* mask with MAC supported features */
0283     if (bp->capabilities & DNET_HAS_GIGABIT)
0284         phy_set_max_speed(phydev, SPEED_1000);
0285     else
0286         phy_set_max_speed(phydev, SPEED_100);
0287 
0288     phy_support_asym_pause(phydev);
0289 
0290     bp->link = 0;
0291     bp->speed = 0;
0292     bp->duplex = -1;
0293 
0294     return 0;
0295 }
0296 
0297 static int dnet_mii_init(struct dnet *bp)
0298 {
0299     int err;
0300 
0301     bp->mii_bus = mdiobus_alloc();
0302     if (bp->mii_bus == NULL)
0303         return -ENOMEM;
0304 
0305     bp->mii_bus->name = "dnet_mii_bus";
0306     bp->mii_bus->read = &dnet_mdio_read;
0307     bp->mii_bus->write = &dnet_mdio_write;
0308 
0309     snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
0310         bp->pdev->name, bp->pdev->id);
0311 
0312     bp->mii_bus->priv = bp;
0313 
0314     if (mdiobus_register(bp->mii_bus)) {
0315         err = -ENXIO;
0316         goto err_out;
0317     }
0318 
0319     if (dnet_mii_probe(bp->dev) != 0) {
0320         err = -ENXIO;
0321         goto err_out_unregister_bus;
0322     }
0323 
0324     return 0;
0325 
0326 err_out_unregister_bus:
0327     mdiobus_unregister(bp->mii_bus);
0328 err_out:
0329     mdiobus_free(bp->mii_bus);
0330     return err;
0331 }
0332 
0333 /* For Neptune board: LINK1000 as Link LED and TX as activity LED */
0334 static int dnet_phy_marvell_fixup(struct phy_device *phydev)
0335 {
0336     return phy_write(phydev, 0x18, 0x4148);
0337 }
0338 
0339 static void dnet_update_stats(struct dnet *bp)
0340 {
0341     u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
0342     u32 *p = &bp->hw_stats.rx_pkt_ignr;
0343     u32 *end = &bp->hw_stats.rx_byte + 1;
0344 
0345     WARN_ON((unsigned long)(end - p - 1) !=
0346         (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
0347 
0348     for (; p < end; p++, reg++)
0349         *p += readl(reg);
0350 
0351     reg = bp->regs + DNET_TX_UNICAST_CNT;
0352     p = &bp->hw_stats.tx_unicast;
0353     end = &bp->hw_stats.tx_byte + 1;
0354 
0355     WARN_ON((unsigned long)(end - p - 1) !=
0356         (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
0357 
0358     for (; p < end; p++, reg++)
0359         *p += readl(reg);
0360 }
0361 
0362 static int dnet_poll(struct napi_struct *napi, int budget)
0363 {
0364     struct dnet *bp = container_of(napi, struct dnet, napi);
0365     struct net_device *dev = bp->dev;
0366     int npackets = 0;
0367     unsigned int pkt_len;
0368     struct sk_buff *skb;
0369     unsigned int *data_ptr;
0370     u32 int_enable;
0371     u32 cmd_word;
0372     int i;
0373 
0374     while (npackets < budget) {
0375         /*
0376          * break out of while loop if there are no more
0377          * packets waiting
0378          */
0379         if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16))
0380             break;
0381 
0382         cmd_word = dnet_readl(bp, RX_LEN_FIFO);
0383         pkt_len = cmd_word & 0xFFFF;
0384 
0385         if (cmd_word & 0xDF180000)
0386             printk(KERN_ERR "%s packet receive error %x\n",
0387                    __func__, cmd_word);
0388 
0389         skb = netdev_alloc_skb(dev, pkt_len + 5);
0390         if (skb != NULL) {
0391             /* Align IP on 16 byte boundaries */
0392             skb_reserve(skb, 2);
0393             /*
0394              * 'skb_put()' points to the start of sk_buff
0395              * data area.
0396              */
0397             data_ptr = skb_put(skb, pkt_len);
0398             for (i = 0; i < (pkt_len + 3) >> 2; i++)
0399                 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
0400             skb->protocol = eth_type_trans(skb, dev);
0401             netif_receive_skb(skb);
0402             npackets++;
0403         } else
0404             printk(KERN_NOTICE
0405                    "%s: No memory to allocate a sk_buff of "
0406                    "size %u.\n", dev->name, pkt_len);
0407     }
0408 
0409     if (npackets < budget) {
0410         /* We processed all packets available.  Tell NAPI it can
0411          * stop polling then re-enable rx interrupts.
0412          */
0413         napi_complete_done(napi, npackets);
0414         int_enable = dnet_readl(bp, INTR_ENB);
0415         int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
0416         dnet_writel(bp, int_enable, INTR_ENB);
0417     }
0418 
0419     return npackets;
0420 }
0421 
0422 static irqreturn_t dnet_interrupt(int irq, void *dev_id)
0423 {
0424     struct net_device *dev = dev_id;
0425     struct dnet *bp = netdev_priv(dev);
0426     u32 int_src, int_enable, int_current;
0427     unsigned long flags;
0428     unsigned int handled = 0;
0429 
0430     spin_lock_irqsave(&bp->lock, flags);
0431 
0432     /* read and clear the DNET irq (clear on read) */
0433     int_src = dnet_readl(bp, INTR_SRC);
0434     int_enable = dnet_readl(bp, INTR_ENB);
0435     int_current = int_src & int_enable;
0436 
0437     /* restart the queue if we had stopped it for TX fifo almost full */
0438     if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
0439         int_enable = dnet_readl(bp, INTR_ENB);
0440         int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
0441         dnet_writel(bp, int_enable, INTR_ENB);
0442         netif_wake_queue(dev);
0443         handled = 1;
0444     }
0445 
0446     /* RX FIFO error checking */
0447     if (int_current &
0448         (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
0449         printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
0450                dnet_readl(bp, RX_STATUS), int_current);
0451         /* we can only flush the RX FIFOs */
0452         dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
0453         ndelay(500);
0454         dnet_writel(bp, 0, SYS_CTL);
0455         handled = 1;
0456     }
0457 
0458     /* TX FIFO error checking */
0459     if (int_current &
0460         (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
0461         printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
0462                dnet_readl(bp, TX_STATUS), int_current);
0463         /* we can only flush the TX FIFOs */
0464         dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
0465         ndelay(500);
0466         dnet_writel(bp, 0, SYS_CTL);
0467         handled = 1;
0468     }
0469 
0470     if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
0471         if (napi_schedule_prep(&bp->napi)) {
0472             /*
0473              * There's no point taking any more interrupts
0474              * until we have processed the buffers
0475              */
0476             /* Disable Rx interrupts and schedule NAPI poll */
0477             int_enable = dnet_readl(bp, INTR_ENB);
0478             int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
0479             dnet_writel(bp, int_enable, INTR_ENB);
0480             __napi_schedule(&bp->napi);
0481         }
0482         handled = 1;
0483     }
0484 
0485     if (!handled)
0486         pr_debug("%s: irq %x remains\n", __func__, int_current);
0487 
0488     spin_unlock_irqrestore(&bp->lock, flags);
0489 
0490     return IRQ_RETVAL(handled);
0491 }
0492 
0493 #ifdef DEBUG
0494 static inline void dnet_print_skb(struct sk_buff *skb)
0495 {
0496     int k;
0497     printk(KERN_DEBUG PFX "data:");
0498     for (k = 0; k < skb->len; k++)
0499         printk(" %02x", (unsigned int)skb->data[k]);
0500     printk("\n");
0501 }
0502 #else
0503 #define dnet_print_skb(skb) do {} while (0)
0504 #endif
0505 
0506 static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
0507 {
0508 
0509     struct dnet *bp = netdev_priv(dev);
0510     unsigned int i, tx_cmd, wrsz;
0511     unsigned long flags;
0512     unsigned int *bufp;
0513     u32 irq_enable;
0514 
0515     dnet_readl(bp, TX_STATUS);
0516 
0517     pr_debug("start_xmit: len %u head %p data %p\n",
0518            skb->len, skb->head, skb->data);
0519     dnet_print_skb(skb);
0520 
0521     spin_lock_irqsave(&bp->lock, flags);
0522 
0523     dnet_readl(bp, TX_STATUS);
0524 
0525     bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
0526     wrsz = (u32) skb->len + 3;
0527     wrsz += ((unsigned long) skb->data) & 0x3;
0528     wrsz >>= 2;
0529     tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
0530 
0531     /* check if there is enough room for the current frame */
0532     if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
0533         for (i = 0; i < wrsz; i++)
0534             dnet_writel(bp, *bufp++, TX_DATA_FIFO);
0535 
0536         /*
0537          * inform MAC that a packet's written and ready to be
0538          * shipped out
0539          */
0540         dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
0541     }
0542 
0543     if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
0544         netif_stop_queue(dev);
0545         dnet_readl(bp, INTR_SRC);
0546         irq_enable = dnet_readl(bp, INTR_ENB);
0547         irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
0548         dnet_writel(bp, irq_enable, INTR_ENB);
0549     }
0550 
0551     skb_tx_timestamp(skb);
0552 
0553     /* free the buffer */
0554     dev_kfree_skb(skb);
0555 
0556     spin_unlock_irqrestore(&bp->lock, flags);
0557 
0558     return NETDEV_TX_OK;
0559 }
0560 
0561 static void dnet_reset_hw(struct dnet *bp)
0562 {
0563     /* put ts_mac in IDLE state i.e. disable rx/tx */
0564     dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
0565 
0566     /*
0567      * RX FIFO almost full threshold: only cmd FIFO almost full is
0568      * implemented for RX side
0569      */
0570     dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
0571     /*
0572      * TX FIFO almost empty threshold: only data FIFO almost empty
0573      * is implemented for TX side
0574      */
0575     dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
0576 
0577     /* flush rx/tx fifos */
0578     dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
0579             SYS_CTL);
0580     msleep(1);
0581     dnet_writel(bp, 0, SYS_CTL);
0582 }
0583 
0584 static void dnet_init_hw(struct dnet *bp)
0585 {
0586     u32 config;
0587 
0588     dnet_reset_hw(bp);
0589     __dnet_set_hwaddr(bp);
0590 
0591     config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
0592 
0593     if (bp->dev->flags & IFF_PROMISC)
0594         /* Copy All Frames */
0595         config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
0596     if (!(bp->dev->flags & IFF_BROADCAST))
0597         /* No BroadCast */
0598         config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
0599 
0600     config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
0601         DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
0602         DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
0603         DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
0604 
0605     dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
0606 
0607     /* clear irq before enabling them */
0608     config = dnet_readl(bp, INTR_SRC);
0609 
0610     /* enable RX/TX interrupt, recv packet ready interrupt */
0611     dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
0612             DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
0613             DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
0614             DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
0615             DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
0616 }
0617 
0618 static int dnet_open(struct net_device *dev)
0619 {
0620     struct dnet *bp = netdev_priv(dev);
0621 
0622     /* if the phy is not yet register, retry later */
0623     if (!dev->phydev)
0624         return -EAGAIN;
0625 
0626     napi_enable(&bp->napi);
0627     dnet_init_hw(bp);
0628 
0629     phy_start_aneg(dev->phydev);
0630 
0631     /* schedule a link state check */
0632     phy_start(dev->phydev);
0633 
0634     netif_start_queue(dev);
0635 
0636     return 0;
0637 }
0638 
0639 static int dnet_close(struct net_device *dev)
0640 {
0641     struct dnet *bp = netdev_priv(dev);
0642 
0643     netif_stop_queue(dev);
0644     napi_disable(&bp->napi);
0645 
0646     if (dev->phydev)
0647         phy_stop(dev->phydev);
0648 
0649     dnet_reset_hw(bp);
0650     netif_carrier_off(dev);
0651 
0652     return 0;
0653 }
0654 
0655 static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
0656 {
0657     pr_debug("%s\n", __func__);
0658     pr_debug("----------------------------- RX statistics "
0659          "-------------------------------\n");
0660     pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
0661     pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
0662     pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
0663     pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
0664     pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
0665     pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
0666     pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
0667     pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
0668     pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
0669     pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
0670     pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
0671     pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
0672     pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
0673     pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
0674     pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
0675     pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
0676     pr_debug("----------------------------- TX statistics "
0677          "-------------------------------\n");
0678     pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
0679     pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
0680     pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
0681     pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
0682     pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
0683     pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
0684     pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
0685     pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
0686 }
0687 
0688 static struct net_device_stats *dnet_get_stats(struct net_device *dev)
0689 {
0690 
0691     struct dnet *bp = netdev_priv(dev);
0692     struct net_device_stats *nstat = &dev->stats;
0693     struct dnet_stats *hwstat = &bp->hw_stats;
0694 
0695     /* read stats from hardware */
0696     dnet_update_stats(bp);
0697 
0698     /* Convert HW stats into netdevice stats */
0699     nstat->rx_errors = (hwstat->rx_len_chk_err +
0700                 hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
0701                 /* ignore IGP violation error
0702                 hwstat->rx_ipg_viol + */
0703                 hwstat->rx_crc_err +
0704                 hwstat->rx_pre_shrink +
0705                 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
0706     nstat->tx_errors = hwstat->tx_bad_fcs;
0707     nstat->rx_length_errors = (hwstat->rx_len_chk_err +
0708                    hwstat->rx_lng_frm +
0709                    hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
0710     nstat->rx_crc_errors = hwstat->rx_crc_err;
0711     nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
0712     nstat->rx_packets = hwstat->rx_ok_pkt;
0713     nstat->tx_packets = (hwstat->tx_unicast +
0714                  hwstat->tx_multicast + hwstat->tx_brdcast);
0715     nstat->rx_bytes = hwstat->rx_byte;
0716     nstat->tx_bytes = hwstat->tx_byte;
0717     nstat->multicast = hwstat->rx_multicast;
0718     nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
0719 
0720     dnet_print_pretty_hwstats(hwstat);
0721 
0722     return nstat;
0723 }
0724 
0725 static void dnet_get_drvinfo(struct net_device *dev,
0726                  struct ethtool_drvinfo *info)
0727 {
0728     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0729     strlcpy(info->bus_info, "0", sizeof(info->bus_info));
0730 }
0731 
0732 static const struct ethtool_ops dnet_ethtool_ops = {
0733     .get_drvinfo        = dnet_get_drvinfo,
0734     .get_link       = ethtool_op_get_link,
0735     .get_ts_info        = ethtool_op_get_ts_info,
0736     .get_link_ksettings     = phy_ethtool_get_link_ksettings,
0737     .set_link_ksettings     = phy_ethtool_set_link_ksettings,
0738 };
0739 
0740 static const struct net_device_ops dnet_netdev_ops = {
0741     .ndo_open       = dnet_open,
0742     .ndo_stop       = dnet_close,
0743     .ndo_get_stats      = dnet_get_stats,
0744     .ndo_start_xmit     = dnet_start_xmit,
0745     .ndo_eth_ioctl      = phy_do_ioctl_running,
0746     .ndo_set_mac_address    = eth_mac_addr,
0747     .ndo_validate_addr  = eth_validate_addr,
0748 };
0749 
0750 static int dnet_probe(struct platform_device *pdev)
0751 {
0752     struct resource *res;
0753     struct net_device *dev;
0754     struct dnet *bp;
0755     struct phy_device *phydev;
0756     int err;
0757     unsigned int irq;
0758 
0759     irq = platform_get_irq(pdev, 0);
0760 
0761     dev = alloc_etherdev(sizeof(*bp));
0762     if (!dev)
0763         return -ENOMEM;
0764 
0765     /* TODO: Actually, we have some interesting features... */
0766     dev->features |= 0;
0767 
0768     bp = netdev_priv(dev);
0769     bp->dev = dev;
0770 
0771     platform_set_drvdata(pdev, dev);
0772     SET_NETDEV_DEV(dev, &pdev->dev);
0773 
0774     spin_lock_init(&bp->lock);
0775 
0776     bp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0777     if (IS_ERR(bp->regs)) {
0778         err = PTR_ERR(bp->regs);
0779         goto err_out_free_dev;
0780     }
0781 
0782     dev->irq = irq;
0783     err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
0784     if (err) {
0785         dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
0786                irq, err);
0787         goto err_out_free_dev;
0788     }
0789 
0790     dev->netdev_ops = &dnet_netdev_ops;
0791     netif_napi_add(dev, &bp->napi, dnet_poll, 64);
0792     dev->ethtool_ops = &dnet_ethtool_ops;
0793 
0794     dev->base_addr = (unsigned long)bp->regs;
0795 
0796     bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
0797 
0798     dnet_get_hwaddr(bp);
0799 
0800     if (!is_valid_ether_addr(dev->dev_addr)) {
0801         /* choose a random ethernet address */
0802         eth_hw_addr_random(dev);
0803         __dnet_set_hwaddr(bp);
0804     }
0805 
0806     err = register_netdev(dev);
0807     if (err) {
0808         dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
0809         goto err_out_free_irq;
0810     }
0811 
0812     /* register the PHY board fixup (for Marvell 88E1111) */
0813     err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
0814                      dnet_phy_marvell_fixup);
0815     /* we can live without it, so just issue a warning */
0816     if (err)
0817         dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
0818 
0819     err = dnet_mii_init(bp);
0820     if (err)
0821         goto err_out_unregister_netdev;
0822 
0823     dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
0824            bp->regs, (unsigned int)res->start, dev->irq, dev->dev_addr);
0825     dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n",
0826            (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
0827            (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
0828            (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
0829            (bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
0830     phydev = dev->phydev;
0831     phy_attached_info(phydev);
0832 
0833     return 0;
0834 
0835 err_out_unregister_netdev:
0836     unregister_netdev(dev);
0837 err_out_free_irq:
0838     free_irq(dev->irq, dev);
0839 err_out_free_dev:
0840     free_netdev(dev);
0841     return err;
0842 }
0843 
0844 static int dnet_remove(struct platform_device *pdev)
0845 {
0846 
0847     struct net_device *dev;
0848     struct dnet *bp;
0849 
0850     dev = platform_get_drvdata(pdev);
0851 
0852     if (dev) {
0853         bp = netdev_priv(dev);
0854         if (dev->phydev)
0855             phy_disconnect(dev->phydev);
0856         mdiobus_unregister(bp->mii_bus);
0857         mdiobus_free(bp->mii_bus);
0858         unregister_netdev(dev);
0859         free_irq(dev->irq, dev);
0860         free_netdev(dev);
0861     }
0862 
0863     return 0;
0864 }
0865 
0866 static struct platform_driver dnet_driver = {
0867     .probe      = dnet_probe,
0868     .remove     = dnet_remove,
0869     .driver     = {
0870         .name       = "dnet",
0871     },
0872 };
0873 
0874 module_platform_driver(dnet_driver);
0875 
0876 MODULE_LICENSE("GPL");
0877 MODULE_DESCRIPTION("Dave DNET Ethernet driver");
0878 MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
0879           "Matteo Vit <matteo.vit@dave.eu>");
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