ethernet/dlink/dl2k.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*  D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
0003 /*
0004     Copyright (c) 2001, 2002 by D-Link Corporation
0005     Written by Edward Peng.<edward_peng@dlink.com.tw>
0006     Created 03-May-2001, base on Linux' sundance.c.
0007
0008 */
0009
0010 #ifndef __DL2K_H__
0011 #define __DL2K_H__
0012
0013 #include <linux/module.h>
0014 #include <linux/kernel.h>
0015 #include <linux/string.h>
0016 #include <linux/timer.h>
0017 #include <linux/errno.h>
0018 #include <linux/ioport.h>
0019 #include <linux/slab.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/pci.h>
0022 #include <linux/netdevice.h>
0023 #include <linux/etherdevice.h>
0024 #include <linux/skbuff.h>
0025 #include <linux/crc32.h>
0026 #include <linux/ethtool.h>
0027 #include <linux/mii.h>
0028 #include <linux/bitops.h>
0029 #include <asm/processor.h>  /* Processor type for cache alignment. */
0030 #include <asm/io.h>
0031 #include <linux/uaccess.h>
0032 #include <linux/delay.h>
0033 #include <linux/spinlock.h>
0034 #include <linux/time.h>
0035 #define TX_RING_SIZE    256
0036 #define TX_QUEUE_LEN    (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
0037 #define RX_RING_SIZE    256
0038 #define TX_TOTAL_SIZE   TX_RING_SIZE*sizeof(struct netdev_desc)
0039 #define RX_TOTAL_SIZE   RX_RING_SIZE*sizeof(struct netdev_desc)
0040
0041 /* Offsets to the device registers.
0042    Unlike software-only systems, device drivers interact with complex hardware.
0043    It's not useful to define symbolic names for every register bit in the
0044    device.  The name can only partially document the semantics and make
0045    the driver longer and more difficult to read.
0046    In general, only the important configuration values or bits changed
0047    multiple times should be defined symbolically.
0048 */
0049 enum dl2x_offsets {
0050     /* I/O register offsets */
0051     DMACtrl = 0x00,
0052     RxDMAStatus = 0x08,
0053     TFDListPtr0 = 0x10,
0054     TFDListPtr1 = 0x14,
0055     TxDMABurstThresh = 0x18,
0056     TxDMAUrgentThresh = 0x19,
0057     TxDMAPollPeriod = 0x1a,
0058     RFDListPtr0 = 0x1c,
0059     RFDListPtr1 = 0x20,
0060     RxDMABurstThresh = 0x24,
0061     RxDMAUrgentThresh = 0x25,
0062     RxDMAPollPeriod = 0x26,
0063     RxDMAIntCtrl = 0x28,
0064     DebugCtrl = 0x2c,
0065     ASICCtrl = 0x30,
0066     FifoCtrl = 0x38,
0067     RxEarlyThresh = 0x3a,
0068     FlowOffThresh = 0x3c,
0069     FlowOnThresh = 0x3e,
0070     TxStartThresh = 0x44,
0071     EepromData = 0x48,
0072     EepromCtrl = 0x4a,
0073     ExpromAddr = 0x4c,
0074     Exprodata = 0x50,
0075     WakeEvent = 0x51,
0076     CountDown = 0x54,
0077     IntStatusAck = 0x5a,
0078     IntEnable = 0x5c,
0079     IntStatus = 0x5e,
0080     TxStatus = 0x60,
0081     MACCtrl = 0x6c,
0082     VLANTag = 0x70,
0083     PhyCtrl = 0x76,
0084     StationAddr0 = 0x78,
0085     StationAddr1 = 0x7a,
0086     StationAddr2 = 0x7c,
0087     VLANId = 0x80,
0088     MaxFrameSize = 0x86,
0089     ReceiveMode = 0x88,
0090     HashTable0 = 0x8c,
0091     HashTable1 = 0x90,
0092     RmonStatMask = 0x98,
0093     StatMask = 0x9c,
0094     RxJumboFrames = 0xbc,
0095     TCPCheckSumErrors = 0xc0,
0096     IPCheckSumErrors = 0xc2,
0097     UDPCheckSumErrors = 0xc4,
0098     TxJumboFrames = 0xf4,
0099     /* Ethernet MIB statistic register offsets */
0100     OctetRcvOk = 0xa8,
0101     McstOctetRcvOk = 0xac,
0102     BcstOctetRcvOk = 0xb0,
0103     FramesRcvOk = 0xb4,
0104     McstFramesRcvdOk = 0xb8,
0105     BcstFramesRcvdOk = 0xbe,
0106     MacControlFramesRcvd = 0xc6,
0107     FrameTooLongErrors = 0xc8,
0108     InRangeLengthErrors = 0xca,
0109     FramesCheckSeqErrors = 0xcc,
0110     FramesLostRxErrors = 0xce,
0111     OctetXmtOk = 0xd0,
0112     McstOctetXmtOk = 0xd4,
0113     BcstOctetXmtOk = 0xd8,
0114     FramesXmtOk = 0xdc,
0115     McstFramesXmtdOk = 0xe0,
0116     FramesWDeferredXmt = 0xe4,
0117     LateCollisions = 0xe8,
0118     MultiColFrames = 0xec,
0119     SingleColFrames = 0xf0,
0120     BcstFramesXmtdOk = 0xf6,
0121     CarrierSenseErrors = 0xf8,
0122     MacControlFramesXmtd = 0xfa,
0123     FramesAbortXSColls = 0xfc,
0124     FramesWEXDeferal = 0xfe,
0125     /* RMON statistic register offsets */
0126     EtherStatsCollisions = 0x100,
0127     EtherStatsOctetsTransmit = 0x104,
0128     EtherStatsPktsTransmit = 0x108,
0129     EtherStatsPkts64OctetTransmit = 0x10c,
0130     EtherStats65to127OctetsTransmit = 0x110,
0131     EtherStatsPkts128to255OctetsTransmit = 0x114,
0132     EtherStatsPkts256to511OctetsTransmit = 0x118,
0133     EtherStatsPkts512to1023OctetsTransmit = 0x11c,
0134     EtherStatsPkts1024to1518OctetsTransmit = 0x120,
0135     EtherStatsCRCAlignErrors = 0x124,
0136     EtherStatsUndersizePkts = 0x128,
0137     EtherStatsFragments = 0x12c,
0138     EtherStatsJabbers = 0x130,
0139     EtherStatsOctets = 0x134,
0140     EtherStatsPkts = 0x138,
0141     EtherStats64Octets = 0x13c,
0142     EtherStatsPkts65to127Octets = 0x140,
0143     EtherStatsPkts128to255Octets = 0x144,
0144     EtherStatsPkts256to511Octets = 0x148,
0145     EtherStatsPkts512to1023Octets = 0x14c,
0146     EtherStatsPkts1024to1518Octets = 0x150,
0147 };
0148
0149 /* Bits in the interrupt status/mask registers. */
0150 enum IntStatus_bits {
0151     InterruptStatus = 0x0001,
0152     HostError = 0x0002,
0153     MACCtrlFrame = 0x0008,
0154     TxComplete = 0x0004,
0155     RxComplete = 0x0010,
0156     RxEarly = 0x0020,
0157     IntRequested = 0x0040,
0158     UpdateStats = 0x0080,
0159     LinkEvent = 0x0100,
0160     TxDMAComplete = 0x0200,
0161     RxDMAComplete = 0x0400,
0162     RFDListEnd = 0x0800,
0163     RxDMAPriority = 0x1000,
0164 };
0165
0166 /* Bits in the ReceiveMode register. */
0167 enum ReceiveMode_bits {
0168     ReceiveUnicast = 0x0001,
0169     ReceiveMulticast = 0x0002,
0170     ReceiveBroadcast = 0x0004,
0171     ReceiveAllFrames = 0x0008,
0172     ReceiveMulticastHash = 0x0010,
0173     ReceiveIPMulticast = 0x0020,
0174     ReceiveVLANMatch = 0x0100,
0175     ReceiveVLANHash = 0x0200,
0176 };
0177 /* Bits in MACCtrl. */
0178 enum MACCtrl_bits {
0179     DuplexSelect = 0x20,
0180     TxFlowControlEnable = 0x80,
0181     RxFlowControlEnable = 0x0100,
0182     RcvFCS = 0x200,
0183     AutoVLANtagging = 0x1000,
0184     AutoVLANuntagging = 0x2000,
0185     StatsEnable = 0x00200000,
0186     StatsDisable = 0x00400000,
0187     StatsEnabled = 0x00800000,
0188     TxEnable = 0x01000000,
0189     TxDisable = 0x02000000,
0190     TxEnabled = 0x04000000,
0191     RxEnable = 0x08000000,
0192     RxDisable = 0x10000000,
0193     RxEnabled = 0x20000000,
0194 };
0195
0196 enum ASICCtrl_LoWord_bits {
0197     PhyMedia = 0x0080,
0198 };
0199
0200 enum ASICCtrl_HiWord_bits {
0201     GlobalReset = 0x0001,
0202     RxReset = 0x0002,
0203     TxReset = 0x0004,
0204     DMAReset = 0x0008,
0205     FIFOReset = 0x0010,
0206     NetworkReset = 0x0020,
0207     HostReset = 0x0040,
0208     ResetBusy = 0x0400,
0209 };
0210
0211 #define IPG_AC_LED_MODE     BIT(14)
0212 #define IPG_AC_LED_SPEED    BIT(27)
0213 #define IPG_AC_LED_MODE_BIT_1   BIT(29)
0214
0215 /* Transmit Frame Control bits */
0216 enum TFC_bits {
0217     DwordAlign = 0x00000000,
0218     WordAlignDisable = 0x00030000,
0219     WordAlign = 0x00020000,
0220     TCPChecksumEnable = 0x00040000,
0221     UDPChecksumEnable = 0x00080000,
0222     IPChecksumEnable = 0x00100000,
0223     FCSAppendDisable = 0x00200000,
0224     TxIndicate = 0x00400000,
0225     TxDMAIndicate = 0x00800000,
0226     FragCountShift = 24,
0227     VLANTagInsert = 0x0000000010000000,
0228     TFDDone = 0x80000000,
0229     VIDShift = 32,
0230     UsePriorityShift = 48,
0231 };
0232
0233 /* Receive Frames Status bits */
0234 enum RFS_bits {
0235     RxFIFOOverrun = 0x00010000,
0236     RxRuntFrame = 0x00020000,
0237     RxAlignmentError = 0x00040000,
0238     RxFCSError = 0x00080000,
0239     RxOverSizedFrame = 0x00100000,
0240     RxLengthError = 0x00200000,
0241     VLANDetected = 0x00400000,
0242     TCPDetected = 0x00800000,
0243     TCPError = 0x01000000,
0244     UDPDetected = 0x02000000,
0245     UDPError = 0x04000000,
0246     IPDetected = 0x08000000,
0247     IPError = 0x10000000,
0248     FrameStart = 0x20000000,
0249     FrameEnd = 0x40000000,
0250     RFDDone = 0x80000000,
0251     TCIShift = 32,
0252     RFS_Errors = 0x003f0000,
0253 };
0254
0255 #define MII_RESET_TIME_OUT      10000
0256 /* MII register */
0257 enum _mii_reg {
0258     MII_PHY_SCR = 16,
0259 };
0260
0261 /* PCS register */
0262 enum _pcs_reg {
0263     PCS_BMCR = 0,
0264     PCS_BMSR = 1,
0265     PCS_ANAR = 4,
0266     PCS_ANLPAR = 5,
0267     PCS_ANER = 6,
0268     PCS_ANNPT = 7,
0269     PCS_ANLPRNP = 8,
0270     PCS_ESR = 15,
0271 };
0272
0273 /* IEEE Extened Status Register */
0274 enum _mii_esr {
0275     MII_ESR_1000BX_FD = 0x8000,
0276     MII_ESR_1000BX_HD = 0x4000,
0277     MII_ESR_1000BT_FD = 0x2000,
0278     MII_ESR_1000BT_HD = 0x1000,
0279 };
0280 /* PHY Specific Control Register */
0281 #if 0
0282 typedef union t_MII_PHY_SCR {
0283     u16 image;
0284     struct {
0285         u16 disable_jabber:1;   // bit 0
0286         u16 polarity_reversal:1;    // bit 1
0287         u16 SEQ_test:1; // bit 2
0288         u16 _bit_3:1;   // bit 3
0289         u16 disable_CLK125:1;   // bit 4
0290         u16 mdi_crossover_mode:2;   // bit 6:5
0291         u16 enable_ext_dist:1;  // bit 7
0292         u16 _bit_8_9:2; // bit 9:8
0293         u16 force_link:1;   // bit 10
0294         u16 assert_CRS:1;   // bit 11
0295         u16 rcv_fifo_depth:2;   // bit 13:12
0296         u16 xmit_fifo_depth:2;  // bit 15:14
0297     } bits;
0298 } PHY_SCR_t, *PPHY_SCR_t;
0299 #endif
0300
0301 typedef enum t_MII_ADMIN_STATUS {
0302     adm_reset,
0303     adm_operational,
0304     adm_loopback,
0305     adm_power_down,
0306     adm_isolate
0307 } MII_ADMIN_t, *PMII_ADMIN_t;
0308
0309 /* Physical Coding Sublayer Management (PCS) */
0310 /* PCS control and status registers bitmap as the same as MII */
0311 /* PCS Extended Status register bitmap as the same as MII */
0312 /* PCS ANAR */
0313 enum _pcs_anar {
0314     PCS_ANAR_NEXT_PAGE = 0x8000,
0315     PCS_ANAR_REMOTE_FAULT = 0x3000,
0316     PCS_ANAR_ASYMMETRIC = 0x0100,
0317     PCS_ANAR_PAUSE = 0x0080,
0318     PCS_ANAR_HALF_DUPLEX = 0x0040,
0319     PCS_ANAR_FULL_DUPLEX = 0x0020,
0320 };
0321 /* PCS ANLPAR */
0322 enum _pcs_anlpar {
0323     PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
0324     PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
0325     PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
0326     PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
0327     PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
0328     PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
0329 };
0330
0331 typedef struct t_SROM {
0332     u16 config_param;   /* 0x00 */
0333     u16 asic_ctrl;      /* 0x02 */
0334     u16 sub_vendor_id;  /* 0x04 */
0335     u16 sub_system_id;  /* 0x06 */
0336     u16 pci_base_1;     /* 0x08 (IP1000A only) */
0337     u16 pci_base_2;     /* 0x0a (IP1000A only) */
0338     u16 led_mode;       /* 0x0c (IP1000A only) */
0339     u16 reserved1[9];   /* 0x0e-0x1f */
0340     u8 mac_addr[6];     /* 0x20-0x25 */
0341     u8 reserved2[10];   /* 0x26-0x2f */
0342     u8 sib[204];        /* 0x30-0xfb */
0343     u32 crc;        /* 0xfc-0xff */
0344 } SROM_t, *PSROM_t;
0345
0346 /* Ioctl custom data */
0347 struct ioctl_data {
0348     char signature[10];
0349     int cmd;
0350     int len;
0351     char *data;
0352 };
0353
0354 /* The Rx and Tx buffer descriptors. */
0355 struct netdev_desc {
0356     __le64 next_desc;
0357     __le64 status;
0358     __le64 fraginfo;
0359 };
0360
0361 #define PRIV_ALIGN  15  /* Required alignment mask */
0362 /* Use  __attribute__((aligned (L1_CACHE_BYTES)))  to maintain alignment
0363    within the structure. */
0364 struct netdev_private {
0365     /* Descriptor rings first for alignment. */
0366     struct netdev_desc *rx_ring;
0367     struct netdev_desc *tx_ring;
0368     struct sk_buff *rx_skbuff[RX_RING_SIZE];
0369     struct sk_buff *tx_skbuff[TX_RING_SIZE];
0370     dma_addr_t tx_ring_dma;
0371     dma_addr_t rx_ring_dma;
0372     struct pci_dev *pdev;
0373     void __iomem *ioaddr;
0374     void __iomem *eeprom_addr;
0375     spinlock_t tx_lock;
0376     spinlock_t rx_lock;
0377     unsigned int rx_buf_sz;     /* Based on MTU+slack. */
0378     unsigned int speed;     /* Operating speed */
0379     unsigned int vlan;      /* VLAN Id */
0380     unsigned int chip_id;       /* PCI table chip id */
0381     unsigned int rx_coalesce;   /* Maximum frames each RxDMAComplete intr */
0382     unsigned int rx_timeout;    /* Wait time between RxDMAComplete intr */
0383     unsigned int tx_coalesce;   /* Maximum frames each tx interrupt */
0384     unsigned int full_duplex:1; /* Full-duplex operation requested. */
0385     unsigned int an_enable:2;   /* Auto-Negotiated Enable */
0386     unsigned int jumbo:1;       /* Jumbo frame enable */
0387     unsigned int coalesce:1;    /* Rx coalescing enable */
0388     unsigned int tx_flow:1;     /* Tx flow control enable */
0389     unsigned int rx_flow:1;     /* Rx flow control enable */
0390     unsigned int phy_media:1;   /* 1: fiber, 0: copper */
0391     unsigned int link_status:1; /* Current link status */
0392     struct netdev_desc *last_tx;    /* Last Tx descriptor used. */
0393     unsigned long cur_rx, old_rx;   /* Producer/consumer ring indices */
0394     unsigned long cur_tx, old_tx;
0395     struct timer_list timer;
0396     int wake_polarity;
0397     char name[256];     /* net device description */
0398     u8 duplex_polarity;
0399     u16 mcast_filter[4];
0400     u16 advertising;    /* NWay media advertisement */
0401     u16 negotiate;      /* Negotiated media */
0402     int phy_addr;       /* PHY addresses. */
0403     u16 led_mode;       /* LED mode read from EEPROM (IP1000A only) */
0404 };
0405
0406 /* The station address location in the EEPROM. */
0407 /* The struct pci_device_id consist of:
0408         vendor, device          Vendor and device ID to match (or PCI_ANY_ID)
0409         subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
0410         class                   Device class to match. The class_mask tells which bits
0411         class_mask              of the class are honored during the comparison.
0412         driver_data             Data private to the driver.
0413 */
0414 #define CHIP_IP1000A    1
0415
0416 static const struct pci_device_id rio_pci_tbl[] = {
0417     {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
0418     {0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
0419     { PCI_VDEVICE(SUNDANCE, 0x1023), CHIP_IP1000A },
0420     { PCI_VDEVICE(SUNDANCE, 0x2021), CHIP_IP1000A },
0421     { PCI_VDEVICE(DLINK,    0x9021), CHIP_IP1000A },
0422     { PCI_VDEVICE(DLINK,    0x4020), CHIP_IP1000A },
0423     { }
0424 };
0425 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
0426 #define TX_TIMEOUT  (4*HZ)
0427 #define PACKET_SIZE     1536
0428 #define MAX_JUMBO       8000
0429 #define RIO_IO_SIZE             340
0430 #define DEFAULT_RXC     5
0431 #define DEFAULT_RXT     750
0432 #define DEFAULT_TXC     1
0433 #define MAX_TXC         8
0434 #endif              /* __DL2K_H__ */